Abstract: A semiconductor memory device that stores information includes: a flash memory that is managed by a predetermined file system having a parameter dependent on the semiconductor memory device; a rewrite frequency storage unit that stores a rewrite frequency of the flash memory; an ID detection unit that detects whether or not first identification information associated with the rewrite frequency is stored in the flash memory as the parameter; and a control unit that, when the ID detection unit detects that the first identification information is stored, reflects the rewrite frequency stored in the rewrite frequency storage unit, on a storage area corresponding to the first identification information.

Abstract: A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition.

Abstract: A storage device is configured to communicate with a host device over a Bluetooth connection. The storage device includes a flash memory, a processor, and a Bluetooth controller. The memory stores at least one permission for determining access to the memory. The processor manages access to the memory, independently of the host device, based on a comparison of a request at the removable storage device to access the memory to at least one permission. The comparison is independent, requiring no management by an operating system of the host device, such that if the at least one permission includes a particular access type that matches the access requested in the request, the processor provides access to the memory.

Abstract: A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold.

Abstract: A memory storage apparatus having a rewritable non-volatile memory module, a first circuit, a memory controller and a power management circuit is provided. The first circuit outputs a state signal and keeps the state signal in a first state when the first circuit is enabled, and then the first circuit keeps the state signal in a second state after a predetermined condition is satisfied. When the memory controller receives a first signal, the power management circuit stops supplying an output voltage to the rewritable non-volatile memory module and the memory controller. Additionally, when the memory controller is enabled, the memory controller determines whether the state signal is in the first state. If true, the memory controller performs a first procedure; and if not, the memory controller performs a second procedure.

Abstract: Methods and structure for transferring additional parameters through a communication interface with limited parameter passing features. Features and aspects hereof provide for generating and transmitting multiple related commands from an initiator device to a target device where one or more initial commands provide additional parameters. The additional parameters are utilized in processing the last of the multiple commands to actually perform a desired data transfer. The initial commands and the data transfer command may all be associated by encoding of a common tag or sub-tag value in each command. The initial commands may be read/write commands having a zero data transfer length. The associated data transfer command may be a read/write command having a non-zero data transfer length. The initial commands each provide one or more additional parameters for processing the data transfer command in addition to the standard parameters that may be encoded in the data transfer command.

Abstract: Storage locations in a first tier of a multi-tier storage system are allocated to a first set of data structures (e.g., inodes) in a first file set. A file that is stored in the first tier is associated with a first data structure of the first set. In response to determining that data in the file should be moved to a second tier of the multi-tier storage system, the file is associated with a second data structure in a second file set. The second data structure is allocated a storage location in the second tier. Consequently, two data structures are associated with the file. The data is copied from the first tier to the storage location in the second tier, and can be subsequently accessed using the second data structure.

Abstract: A memory management method for a rewritable non-volatile memory module including physical unit unions is provided. The physical unit unions are at least partitioned into a data area and a second area. Logical unit union addresses are managed by a file system and would be allocated and mapped to the physical unit unions of the data area. The method includes executing a procedure if a programming error occurs when programming a third physical unit union of the second area. The procedure includes obtaining a second physical unit union mapped to a second logical unit union address from the data area and mapping the second logical unit union address to the third physical unit union. Accordingly, the lifespan of the rewritable non-volatile memory module would be prolonged by the method.

Abstract: An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid.

Abstract: A method, apparatus, and a storage system are provided for implementing enhanced indirection update for indirected storage devices. A novel remapping command generated by a host is used to store indirection data. The remapping command enables remapping of a set of Logical Block Addresses (LBAs) to a different set of LBAs. The remapping command includes a source LBA, length and a destination LBA.

Abstract: A memory system includes a nonvolatile memory area including a first area in which write-in and read-out actions on data are performed and a second area in which such actions are prohibited, first and second interfaces, and a controller configured to connect to a second host using a first wireless communication configuration when the controller determines a second wireless communication configuration to connect to the second host device is not retained in the first area, the controller controlling the first interface in so that the first host device writes data into the memory area on a basis of a command provided from the second host device. When the controller changes the first wireless communication configuration, the controller connects to the second host device using the second wireless communication configuration, and the first interface notifies an error to the first host device not to write data into the memory area.

Abstract: In an embodiment, a non-volatile memory has erasable blocks of memory cells. The one or more of the erasable blocks include a particular block to be identified by a particular group of logical block addresses corresponding to a predetermined group of sectors.

Abstract: A data writing method for a rewritable non-volatile memory module containing physical blocks is provided. The method includes: configuring virtual block address to map to at least a part of the logical blocks; receiving a write command which instructs to write file data to the first virtual block addresses, and the first virtual block addresses are mapped to first logical blocks of the at least the part of the logical blocks. The method further includes: writing the file data into the physical blocks mapped to a plurality of second logical blocks; determining whether a program failure is occurred during the writing period; and if the program failure is not occurred, the first virtual block addresses are remapped to the second logical block. Accordingly, the method can ensure the update completeness of the file data.

Abstract: A method and apparatus manages a buffer cache. An extended buffer is used to perform a page replacement algorithm using reference time information regarding a time at which a page is referred. Pages replaced through the page replacement algorithm, when re-referred to, may be retrieved from the extended buffer, instead of a hard disk. As a result, write/read operations with respect to the disk are made efficient and the page input/output speed is increased.

Abstract: A storage management system decouples application write requests from write requests to a flash-based storage device. By placing a layer of software intelligence between application requests to write data and the storage device, the system can make more effective decisions about when and where to write data that reduce wear and increase performance of the storage device. An application has a set of performance characteristics and writes data with a frequency that is appropriate for the application, but not necessarily efficient for the hardware. By analyzing how data is being used by an application, the system can strategically place data in the storage device or even avoid using the storage device altogether for some operations to minimize wear. One technique for doing this is to create an in-memory cache that acts as a buffer between the application requests and the storage hardware.

Abstract: A NAND flash memory chip has a configurable interface that can communicate with a NAND flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels. Control information from the NAND flash memory controller uses a small number of channels. Double Data Rate (DDR) communication provides serial communication with adequate data transfer speed.

Abstract: Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.

Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.

Abstract: A system for supporting multiple authentication systems. The system includes a computing device, a host memory for storing a plurality of software stacks, a flash memory configured to be programmed with one of the plurality of software stacks, and at least one processor. The at least one processor is programmed to identify a model of the device, select a software stack from the plurality of software stacks based on a device model of the computing device, and program the selected software stack into the flash memory. The device may be an electrical appliance.

Abstract: A data protecting method for a rewritable non-volatile memory module having physical blocks is provided, a plurality of logical block addresses is mapped to a part of the physical blocks. The method includes, configuring a plurality of virtual block addresses to map to the logical block addresses, grouping at least one virtual block address into a virtual block address area, and allocating the virtual block address area to an application. The method also includes, receiving an access command which is configured to instruct accessing a first virtual block address from the application. The method also includes: determining whether the first virtual block address belongs to the virtual block address area, if not, sending an error message to the application. Accordingly, the method can effectively prevent an application from accessing the data which can not be accessed by the application program.

Abstract: A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received.

Abstract: The device controller (a) executes a data I/O process with respect to a physical storage area in accordance with an I/O command, and (b) sends to the storage controller an I/O command-related response comprising status information subsequent to being changed in accordance with the I/O process. The storage controller (A) receives the response from the target physical storage device, and (B) based on the status information included in the response received in (A), makes a determination as to whether or not to execute internal processing, and in a case where the result of the determination is to execute internal processing, sends to the target physical storage device an internal processing execution command instructing the execution of internal processing. The device controller in the target physical storage device (c), upon receiving the internal processing execution command, executes internal processing in accordance with the internal processing execution command.

Abstract: A storage subsystem contains multiple non-volatile memory arrays that are accessible to a host system when the storage subsystem is connected thereto. The storage subsystem implements commands and/or modes for enabling the host system to create and use backup copies of files, such that the host system can recover when files become corrupted or otherwise lost. In one embodiment, the storage subsystem presents the non-volatile memory arrays to the host's operating system as distinct storage devices (e.g., ATA device 0 and 1), and implements special commands for copying data between these storage devices. The subsystem may alternatively present the memory arrays to the host operating system as a single storage device. The storage subsystem may have a standard form factor, such as a form factor commonly used for memory cards.

Abstract: A nonvolatile storage device includes a nonvolatile memory that stores data and a memory controller that controls the nonvolatile memory. The memory controller accepts a pause instruction to pause writing from the access device within a period in which data from the access device are written, and writes the data received from the access device to the nonvolatile memory within a predetermined time interval, then pauses the writing and accepts read and/or write of new data from the access device.

Abstract: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: Provided are a computer program product, system, and method for using different secure erase algorithms to erase chunks from a file associated with different security levels. A request is received to secure erase a file having a plurality of chunks stored in at least one storage device. A determination is made of a first secure erase algorithm to apply to a first chunk in the file in response to the request and of a second secure erase algorithm to apply to a second chunk in the file in response to the request. The first secure erase algorithm is applied to erase the first chunk and the second secure erase algorithm is applied to erase the second chunk. The first and second secure erase algorithms use different processes to erase the chunks to which they are applied.

Abstract: One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage.

Abstract: Data frames, such as Controller Access Network frames, that are to be programmed into a FLASH memory device, are sent from a programming station to a target device via a relatively high-speed bus and stored temporarily at the target device in numbered frame buffers. Each frame carries a payload. Before a frame is sent, an identifier is assigned to it, or an identifier is appended to the frame. The identifier identifies a particular buffer in the target device where the frame is to be stored in the target device until the target device is able to process the frame and write its payload into a FLASH memory device.

Abstract: A data writing method for a memory storage device having physical unit unions is provided, wherein each of the physical unit unions includes upper physical units and lower physical units. The method includes partitioning the physical unit unions into a storage area including a data area and a spare area; configuring logical units for mapping to the physical unit unions of the data area; and receiving update data from a host system. The method also includes: selecting several physical unit unions from the spare area as buffer physical unit unions; writing the update data only to a part of each of the buffer physical unit unions; and moving the update data from buffer physical unit unions to the storage area by using a copy procedure. Therefore, the time of performing a write command can be shorten and the lifespan of the memory storage device can be prolonged effectively.

Abstract: Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory. Features and aspects hereof provide an enhanced storage controller having a volatile cache memory and multiple communication channels each coupled with a corresponding nonvolatile memory device. Responsive to detecting an impending loss of power, control logic of the controller copies data from the volatile cache memory to the multiple nonvolatile memories using the multiple communication channels operating substantially in parallel. Using multiple parallel channels and nonvolatile memory substantially temporally overlapping their operations assures that the cached data can be saved to nonvolatile memory before the controller is inoperable due to power loss. A simple “file system” and error detection and correction codes on the nonvolatile memory help assure that the saved data is valid for return to the volatile memory when power is restored to the controller.

Abstract: Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

Abstract: A data writing method for writing data into a physical block of a rewritable non-volatile memory module is provided. The method includes setting danger distance respectively corresponding to each of the physical pages of the physical block, and setting a secure writing flag in an enable state in response to a secure write command. The method also includes determining whether the secure writing flag is set in the enable state when receiving a write command and updated data thereof; if no, writing the updated data into a predetermined physical page of the physical block; if yes, writing the updated data into a secure physical page of the physical block and re-setting the secure writing flag in a disable state, and the distance between the secure physical page and the predetermined physical page is equal to the danger distance corresponding to the predetermined physical page.

Abstract: According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block.

Abstract: A hybrid drive and associated methods increase the rate at which data are transferred to a nonvolatile storage medium in the hybrid drive. By using a large nonvolatile solid state memory device as cache memory for a magnetic disk drive, a very large number of write commands can be cached and subsequently reordered and executed in an efficient manner. In addition, strategic selection and reordering of only a portion of the write commands stored in the nonvolatile solid state memory device increases efficiency of the reordering process.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

Abstract: A method or system comprising iteratively updating a value of an operating parameter of a storage region of a storage device based on dynamic characterization of the storage region during operation of the storage device and using the updated value of the operating parameter during access to the storage region.

Abstract: Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

Abstract: Methods and apparatuses for performing deduplication in a hybrid storage aggregate are provided. In one example, a method includes operating a hybrid storage aggregate that includes a plurality of tiers of different types of physical storage media. The method includes identifying a first storage block and a second storage block of the hybrid storage aggregate that contain identical data and identifying caching statuses of the first storage block and the second storage block. The method also includes deduplicating the first storage block and the second storage block based on the caching statuses of the first storage block and the second storage block.

Abstract: A burning system includes an indentifying module, a dividing module, a calculating module, an index module, and a burning module. The identifying module identifies bad blocks of the flash memory. The dividing module reads all blocks of the flash memory in sequence, and when one or more continuous blocks being read are bad blocks, groups the bad blocks and the previously read good block as a storage sector. The calculating module calculates a bad block ratio of each storage sector. The index module assigns a priority level to each storage sector according to the bad block ratio of the storage sector, and associates each priority level of the storage sectors with a start address. The burning module accesses the storage sectors in an order of the priority levels of the storage sectors, and begins writing programs into the storage sectors from the associated start addresses.

Abstract: Systems and methods are disclosed for heuristics associated with programming data in a non-volatile memory (“NVM”). One or more applications can generate information that notifies a system of the amounts of recoverable and unrecoverable new data that will be programmed to an NVM. Based on this information, the system can calculate the amount of new data that needs to be placed in a bulk mode instead of a SLC mode. By utilizing multi-modal modes of an NVM effectively, the system can improve overall performance and reduce the probability of unnecessary garbage collection.

Abstract: An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.

Abstract: Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

Abstract: An information processing apparatus includes an execution unit that executes a program, a main storage unit that includes a first non-volatile memory which is readable and writable and is capable of retaining stored information even when no power is supplied and is provided with a first storage area which stores the program executed by the execution unit and a second storage area which stores data generated by the execution of the program by the execution unit, a connection unit that connects the execution unit and the main storage unit, and a condition storage unit that includes a second non-volatile memory which is readable and writable and is capable of retaining stored information even when no power is supplied and stores conditions which are set by the connection unit to transmit and receive the program and the data between the execution unit and the main storage unit.

Abstract: Using integrated circuits, such as field programmable gate arrays, it is possible to transfer data to common off the shelf storage devices at high speeds which would normally be associated with special purpose hardware created for a particular application. Such high speed storage can include prefetching data to be stored from a memory element into a cache, and translating the commands which will be used in accomplishing the transfer into a standard format, such as peripheral component interconnect express.

Abstract: Various embodiments of the present disclosure are generally directed to the accessing of data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a transfer command is received to transfer selected data between a control module and a memory module. The transfer command specifies a target address in the memory module and a sense threshold vector associated with the selected data. The sense threshold vector in the received transfer command is used to sense a programmed state of at least one solid-state memory cell at the target address responsive to the received transfer command. The transfer command may be a read or write command.

Abstract: An apparatus having a memory circuit and a manager is disclosed. The memory circuit generally has (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses. The manager may be configured to (i) receive data items in a random order from one or more applications, (ii) write the data items in an active one of a plurality of regions in a memory circuit and (iii) mark the memory addresses in the active region that store the data items as used. Each data item generally has a respective host address. The applications may be executed in one or more computers. The memory addresses in the active region may be accessed in a sequential order while writing the data items to minimize a write amplification. The random order is generally preserved between the data items while writing in the active region.