Abstract: A data writing method for a multi-level cell (MLC) NAND flash memory and a storage system and a controller using the same are provided. The flash memory includes a plurality of blocks. Each of the blocks includes a plurality of page addresses. The page addresses are categorized into a plurality of upper page addresses and a plurality of lower page addresses. The writing speed of the lower page addresses is faster than that of the upper page addresses. The data writing method includes receiving a writing command and data and writing the data into a page address. The page address is skipped when it is an upper page address and a corresponding lower page address stores a valid data written by a previous writing command. Thereby, the accuracy of the data written by the previous writing command is ensured when a programming error occurs to the flash memory.

Abstract: A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.

Abstract: A technique for achieving consistent read latency from an array of non-volatile solid-state memories involves an external entity determining the “busy” or “not busy” status of non-volatile solid-state memory elements in a RAID group. An external data layout engine then uses parity based RAID data reconstruction to avoid having to read from any memory element that is busy in a RAID group, along with careful scheduling of writes and erasures.

Abstract: A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency.

Abstract: A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device).

Abstract: A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory.

Abstract: Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

Abstract: The subject disclosure is directed towards a multi-tiered cache having cache tiers with different access properties. Objects are written to a selected a tier of the cache based upon object-related properties and/or cache-related properties. In one aspect, objects are stored in an active log among a plurality of logs. The active log is sealed upon reaching a target size, with a new active log opened. Garbage collecting is performed on a sealed log, such as the sealed log with the most garbage therein.

Abstract: A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a CPU; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory. Thereby, the engine is accessing the data from each table in parallel to significantly reduce the total operation time.

Abstract: A computer system includes one or more field programmable gate arrays as a coprocessor that can be shared among processes and programmed using hardware libraries. Given a set of hardware libraries, an update process periodically updates the libraries and/or adds new libraries. One or more update servers can provide information about libraries available for download, either in response to a request or by notifying systems using such libraries. New available libraries can be presented to a user for selection and download. Requests for updated libraries can arise in several ways, such as through polling for updates, exceptions from applications attempting to use libraries, and upon compilation of application code.

Abstract: A data storing method for a rewritable non-volatile memory module is provided. The method includes dividing logical addresses into a plurality of logical zones, and respectively establishing a plurality of logical address mapping tables for the logical zones. The method also includes writing data of a logical address into a physical program unit; and recording a mapping record indicating the logical address is mapped to the physical program unit in a temp mapping table. The method further includes: if the temp mapping table is full, updating the mapping relations between the logical addresses and the physical program units in the logical address mapping tables based on mapping records recorded in the temp mapping table, and deleting the mapping records in the temp mapping table.

Abstract: A data writing method for controlling a rewritable non-volatile memory module having a plurality of physical erase units is provided. The method includes: receiving a write command which instructs writing data to a first logical address, wherein the first logical address is mapped to a second physical erase unit; determining whether the second physical erase unit is in a sequential writing state which represents that the physical programming units over a predetermined ratio in the second physical erasing unit have been successively written sequentially within a predetermined time; if yes, writing the data into a third physical erasing unit in a first programming mode, wherein the first programming mode represents that a plurality of upper physical programming units are non-programmable. Accordingly, the data writing rate is increased.

Abstract: An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes.

Abstract: A RAID system to transfer data to and from host equipment includes a semiconductor storage unit, a semiconductor-memory selector, and a memory controller. The semiconductor storage unit includes two or more semiconductor memories, a mounting board, and solder joints. The semiconductor memories are mounted on the mounting board. The solder joints are between the semiconductor memories and the mounting board. The semiconductor-memory selector selects a combination of the semiconductor memories to dispersively record the data in the semiconductor storage unit. The memory controller accesses the combination in response to a request of the host equipment. In addition, the selector selects the combination so that mechanical loads received by the semiconductor memories are averaged.

Abstract: A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern.

Abstract: Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.

Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: A method for constructing an address mapping table of a solid state drive is provided. The address mapping table is stored in a non-volatile memory of the solid state drive. The method includes the following steps. After the solid state drive is powered on, a command from a host is received. Then, a logical allocation address is calculated according to a logical block address corresponding to the command. Then, the calculated logical allocation address is defined as an initial address, and a specified number of logical allocation addresses starting from the initial address and corresponding physical allocation addresses are loaded into a cache memory, so that a first portion of the address mapping table is constructed into the cache memory. Afterwards, the solid state drive responds the command according to the first portion of the address mapping table.

Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: The invention relates to a method for programming and/or diagnosis of a memory-programmable controller, having at least one memory-programmable function component. For programming, a predetermined programming system is used. In the context of this programming system variables are predetermined, and information exchange sequences are used for the programming. Results of the programming are output during at least one programming mode via an output device, and input information is at least in part stored permanently in memory.

Abstract: One or more embodiments are directed a solid state storage device for maintaining versions of data. The solid state storage device comprises a processor and a solid state memory communicatively coupled to the processor. A flash translation layer receives at least one request from a file system to write at least one dataset to a logical page of the solid state memory. At least one physical page in a data block of the solid state memory associated with the logical page is identified. At least one dataset in the physical page is stored. At least one data versioning tag is associated with the dataset in a data structure associated with the logical page. The data versioning tag identifies the dataset as a given version of the logical page. The dataset is maintained as accessible from the physical page irrespective of subsequent write operations to the logical page.

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations with respect to the area of the cache.

Abstract: One or more embodiments are directed a solid state storage device for maintaining versions of data. The solid state storage device comprises a processor and a solid state memory communicatively coupled to the processor. A flash translation layer is configured to perform a method comprising creating at least one data structure associated with at least one logical page of the solid state memory. The logical page is associated with at least one physical page in a data block of the solid state memory. A first set of information associated with the logical page is stored in the data structure. A second set of information associated with the physical page is stored in the data structure. The second set of information comprises at least versioning information identifying which version of the logical page is represented by a dataset stored within the physical page.

Abstract: One or more embodiments are directed to managing data in a solid state memory supporting data versioning. A file system reserves a plurality of logical pages from a solid state memory. Each logical page in the plurality of logical pages is associated with a plurality of physical pages in the solid state memory. Each logical page in the plurality of logical pages is assigned to one group in a plurality of groups. A request is sent to a flash translation layer for an operation to be performed by the flash translation layer on a group in the plurality of groups.

Abstract: A method of initializing a non-volatile memory system is disclosed. System data are written to a non-volatile memory based on a formula rule at a factory, and a number of copies of the system data are written to the non-volatile memory. The system data are searched in the non-volatile memory according to the formula rule and a selected data access mode. At least one operating parameter of the selected data access mode is reconfigured, followed by checking if the searched system data are successfully read. The system data are utilized to set the at least one operating parameter of the non-volatile memory system when the searched system data are successfully read from the non-volatile memory.

Abstract: A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache.

Abstract: One or more embodiments are directed to managing data in a solid state memory supporting data versioning. A file system residing at an information processing system reserves a plurality of logical pages from a solid state memory. Each logical page in the plurality of logical pages is associated with a plurality of physical pages in the solid state memory. Each logical page in the plurality of logical pages is assigned to one group in a plurality of groups. A request is sent to a flash translation layer for an operation to be performed by the flash translation layer on a group in the plurality of groups.

Abstract: A method for recovering from an interruption during a Firmware Over-The-Air (FOTA) update is provided. The method includes identifying a missing block of a plurality of blocks to be updated in the first memory, the missing block corresponding to a block being updated when the interruption occurred, copying a backup block into a backup buffer, simulating an application of the FOTA update in a second memory, the simulation including, for each block of the plurality of blocks to be updated, performing a reversible operation on the contents of the backup buffer and an updated block, and updating the backup buffer with the operation result, replacing the missing block with the updated backup buffer, and resuming the FOTA update.

Abstract: The present invention provides a computer system comprising a server and a storage system having a compression function, wherein the server includes a control unit and a cache, and the storage system has a storage area provided by a plurality of storage devices. When a designated data of a received read request is stored in the cache, the control unit of the server returns the stored data as a response to the read request, and when the designated data is not stored in the cache, the control unit acquires the designated data compressed via the compression function and stored in the storage area in the compressed state from the storage system, decompresses the acquired compression data, and returns the same as a response to the read request.

Abstract: A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.

Abstract: The present invention discloses a data storage system using a solid state disk to replace a non-volatile memory. The data storage system comprises a plurality of controllers, a first storage unit and a second storage unit. The plurality of controllers are electrically connected with each other, and are capable of storing data into said storage units and restoring data from said storage units. When a controller receives the data transmitted from a remote device, a data journal is generated and stored into the first storage unit. After a message of “successfully received” is sent back to the remote device, the data is transferred to the second storage unit.

Abstract: A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. A disk subsystem and data restoration method whereby, when the power of the disk subsystem is shut off, the shared memory management table is saved to non-volatile memory together with the cache data and, when the power of the disk subsystem is restored, the shared memory management table is referenced and the duplex data is assigned by two non-volatile memories and restored to each of two shared memories.

Abstract: A memory management method adapted to a rewritable non-volatile memory module having a plurality of physical erase units is provided. The operation mode of each physical erase unit is set to include three modes. A first mode indicates all physical program units to be programmable, a second mode and a third mode indicate upper physical program units to be non-programmable, but the third mode is unswitchable to the first or the second mode. The physical erase units are grouped into a first area and a second area. Each physical erase unit in the first area switchably operates in the first or the second mode, and each physical erase unit in the second area operates in the third mode. If a condition is satisfied, a physical erase unit in the first area is grouped to the second area. Thereby, the lifespan of the rewritable non-volatile memory module is prolonged.

Abstract: One or more embodiments are directed to managing data in a solid state memory supporting data versioning. At least one request to perform an operation on at least one logical page of a solid state memory is received from a file system. A data structure associated with the at least one logical page is identified. The data structure at least identifies one or more physical pages associated with the at least one logical page, and a version of the at least one logical page represented by a dataset stored in each of the one or more physical pages. The operation is performed on the at least one logical page based on the data structure that has been identified.

Abstract: One or more embodiments are directed to maintaining versions of data within a solid state memory. At least one request to perform an operation on at least one logical page of a solid state memory is received from a file system. A data structure associated with the at least one logical page is identified. The data structure at least identifies one or more physical pages associated with the at least one logical page, and a version of the at least one logical page represented by a dataset stored in each of the one or more physical page. The operation is performed on the at least one logical page based on the data structure that has been identified.

Abstract: Various embodiments are directed to maintaining versions of data within a solid state memory. At least one request to write at least one dataset to a logical page of a solid state memory is received from a file system. At least one physical page in a data block of the solid state memory associated with the logical page is identified. A processor stores the dataset in the at least one physical page. At least one data versioning tag is associated with the at least one dataset in a data structure associated with the logical page. The data versioning tag identifies the at least one dataset as a given version of the logical page. The at least one dataset is maintained as accessible from the at least one physical page irrespective of subsequent write operations to the logical page in response to associating the at least one data versioning tag.

Abstract: Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.

Abstract: Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“NVM”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the NVM. In some embodiments, the host can track the read behavior of a particular application over a period of time. As a result, the host can maintain heuristics of logical sectors that are most frequently read together. The host can then notify the NVM to pre-fetch data that the application will most likely request at some point in the future. These notifications can take the form of non-data transfer read commands. Each non-data transfer read commands can include a flag bit that is set to indicate that no data transfer is desired.

Abstract: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.

Abstract: A smart data storage apparatus and data transmitting method for the same are to combine the hard disk with the dual interface memory, and are to use radio frequency identification (RFID) technology or near field communication (NFC) technology. The information of the self-monitoring analysis and reporting technology (SMART) of the hard disk still could be received by the handheld device without the power for the hard disk. Moreover, the external hard disk could be registered with the handheld device quickly.

Abstract: A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.

Abstract: Methods, storage controllers, and systems for grouping data stored on an array of solid-state storage elements are described. One method includes sequentially writing user data to an append point at a head of a log stored in an array of solid-state storage elements. The user data is stored in a plurality of logical erase blocks of the array. The method further includes selecting partially invalidated logical erase blocks of the array based on a characteristic for the partially invalidated logical erase blocks and arranging valid portions of the selected partially invalidated logical erase blocks into groups based on the characteristic. The method further includes writing the groups of valid portions to the log.

Abstract: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a first hash value associated with a first set of data stored in a memory is compared to a second hash value associated with a second set of data pending storage to the memory. The second set of data is stored in the memory responsive to a mismatch between the first and second hash values.

Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.

Abstract: A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank.

Abstract: An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request.

Abstract: Systems and methods for efficiently using solid-state devices are provided. Some embodiments provide for a data processing system that uses a non-volatile solid-state device as a circular log, with the goal of aligning data access patterns to the underlying, hidden device implementation, in order to maximize performance. In addition, metadata can be interspersed with data in order to align data access patterns to the underlying device implementation. Multiple input/output (I/O) buffers can also be used to pipeline insertions of metadata and data into a linear log. The observed queuing behavior of the multiple I/O buffers can be used to determine when the utilization of the storage device is approaching saturation (e.g., in order to predict excessively-long response times). Then, the I/O load on the storage device may be shed when utilization approaches saturation. As a result, the overall response time of the system is improved.

Abstract: A memory system for digital data communication with a host device is described to provide data storage capacity. The system can include a controller and a plurality of modules, each module including a nonvolatile memory device wherein the module is configured to perform a management function with respect to the module at least partially based on a parameter. The parameter is provided by the controller and/or the module. The system and modules, in one feature, can support multiple forms of concurrency with respect to data accesses involving the modules.

Abstract: Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.

Abstract: A data stream dispatching method for a memory storage apparatus having a non-volatile memory module and a smart card chip is provided. The method includes configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses is used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit into a buffer memory. The method further includes when a logical block address corresponding to a read command issued by a host system is one of the specific logical block addresses and the response data unit is stored in the buffer memory, transmitting the response data unit to the host system by aligning an access unit. Thereby, the host system can correctly receive the response data unit from the smart card chip.