Abstract: A digital still camera performs temporary high-speed writing when capturing a large number of images in a short time. Lengthy processing for erased block allocation or copying performed inside a nonvolatile storage device may disable the captured images to be written completely (may cause some frames to drop). A nonvolatile storage system includes an access device (1001) and a nonvolatile storage device (1002). A button operation of a user on the access device (1001) causes the mode of data writing to the nonvolatile storage device (1002) to be switched. Temporary high-speed writing is performed into a physical block of a nonvolatile memory (27) from which a plurality of data pieces with different logical addresses and different data sizes have been erased. After the temporary high-speed writing, the written data is relocated into a user storage area (272), and an erased block is newly allocated for subsequent temporary high-speed data writing.

Abstract: A method for managing redundancy of data in a solid-state cache system including at least three solid-state storage modules. The method may include designating one or more extents of each dirty mirror pair to be of a particular priority order of at least two priority orders. The at least two priority orders can include at least a highest priority order. The highest priority order can have a higher relative priority than the other priority orders. The method may also include performing at least one redundancy conversion iteration. Each redundancy conversion iteration includes converting extents of at least two dirty mirror pairs into at least one RAID 5 group and at least one unconverted extent. The extents of the at least two dirty mirror pairs can include extents designated to be of a highest remaining priority order. Each redundancy conversion iteration can also include deallocating the at least one unconverted extent.

Abstract: A method of data collection is performed in a non-volatile memory that has a number of blocks and each block has multiple pages. A timestamp is recorded associated with a data written to the non-volatile memory. Some of the written data are moved from a plurality of different pages respectively to a first block according to the timestamps associated with the plurality of written data stored in the plurality of different pages.

Abstract: A data storing method and a memory controller and a memory storage apparatus using the same are provided. The method includes logically grouping physical erase units into a data area and a spare area; selecting a physical erase unit form the spare area as a first data collecting unit; and selecting a physical erase unit from the spare area as a second data collecting unit. The method also includes writing data received from a host into the first data collecting unit. The method further includes performing a data arranging operation to move valid data in a third physical erase unit to the second data collecting unit and associating the third physical erase unit with the spare area. Accordingly, the method can effectively enhance the performance of the write operation.

Abstract: A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.

Abstract: Exemplary embodiments provide information processing system and data processing for efficient I/O processing in the storage system. In one aspect, a storage system comprises: a memory; and a controller being operable to execute a process for data stored in the memory so that an address of the data stored in the memory is changed between a first address managed in a virtual memory on a server and a second address managed by the controller, based on a command containing an address corresponding to the first address, the command being sent from the server to the storage system. In some embodiments, the memory includes a server data memory and a storage data memory. In specific embodiments, in response to the command from the server, the controller is operable to change a status of data stored in the memory from server data to storage data or from storage data to server data.

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract: According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.

Abstract: A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory.

Abstract: Data storage devices and methods are disclosed that provide a status indication when a maintenance operation is to be performed prior to completion of a write command. A method includes receiving a write command from a host device to write data to the non-volatile memory while the data storage device is operatively coupled to the host device. In response to determining that a maintenance operation is to be performed prior to the completion of the write command, an indication is sent to the host device that the write command has a status of incomplete.

Abstract: A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.

Abstract: Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract: A device for aggregating flash modules includes a switch to connect to a plurality of servers and a midplane to connect to a plurality of flash modules. The switch and midplane are connected such that the switch can route data traffic to any of the plurality of flash modules, and the plurality of servers can connect to the plurality of flash modules transparently, as if a flash module was directly installed into a server.

Abstract: A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit.

Abstract: Provided is a semiconductor storage device having a first interface section meeting a USB standard for connection to host equipment, a NAND memory section that is a first semiconductor memory section, a second interface section to which small memory cards can be connected, each small memory card having a second semiconductor memory section, and a controller capable of controlling the NAND memory section and the second semiconductor memory sections by one linear address.

Abstract: A virtual non-volatile memory is simulated for a virtual switch. Operating instructions from the non-volatile memory of a physical switch may be translated into a flash type file. The flash type file may be stored on a virtual storage area in the virtual switch. Operating instructions in the virtual switch may access the flash type file in the virtual storage area without the need to access the non-volatile memory in the physical switch.

Abstract: A method for conducting memory transactions includes receiving a transaction. The steps of the received transaction are performed in a memory buffer. A state of the memory buffer cache lines is set as pending and unstored while the transaction is in progress. After all steps have been successfully performed, the state of the memory buffer cache lines are changed to complete and unstored. When it is determined that the memory buffer cache lines are to be written to the non-volatile main memory, the contents is written to the non-volatile main memory. The state of the memory buffer cache lines are then changed to complete and stored. When the memory buffer cache lines are in the complete and unstored state, access to modify their content is restricted.

Abstract: A memory system may include an optimized data compaction algorithm. The compaction may include transferring only valid data from a source block to a destination block. A compaction bitmap that is maintained in random access memory (“RAM”) may be populated during the compaction process. The populated bitmap may be used to copy valid fragments to the destination block.

Abstract: A system and method for changing a state of a binary flag in a flash memory. The method defines a cell segment including a predetermined number of bits as the binary flag, where each bit is converted to a logical 1 when the memory is erased. The method also defines that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity, and defines whether an even parity is an ON state of the binary flag or an odd parity is the ON state of the binary flag. The method changes the parity of the binary flag by writing one of the bits in the flash cell segment from a logical 1 to a logical 0 to change the state of the flag.

Abstract: A virtual EEPROM driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual EEPROM driver. The virtual EEPROM driver may be duplicated into a non-volatile memory providing availability during a boot process.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: Systems and methods that may be implemented to utilize the same portion of solid state nonvolatile memory for both managing system running data during a system working state and to store previous working state data written from system volatile memory during a low power state when the system volatile memory is depowered. The previous working state information may include data and instructions that may be employed to restore the previous working state of the information handling system prior to entering the low power state and terminating power to the system volatile memory.

Abstract: A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.

Abstract: Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.

Abstract: A method of storing system data, and a memory controller and a memory storage apparatus using the same are provided. The method includes determining whether the unused storage space of a system physical erase unit is enough for storing updated system data. The method further includes, if the unused storage space of the system physical erase unit is not enough for storing the updated system data, selecting an empty physical erase unit, writing the updated system data into at least one first physical program unit of the selected physical erase unit and writing dummy data into a second physical program unit of the selected physical erase unit.

Abstract: A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.

Abstract: An apparatus for measuring a remaining power of a battery unit includes a first memory unit, a second memory unit, and a processor. The first memory unit stores a first program code. The second memory unit stores a second program code. The second memory unit is accessed at a second speed that is lower than a first speed at which the first memory unit is accessed. The processor is utilized for reading the first program code from the first memory unit to execute calculation for current of the battery unit during a normal operation mode and reading the second program code from the second memory unit to execute an exception during the normal operation mode if required.

Abstract: A nonvolatile memory (“NVM”) buffer can be incorporated into an NVM system between a volatile memory buffer and an NVM to decrease the size of the volatile memory buffer and organize data for programming to the NVM. Heterogeneous data paths may be used for write and read operations such that the nonvolatile memory buffer is used only in certain situations.

Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.

Abstract: Various flash management techniques may be described. An apparatus may comprise a processor, a flash memory coupled to the processor, and a flash management module. The flash management module may be executed by the processor to receive a write request to write data to the flash memory, write a first control sector with a sequence number to the flash memory, and write the sequence number, an address for a logical sector, and data to at least one physical sector corresponding to the logical sector of the flash memory. Other embodiments are described and claimed.

Abstract: A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed.

Abstract: A method includes receiving one or more storage commands and at least one flush command in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory. The flush command instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory. The storage commands are executed in accordance with a first storage rule. The flush command is executed in accordance with a second storage rule having smaller latency relative to the first storage rule.

Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.

Abstract: A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units on the second memory device less than a number of available storage units on the first memory device.

Abstract: An access device 100 includes an access speed information part 112 for informing an access speed required for data recording by the access device 100 to a nonvolatile memory device 200. The nonvolatile memory device includes an access condition determination part 212 for determining an access condition required for meeting the informed access speed and an access area determination unit 213 for determining an access area according to the determined access condition. The access device 100 informs the required access speed to the nonvolatile memory device 200 in advance so that the access condition determination part 212 and the access area determination part 213 in the nonvolatile memory device 200 realize data recording which meets the access speed informed in advance upon the data recording. Thus, it is possible to access all the nonvolatile memory devices at a desired speed regardless of difference in characteristics of the recording speed of each of the nonvolatile memory devices.

Abstract: In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory and a controller. The flash memory is used for data storage. The controller receives write data and a write logical address from the host, calculates a running sum value according to the write data, determines whether target data with a running sum equal to the running sum value is stored in the flash memory, reads the target data from the flash memory when the target data is stored in the flash memory, determines whether the target data is identical to the write data, and records a mapping relationship between an original logical address of the target data and a write logical address of the write data in a remapping table without writing the write data to the flash memory when the target data is identical to the write data.

Abstract: A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a Physical Entry to Logical (PE2L) mapping table stored in a SRAM; updating a Physical Entry (PE) status table; checking if the PE2L mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the PE2L mapping table and update the PE status table, and then run next step; transferring part of the PE2L mapping table to a Logical to Physical (L2P) mapping table stored in the non-volatile storage device; and programming the L2P mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the PE2L mapping table and updating the PE status table.

Abstract: Method and apparatus for managing data in a memory, such as but not limited to a flash memory. In accordance with some embodiments, a memory is provided with a plurality of addressable data storage blocks which are arranged into a first set of garbage collection units (GCUs). The blocks are rearranged into a different, second set of GCUs responsive to parametric performance of the blocks.

Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

Abstract: A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second data storage segment having a second physical address and associates the second physical address with the logical address and the file identifier. When a file delete request for the file is received, the controller identifies the first physical address and the second physical address using the file identifier and erases the information stored at the first data storage segment and the second data storage segment based upon the file identification.

Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

Abstract: The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

Abstract: A memory address translation method for flash storage system is disclosed. There are two level mapping tables to reduce overhead of mapping table management. In level-one mapping table, each entry contains two kinds of information, which one is the validation of this entry, called Valid Mark and the other is the location of level-two mapping. The level-one mapping table is always located on RAM, and never saved into flash memory. In level-two mapping table, each entry contains two kinds of information, which one is the validation of this entry and the other is the physical location of data in flash memory. The physical addresses of both data and level-two mapping table are dynamically determined. Level-two mapping table is loaded to RAM when it is needed to reference, and is saved into flash memory periodically if the content is updated.

Abstract: A user device includes a flash memory configured to store an index including a plurality of index nodes and a controller configured to control the flash memory. The controller is configured to detect a pointer ID corresponding to a selected key of a first index node, translate the detected pointer ID to an index address by using a pointer table, and access a second index node corresponding to the selected key by using the index address.

Abstract: A storage apparatus and its control method capable of implementing thin provisioning and reducing power consumption of storage devices are provided. The storage apparatus classifies a plurality of storage devices, which provide a pool with a storage resource, into a plurality of groups; performs thin provisioning operation by setting some of the plurality of groups to an active mode, in which the storage devices belonging to the groups are made to enter an activated state; sets other groups to a power-saving mode in which the storage devices are made to enter a power-saving state; and sequentially switches between the group(s) in the active mode and the group(s) in the power-saving mode among the plurality of groups.

Abstract: An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence.