Abstract: An apparatus and method for reorganizing mapping information in a flash memory are provided. The apparatus includes a sector-managing module that secures a mapping sector where mapping information is recorded in a physical unit, and determines whether user data is recorded up to a sector located in a predetermined position, and a mapping-information-recording module that records the mapping information in the mapping sector according to a result of the determination. Here, the mapping information includes a relation of a physical sector storing the user data and a logical sector corresponding to the physical sector.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

Abstract: A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.

Abstract: A non-volatile memory apparatus includes non-volatile memory having a user block and a reserved block, a first connector for connecting to a host device, at least one second connector for connecting to a storage medium, and a first controller connected to the non-volatile memory, the first connector and the at least one second connector. Memory blocks of the storage medium are used as extra reserved blocks for the non-volatile memory apparatus. The first controller controls and remaps the user blocks and reserved blocks of the non-volatile memory, and the memory blocks of the storage medium.

Abstract: A data storage device is coupled to a host and includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein a spare block count indicates a total number of the spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the spare block count is less than a spare block count threshold when the current programming page is the first page, and sets data move information for a data merge process when the spare block count is less than the spare block count threshold.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller determines a minimum erase count from the erase counts of the spare blocks and the data blocks, adds a first difference to the minimum erase count to obtain a jail threshold, compares the erase counts of the spare blocks with the jail threshold to obtain a plurality of jail blocks with the erase counts greater than the jail threshold, and confines the jail blocks to a jail pool.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a plurality of flash memory areas and a controller. Each of the flash memory areas comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, selects a target memory area to which the target data is to be written from the flash memory areas, sets a physical address range parameter according to the target memory area, sets a spare block pool parameter according to the target memory area, and writes the target data to a current data block of the target memory area.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current programming data block, determines whether a current programming page is a first page of the current programming data block, determines whether data move information is set when the current page is not the first page, and when the data move information is set, perform a data move process according to the data move information within a limited time period.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current data block, and determines whether the current data block is full. When the current data block is full, the controller updates at least one table according to the information of the current data block.

Abstract: A system includes a serial interface, a peripheral device coupled to the serial interface, non-volatile memory, and a DMA controller including multiple linked channels. The various channels can be configured in different modes to facilitate the DMA controller performing various operations, such as data transfer, with respect to the non-volatile memory or the peripheral device.

Abstract: A data storage includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the hot spare block count is greater than zero when the current programming page is the first page, and sets data move information for a wear-leveling process when the hot spare block count is greater than zero.

Abstract: An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.

Abstract: A file protecting method and system and a memory controller and a memory storage apparatus using the same are provided. The file protecting method includes performing a file protection enabling procedure for a file to generate an entry value backup according to at least one entry value corresponding to at least one cluster storing the file, which is recorded in a file allocation document, store the entry value backup in a secure storage area and change the entry value corresponding to the cluster storing the file in the file allocation document, wherein the file cannot be read according to the changed entry value. Accordingly, the file stored in the memory storage apparatus the can be effectively protected from being accessed by an un-authorized person.

Abstract: A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.

Abstract: A storage unit management method for managing a plurality of physical units in a rewritable non-volatile memory module is provided, wherein the physical units are at least grouped into a data area and a spare area. The method includes configuring a plurality of logical units for mapping to the physical units belonging to the data area, and determining whether the rewritable non-volatile memory module contains cold data. The method further includes performing a first wear-leveling procedure on the physical units if it is determined that the rewritable non-volatile memory module does not contain any cold data, and performing a second wear-leveling procedure on the physical units if it is determined that the rewritable non-volatile memory module contains the cold data.

Abstract: A nonvolatile storage device buffers multiple write commands and selects one or more therefrom according to a choosing policy to execute in priority, so as to increase the probability of continuously executing write commands corresponding to an identical smallest erasable unit, thereby reducing the frequency of backup, erasing and copyback operations and improving the efficiency of the nonvolatile storage device.

Abstract: A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data.

Abstract: Systems and methods for providing early hinting to nonvolatile memory charge pumps are disclosed. Charge pumps associated with one or more nonvolatile memory dies can be proactively activated based on a determination that a command queue of access requests contains at least a threshold number of consecutive access requests of the same type. Based on analysis of the command queue, the memory controller can transmit an early hint command to a nonvolatile memory die to proactively activate its charge pump to provide a voltage suitable for executing the consecutive access requests of the same type.

Abstract: A storage system comprises multiple memory packages and a storage controller. The multiple memory packages respectively comprise multiple nonvolatile semiconductor memory devices for storing data, and a memory controller for controlling the reading/writing of data from/to these multiple semiconductor memory devices, and the storage controller receives an I/O command issued from a host computer, creates, on the basis of the received I/O command, a first level command for controlling the multiple memory packages, and sends this first level command to the multiple memory packages. The memory controllers of the multiple memory packages create a second level command for the multiple nonvolatile semiconductor memory devices inside its own memory package, and estimate the power to be consumed in its own memory package. In a case where the estimated power consumption exceeds a preconfigured permissible power, suspends the execution of the received second level command.

Abstract: In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.

Abstract: Relatively small capacity solid-state storage devices (SSD) are combined with larger capacity magnetic disk storage devices for storing storage block write data to ensure data consistency. Write operations are stored in a sequential write buffer in an SSD to guarantee the storage of write data and then copied from the sequential write buffer to the destination address in a magnetic disk storage device. The sequential write buffer store write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the magnetic disk storage device in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, the most recent value of the checkpoint index is retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage device.

Abstract: A peripheral device includes a first memory, a second memory, a first access controller, a second access controller and a main controller. When accessing data, first data is written to the first memory from the main controller while second data is read from the second memory to the main controller. Then the first data is written from the first memory to the second memory after writing the first data to the first memory and reading the second data from the second memory are completed.

Abstract: Solid-state storage devices (SSD) are combined with larger capacity magnetic disk-based RAID arrays for storing write data to ensure data consistency across multiple RAID disks. Write operations are stored in a sequential write buffer in at least one SSD to guarantee their storage and then copied from the sequential write buffer to the destination address in RAID array. The sequential write buffer stores write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the RAID array in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, a copy of the sequential write buffer and its associated checkpoint index are retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage devices in the RAID array.

Abstract: A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board.

Abstract: An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device. The storage device may allocate logical capacity in the logical address space. An allocation request may be allowed when there is sufficient unassigned and/or unallocated logical capacity to satisfy the request. Data may be stored on the non-volatile storage device by requesting physical storage capacity. A physical storage request, such as a storage request or physical storage reservation, when there is sufficient available physical storage capacity to satisfy the request. The device may maintain an index to associate logical identifiers (LIDs) in the logical address space with storage locations on the storage device. This index may be used to make logical capacity allocations and/or to manage physical storage space.

Abstract: A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: Dynamic allocation of memory in a hybrid system is provided. In particular, a method and system is provided to leverage a hybrid infrastructure for dynamic memory allocation and persistent file storage. The method includes dynamically allocating a file or its part or to cache a file or its part between different storage technologies and respective memory technologies in a hybrid infrastructure.

Abstract: A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.

Abstract: A method comprises sending a first command to a solid state drive (SSD), the first command indicating that the SSD can de-allocate a first plurality of logical block addresses (LBAs), and calculating first parity data for a redundant array of independent disks (RAID) array that includes the SSD in response to receiving a first reply from the SSD indicating that the first LBAs were de-allocated by the SSD. The first parity data is calculated based upon the first LBAs including all logical zeros.

Abstract: Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption.

Abstract: Embodiments of the present invention provide an approach for Dynamic Random Access Memory (DRAM) and flash converged memory and storage. Specifically, in a typical embodiment, at least one substrate will be provided on which a DRAM unit and flash memory unit are positioned. A set (e.g., one or more of input/outputs (I/Os)) may be provided for the units. Such a set of I/Os may communicate storage and/or memory access requests to a set (e.g., one or more) of controllers, which control the DRAM and flash memory units. The set of controllers may comprise a single integrated controller or multiple controllers having separate and distinct functions (e.g., a memory controller, a storage controller, a DRAM controller, a flash controller, etc.).

Abstract: Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.

Abstract: A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.

Abstract: Mechanisms identify one or more first storage devices in a first tier of the tiered storage system that may be placed in a minimal power consumption state and identify one or more data segments stored on the one or more first storage devices that are most likely to be accessed during a period of time in which the one or more first storage devices are in the minimal power consumption state. The mechanisms migrate the one or more data segments to one or more second storage devices in one of the first tier or a second tier of the storage system and place the one or more first storage devices in the minimal power consumption state. Access requests to the one or more data segments are serviced by the one or more second storage devices while the one or more first storage devices are in the minimal power consumption state.

Abstract: An I/O scheduler and a method for scheduling I/O requests to a solid-state drive (SSD) is disclosed. The I/O scheduler in accordance with the present disclosure bundles the write requests in such a form that the write requests in each bundle goes into one SSD block. Bundling the write requests in accordance with the present disclosure reduces write amplification and increases system performance. The I/O scheduler in accordance with the present disclosure also helps increasing the life of the SSDs.

Abstract: A memory formatting method adapted to a memory storage apparatus is provided. The memory formatting method includes configuring a plurality of logical block addresses to be mapped to a portion of a plurality of physical blocks, generating a first file system data and a second file system data according to the size of the logical block addresses, and storing the first file system data into a first physical block, and the first physical block is mapped to a first logical block address among the logical block addresses. The memory formatting method also includes selecting a second physical block among the physical blocks, storing the second file system data into the second physical block, determining whether a format command is received, and when the format command is received, re-mapping the first logical block address to the second physical block.

Abstract: A data storage device includes a memory, a controller, a first module, a first interface, and a second interface. The first interface and the second interface are coupled to the controller. The controller is used to access data in the memory, the first module is used to perform a first predetermined function. The second interface is inaccessible to the first module. The first interface may gain access to at least one additional module in the data storage device to perform at least one additional predetermined function which the second interface may not gain access to and may not perform.

Abstract: A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory.

Abstract: A nonvolatile memory system includes a memory card (102) and host equipment (101). The memory card (102) includes a nonvolatile memory (106) including a plurality of physical blocks, and a memory controller (105) for writing data into the nonvolatile memory (106). The host equipment (101) provides to the memory card (102) an access instruction that designates a logical address and a channel number. The memory controller (105) has an address conversion function for converting the logical address into a physical address in the nonvolatile memory (106), a write destination determination function for determining in relation to the channel number a physical address in the nonvolatile memory (106) to which the data is to be written, and a channel management function for individually managing for each channel number a write state in which data of a smaller size than each physical block is written.

Abstract: An automobile MP3 system for an automobile is provided. The automobile MP3 system comprises a data storage device mounted within the automobile, the data storage device having memory for holding content and content downloading capability. The data storage device stores music and other content.

Abstract: The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings.

Abstract: A method for selectively placing cache data, comprising the steps of (A) determining a line temperature for a plurality of devices, (B) determining a device temperature for the plurality of devices, (C) calculating an entry temperature for the plurality of devices in response to the cache line temperature and the device temperature and (D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.

Abstract: A memory system or flash card may include an algorithm for identifying a pattern in a sustained or continuous write operation. In one example, a video recording device may be a host that continuously writes data to a memory card in an identifiable pattern. The pattern identification algorithm may be stored in the firmware of the memory card and used to schedule background operations during the predicted idle times in which the host is not writing data to the memory card.

Abstract: Various techniques of solid-state drive (“SSD”) management systems, components, modules, routines, and processes are described in this application. In one embodiment, a management engine for controlling a solid-state drive includes an input interface configured to receive a target operation profile from an input source. The management engine also includes a process component g configured to receive the target operation profile from the input interface, retrieve an operating policy from a database based on the target operation profile, and determine operating parameters for the SSD based on the retrieved operating policy. The management engine further includes a device interface coupled to the process component, the device interface being configured to transmit the determined operating parameters to the SSD for controlling operation of the SSD.

Abstract: A system operation method for controlling a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of physical blocks. The system operation method includes following steps. A first signal is received from a host system through a host interface. Whether a system setting of the host interface is to be modified is determined. If the system setting is to be modified, a system parameter is read from the physical blocks, and the system setting is modified according to the system parameter. A second signal is transmitted to the host system to establish a connection recognition between the rewritable non-volatile memory module and the host system. Thereby, the settings of transmission between the host system and the rewritable non-volatile memory module are made more flexible.

Abstract: A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory, proactively preventing fragmentation by only writing an amount of sequentially addressed logical groups of data into a main storage area of the storage device, such as multi-level cell (MLC) flash memory, and reactively defragmenting data previously written into the MLC memory when a trigger event is reached. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for minimum sequential writes into MLC, and for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data already in MLC into new MLC blocks, may be fixed or variable.

Abstract: A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips.