Abstract: A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits.

Abstract: A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract: A storage apparatus includes a flash memory, a second memory for storing an address translation table, and a control section. The flash memory is formed of multiple pages, each having a spare area, and data are stored on a page-by-page basis. The control section has the functions of: saving the table to the flash memory; when writing/updating data, storing the user data, recording, in the table, a correspondence between a logical page address and an address of a page in which the data is stored, and storing information for identifying the corresponding logical page address in the spare area of the page; when the apparatus is started, detecting pages to which data was written after the most recent saving of the table; and scanning the spare area of each page detected and reproducing a state of the table as updated after the most recent saving to reconstruct the table.

Abstract: A method and a corresponding apparatus provide for remapping for wear leveling of a memory. The method is implemented as logic and includes the steps of receiving a memory operation, the memory operation including a logical memory address; dividing the logical address into a logical block address portion, a logical line address portion, and a logical subline address portion; translating the logical block address portion into a physical block address; selecting a line remap key; applying the line remap key to the logical line address portion to produce a physical line address; producing a physical subline address portion; and combining the physical block, line, and subline address portions to produce a physical address for the memory operation.

Abstract: A file system-aware SSD management system including an SSD management module that incorporates both file system information and information related to the underlying physical solid-state storage media into its operations is described. Also described are related methods for performing data management operations in a file system-aware manner. By incorporating both file system and physical storage information, the system may achieve various advantages over conventional systems, such as enhanced I/O performance, simplified SSD firmware, and extended SSD lifespan. Moreover, by moving solid-state management functions above the firmware level, the system may enable the simultaneous management of a pool of multiple SSDs.

Abstract: The invention discloses a method for storing data and a device of implementing the same. The method comprises receiving a request for storing data sent by a user and storing the data to an SSD according to the received request. The device comprises a request receiving module used to receive the request storing data and an SSD storage module used to store the data to an SSD according to the received request. The invention ensures consistency of data storage by storing data to an SSD according to the received request, thereby reducing data redundancy caused by using a cache layer to cache the data in the prior art. Additionally, the use of a single layer of an SSD to store data avoids the need of reloading data in the cache layer once a machine is power-down, thereby reducing the complexity of system design and the cost of operation and maintenance.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit stores management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of the management information in a latest state and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

Abstract: A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.

Abstract: A method and system for page preloading using a control flow are provided. The method includes extracting preload page information from one or more pages in a first program code, and generating a second program code including the first program code and the extracted preload page information. The second program code is stored in non-volatile memory. When loading a page from the second program code stored in the non-volatile memory into main memory, preloading one or more pages from the non-volatile memory based on the preload page information stored in the loaded page.

Abstract: A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals.

Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.

Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.

Abstract: Described are embodiments of methods, apparatus, and systems for detecting incompressible data and selectively compressing compressible data without compressing the incompressible data. A method may include determining a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, determining that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold, and compressing the second data of the plurality of input data. Other embodiments may be described and claimed.

Abstract: A low power write journaling storage system may be part of an information handling system that includes a system processor and a system memory that is coupled to the system processor. The low power write journaling storage system is coupled to the system processor and includes a non-volatile solid state memory system. A first processing element in the low power write journaling storage system is operable, while the storage system is in a storage system first mode, to journal write commands in the non-volatile solid state memory system. A second processing element in the low power write journaling storage system is operable, while the storage system is in a storage system second mode that may cause the low power write journaling storage system to consume more power than when in the storage system first mode, to execute the write commands journaled in the non-volatile solid state memory system.

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract: Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects.

Abstract: A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided.

Abstract: A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory.

Abstract: A system and method for tuning a solid state disk memory includes computing a metric representing a usage trend of a solid state disk memory. Whether one or more parameters need to be adjusted to provide a change in performance is determined. The parameter is adjusted in accordance with the metric to impact the performance of running workloads. These steps are repeated after an elapsed time interval.

Abstract: Different FTL implementations, including the use of different mapping schemes, log block utilization, merging, and garbage collection strategies, perform more optimally than others for different data operations with certain characteristics. The presently claimed invention provides a method to distinguish and categorize the different data operations according to their different characteristics, or data attributes; then deploy the most optimal mapping schemes, log block utilization, merging, and garbage collection strategies depending on the data attributes; wherein the data attributes include, but are not limited to, access frequency, access sequence, access size, request mode, and request write ratio.

Abstract: A memory controller that generates interface signals for a memory device determines an interface signal frequency based on a timing mode of the memory device and a corresponding clock division ratio. Based on the timing mode, a look up table (LUT) is selected and then a timing parameter corresponding to the clock division ratio and the interface signal frequency is fetched from the LUT. An interface signal is generated based on the interface signal frequency and fetched timing parameter.

Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Abstract: An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.

Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata are stored in a memory. The metadata are arranged as a first sequence of snapshots of the metadata at different points in time during the operation of the memory, and a second sequence of intervening journals which reflect updates to the metadata from one snapshot to the next. Requested portions of the metadata are recovered from the memory using a selected snapshot in the first sequence and first and second journals in the second sequence.

Abstract: A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data.

Abstract: A method of programming a nonvolatile memory device comprises generating write data and metadata associated with the write data, generating a seed associated with the write data and scrambling the generated seed, randomizing the write data and the metadata using the scrambled seed, and programming the randomized write data, the randomized metadata, and the scrambled seed in the nonvolatile memory device.

Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined.

Abstract: Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency.

Abstract: A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.

Abstract: A terminal apparatus including a non-volatile memory for which writing is performed in units of blocks; and a control unit configured to perform a first method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to an information management table in a file system of the non-volatile memory, and to perform a second method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to user data in the file system.

Abstract: In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device.

Abstract: Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM.

Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Abstract: A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment. An original/initial identifier may be generated from the information read from the memory segment. The original/initial identifier may then be stored in a non-volatile storage of the processor. On subsequent startups of the processor, it verifies that the processor is still coupled to the same external volatile memory device by using the stored identifier. For instance, on a subsequent startup, the processor again reads the same memory segment of the external memory device and generates a new identifier. If the identifier matches the previously stored identifier, then the processor may continue its operations; otherwise the processor is disabled/halted.

Abstract: A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (L-Pages), each associated with an L-Page number that enables the controller to logically reference data stored in the physical pages. A volatile memory may comprise a logical-to-physical address translation map that enables the controller to determine a physical location, within the physical pages, of data stored in each L-Page. The controller may be configured to maintain, in the memory devices, journals defining physical-to-logical correspondences, each journal covering a predetermined range of physical pages and comprising a plurality of entries that associate one or more physical pages to each L-Page. The controller may read the journals upon startup and rebuild the address translation map from the read journals.

Abstract: A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.

Abstract: A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: A data merging method for merging valid data of one logical block in a rewritable non-volatile memory module is provided. The method includes assigning a plurality of log physical blocks for the logical block. The method also includes performing a data arrangement operation and a data move operation with a partial synchronization manner to copy the valid data of the logical block into the lower physical pages of the log physical blocks from a first data physical block and at least one spare physical block while programming the valid data of the logical block into a second data physical block from the lower physical pages of the log physical blocks in units of each physical page group. The method further includes remapping the logical block to the second physical block. Accordingly, the method can effectively shorten the time of merging valid data and improving the reliability of data writing.

Abstract: A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page.

Abstract: The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

Abstract: A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.

Abstract: A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor.

Abstract: In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.

Abstract: Systems and methods to manage memory on a dual in-line memory module (DIMM) are provided. A particular method may include receiving at a flash application-specific integrated circuit (ASIC) a request from a processor to access data stored in a flash memory of a DIMM. The data may be transferred from the flash memory to a switch of the DIMM. The data may be routed to a dynamic random-access memory (DRAM) of the DIMM. The data may be stored in the DRAM and may be provided from the DRAM to the processor.

Abstract: A method includes, in a storage device that includes a non-volatile memory and a volatile memory, maintaining at least one data structure that stores management information used for managing data storage in the non-volatile memory, such that at least a portion of the data structure is stored in the volatile memory. A sequence of journaling chunks is created during operation of the storage device, each journaling chunk including a respective slice of the data structure and one or more changes that occurred in the data structure since a previous journaling chunk in the sequence. The sequence of the journaling chunks is stored in the non-volatile memory. Upon recovering from an electrical power interruption in the storage device, the data structure is reconstructed using the stored journaling chunks.

Abstract: Systems and methods may provide for securely transferring data from a flash component. In one example, the method may include receiving a download request from an embedded controller chip, obtaining information from the flash component in response to the download request, and transferring the information to the embedded controller chip.

Abstract: In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device.