Using Page Tables, E.g., Page Table Structures, Etc. (epo) Patents (Class 711/E12.059)
  • Patent number: 9009445
    Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventor: Jesse Pan
  • Patent number: 9009446
    Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an electrical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the electrical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the electrical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: April 14, 2015
    Assignee: Oracle International Corporation
    Inventors: Pranay Koka, David A. Munday, Michael O. McCracken, Herbert D. Schwetman, Jr.
  • Patent number: 9009395
    Abstract: The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor receives a write request from a host computer and data D1 to D3 exist in a cache slot, the microprocessor reads the LBA of each piece of the data, manages each piece of the data D1 to D3 using a bitmap table by associating them with their LBAs, generates a specific command CMD based on the LBAs of the data D1 to D3, adds the data D1 to D3 and addresses ADD1 to ADD3 indicating where the data D1 to D3 are to be stored, to the specific command CMD, and sends it to an FMPK. The FMPK stores each piece of update data in a specified block in the flash memory based on the specific command CMD.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiki Kano, Masanori Takada, Akira Yamamoto, Akihiko Araki, Masayuki Yamamoto, Jun Kitahara, Sadahiro Sugimoto
  • Patent number: 8996842
    Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 31, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Gaertner, Mark Alan Heath
  • Patent number: 8990541
    Abstract: A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adekunle Bello, Douglas Griffith, Angela Astrid Jaehde, Srinivasa Muppala Rao
  • Patent number: 8990542
    Abstract: A method for protecting page-level metadata in a storage system is provided. The method includes providing in a page table first protection data, receiving a command to read data from a page of the storage system corresponding to the page table, and comparing first protection data to second protection data. If the first protection data is different than the second protection data, then the method includes identifying third protection data in the storage system and comparing the third protection data to the first protection data. If the third protection data is different than the first protection data, then the method includes determining that the page-level metadata is inconsistent.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Dot Hill Systems Corporation
    Inventor: Ian Robert Davies
  • Patent number: 8990476
    Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. The write look ahead information can include information about the location where data would have next been written to a memory system.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 8966198
    Abstract: In general, one aspect of the subject matter described in this specification can be embodied in methods that include receiving, at a computer system, a request to create a snapshot of a virtual storage device, wherein the virtual storage device virtually stores data at virtual addresses, the data being physically stored at a plurality of physical storage locations that are managed by an underlying storage system associated with virtual storage device; the methods can further include identifying, by the computer system, one or more regions of the virtual storage device that have been written to since a previous snapshot of the virtual storage device was created; the methods can additionally include generating a unique identifier for the requested snapshot; and creating the requested snapshot using the identified one more regions and the unique identifier.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 24, 2015
    Assignee: Google Inc.
    Inventors: Matthew S. Harris, Andrew Kadatch, Sergey Khorun, Carl Hamilton
  • Patent number: 8966157
    Abstract: A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping a plurality of physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring a plurality of logical units for mapping a part of the physical units. The method further includes receiving at least two pieces of update data, which are corresponding to different logical pages of the logical units. The method further includes getting a physical unit from the physical units. The method further includes writing the at least two pieces of update data into the same one physical page of the gotten physical unit. Accordingly, the use efficiency of the physical units could be improved.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: February 24, 2015
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8959302
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8954710
    Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: February 10, 2015
    Assignee: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller
  • Patent number: 8954707
    Abstract: A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Gheith, Eric Van Hensbergen, James Xenidis
  • Patent number: 8898407
    Abstract: A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes taking a snapshot of a physical volume with a native snapshot program, determining which blocks have changed since a previous snapshot with a change block tracker, creating a child virtual container, populating the child virtual container with the changed blocks, and linking the child virtual container with a parent virtual container.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 25, 2014
    Assignee: EMC Corporation
    Inventors: Shankar Balasubramanian, Vladimir Mandic, Sriprasad Bhat Kasargod, Anand Raj
  • Patent number: 8892847
    Abstract: The storage apparatus comprises a storage unit storing data read/written by the host apparatus, and a control unit controlling writing of the data to the storage unit. The control unit configures one or more pools from the storage unit and divides one of the pools into first pages having an area of a first size and divides the first pages into second pages having the second area, and manages the pages, manages a data storage area of a first volume storing the data by using the first-size area and manages a data storage area of a second volume storing the data by using the second-size area, assigns the first page to the data storage area of the first volume, and assigns the first page in units of the second volume and assigns the second page obtained by dividing the first page to the data storage area of the second volume.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Miho Imazaki, Yusuke Nonaka
  • Patent number: 8868865
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8862854
    Abstract: The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: October 14, 2014
    Inventors: Ramachandran Vaidyanathan, Matthew Jordan
  • Patent number: 8856490
    Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel, Martin Ohmacht, Burkhard Steinmacher-Burow
  • Patent number: 8838875
    Abstract: A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the host to the data storage device for one or more files stored thereon. The file delete command may specify a logical address and data to be invalidated associated with the deleted file. The data storage device may identify one or more units of memory allocation in the erase before write memory as containing invalid data based on the specified logical address and data to be invalidated. The data storage device may maintain a data structure that associates physical addresses for units of memory allocation in the erase before write memory with indications of whether the units of memory allocation contain invalid data. The data structure may be used to mark units of memory allocation associated with deleted files as containing invalid data.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Ik Park
  • Patent number: 8838922
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8793467
    Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 29, 2014
    Assignee: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller
  • Patent number: 8782338
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 8775776
    Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, John J. Reilly
  • Patent number: 8751724
    Abstract: Embodiments of the present invention provide a method, system and computer program product for dynamic main memory reconfiguration in virtual memory management. In an embodiment of the invention, a method for dynamic main memory reconfiguration in virtual memory management can include receiving a memory access directive in a host computer, determining a low free space condition in a memory allocation to satisfy the memory access directive, augmenting the memory allocation with a mapping to additional memory in the host computer in lieu of page swapping in response to the low free space condition, and satisfying the memory access directive. Additionally, the method can include determining an excess free space condition in the memory allocation and removing from the memory allocation a selection of allocated memory in the host computer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventor: Aravinda Prasad
  • Patent number: 8745307
    Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Cathy May, Naresh Nayar, Randal Craig Swanberg
  • Patent number: 8732431
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • Publication number: 20140136814
    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple threshold values (TVs) from memory. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The multiple TVs define multiple lookup key ranges. The TM determines which lookup key range includes the LKV. A RV is selected based upon the lookup key range determined to include the LKV. The lookup key range is determined by a lookup key range identifier circuit. The selected RV is selected by a result value selection circuit.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Publication number: 20140129757
    Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Haw-Jing Lo, Ali Taha, Dexter T. Chun
  • Patent number: 8719543
    Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 6, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patryk Kaminski, Thomas Woller, Keith Lowery, Erich Boleyn
  • Publication number: 20140122828
    Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: MELLANOX TECHNOLOGIES LTD.
    Inventors: Michael Kagan, Noam Bloch, Liran Liss, Shachar Raindel
  • Patent number: 8706985
    Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Robert M. Fallone
  • Patent number: 8700839
    Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 15, 2014
    Assignee: Genesys Logic, Inc.
    Inventors: Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, Cheng-Chih Yang
  • Patent number: 8683168
    Abstract: A memory system including a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively, a plurality of second blocks provided for individually storing therein the first physical addresses of initial defective blocks out of the plurality of first blocks, and a plurality of third blocks provided for individually storing therein the first physical addresses of late defective blocks out of the plurality of first blocks. The memory system further includes a computing device for obtaining the first physical address corresponding to a logical address on the basis of the logical address, information stored in the second blocks, and information stored in the third blocks.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 25, 2014
    Assignee: MegaChips Corporation
    Inventor: Shinji Tanaka
  • Publication number: 20140075148
    Abstract: A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ADEKUNLE BELLO, DOUGLAS GRIFFITH, ANGELA ASTRID JAEHDE, SRINIVASA MUPPALA RAO
  • Patent number: 8656084
    Abstract: A user device includes a flash memory configured to store an index including a plurality of index nodes and a controller configured to control the flash memory. The controller is configured to detect a pointer ID corresponding to a selected key of a first index node, translate the detected pointer ID to an index address by using a pointer table, and access a second index node corresponding to the selected key by using the index address.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Eun Kim, Namyoon Woo
  • Publication number: 20140040577
    Abstract: A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ahmed Gheith, Eric Van Hensbergen, James Xenidis
  • Publication number: 20140040593
    Abstract: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Colin Christopher Sharp, Thomas Andrew Sartorius
  • Publication number: 20140040589
    Abstract: One or more embodiments are directed to allocating a page to put non-shared data to the page, setting a transactional property for the page, the transactional property indicating that data in the page does not need tracking by hardware transactional memory (HTM), in response to detecting an access to the page during a transaction, determining whether the transactional property for the page is set, and in response to determining that the transactional property for the page is set, handling data loaded from the page in a cache as non-transactional data.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Takeshi Ogasawara
  • Publication number: 20140006711
    Abstract: A system and method for adapting a secure application execution environment to support multiple configurations includes determining a maximum configuration for the secure application execution environment, determining an optimal configuration for the secure application environment, and, at load time, configuring the secure application execution environment for the optimal configuration.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Inventor: Bin Xing
  • Patent number: 8621141
    Abstract: A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporations
    Inventors: Eric D. Mudama, David M. Jones, Andrew W. Vogan
  • Publication number: 20130339567
    Abstract: Digital objects are stored and accessed within a fixed content storage cluster by using a page mapping table and a pages index. A stream is read from the cluster by using a portion of its unique identifier as a key into the page mapping table. The page mapping table indicates a node holding a pages index indicating where the stream is stored. A stream is written to the cluster by storing the stream on any suitable node and then updating a pages index stored within the cluster. The cluster recovers from a node failure by first replicating streams from the failed node and reallocating a page mapping table to create a new pages index. The remaining nodes send records of the unique identifiers corresponding to objects they hold to the new pages index. A node is added to the cluster by reallocating a page mapping table.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: CARINGO, INC.
    Inventors: Paul R. M. CARPENTIER, Russell TURPIN
  • Publication number: 20130332684
    Abstract: Embodiments are directed to maintaining versions of data within a solid state memory. One or more embodiments create at least one data structure associated with at least one logical page of a solid state memory. The logical page is associated with at least one physical page in a data block of the solid state memory. A first set of information associated with the logical page is stored in the data structure. A second set of information associated with the physical page is stored in the data structure. The second set of information includes at least versioning information identifying which version of the logical page is represented by a dataset is stored within the physical page.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gokul B. KANDIRAJU, Hubertus FRANKE, David CRAFT
  • Publication number: 20130326158
    Abstract: In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request to write data to a logical memory address of a memory system may be received. The logical memory address may include a logical page number and a page offset, where the logical page number maps to a physical page number and the logical memory address maps to a physical memory address. A memory unit out of a plurality of memory units in the memory system may be determined by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number. The data may be written to a physical memory address in the determined memory unit in the memory system.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Lin Chen, Long Chen
  • Publication number: 20130326109
    Abstract: A method and system for dynamically managing memory in a computing environment using a control monitor. The control monitor (e.g., a virtual machine monitor or operating system kernel) includes a nomination module configured to collect memory statistics associated with at least one memory node. Based on the memory statistics, the control monitor detects one or more first pages accessed from a remote memory node at or above an access threshold. The nomination module nominates, via a communication to at least one of a scheduler module and a memory manager of the control monitor, the one or more first pages for migration to the remote memory node.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Inventor: Avi Kivity
  • Patent number: 8578088
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Publication number: 20130290669
    Abstract: In general, in one aspect, the invention relates to a system that includes memory and a prediction subsystem. The memory includes a first memgroup and a second memgroup, wherein the first memgroup comprises a first physical page and a second physical page, wherein the first physical page is a first subtype, and wherein the second physical page is a second subtype. The prediction subsystem is configured to obtain a status value indicating an amount of freed physical pages on the memory, store the status value in a sample buffer comprising a plurality of previous status values, determine, using the status value and the plurality of previous status values, a deficiency subtype state for the first subtype based on an anticipated need for the first subtype on the memory, and instruct, based on the determination, an allocation subsystem to coalesce the second physical page to the first subtype.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Eric E. Lowe, Blake A. Jones, Jonathan William Adams
  • Publication number: 20130290752
    Abstract: A system including memory and a resource controller. The memory includes a first memgroup and a second memgroup, wherein the first memgroup comprises a first physical page mapped to a virtual page, and wherein the second memgroup comprises a second physical page. The resource controller is configured to receive a request to stop the first memgroup, instruct a memory power management subsystem to mark the first memgroup as stopped in response to receiving the request to stop the first memgroup, wherein no free pages are allocated from the first memgroup after the first memgroup is marked as stopped, remap the virtual page to the second physical page in response to the marking the first memgroup as stopped, and reduce power to the first memgroup in response to a determination that the first physical page is not mapped to the virtual page.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Blake A. Jones, Julia D. Harper, Jonathan William Adams
  • Patent number: 8566511
    Abstract: A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 22, 2013
    Assignee: STEC, Inc.
    Inventors: Mohammadali Tootoonchian, Mark Moshayedi
  • Patent number: 8560806
    Abstract: Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 15, 2013
    Assignee: Intel Corporation
    Inventors: David M. Durham, Uday R. Savagaonkar, Ravi Sahita
  • Publication number: 20130262814
    Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.
    Type: Application
    Filed: August 17, 2012
    Publication date: October 3, 2013
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 8549254
    Abstract: Embodiments of an invention for using a translation lookaside buffer to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Uday R. Savagaonkar