Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry.

Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address.

Abstract: A memory system includes a memory including a page table, and an input/output memory management unit (I/O MMU) connected to the memory, and configured to receive a virtual address from an I/O Device and to search within the I/O MMU for a plurality of entries matching the virtual address. If no entries matching the virtual address are found within the I/O MMU as a result of searching for the entries, the I/O MMU accesses the memory, searches the page table for the entries matching the virtual address, and stores the entries within the I/O MMU.

Abstract: A storage control system comprises a storage resource and a controller. If the controller receives a write command which specifies an address belonging to a virtual volume, to the area belonging to the address, unassigned pages in a pool which is a storage area based on a plurality of media types of physical storage media and which is divided into a plurality of pages are supposed to be assigned. The storage control system comprises a plurality of management entries which are a plurality of entries for page management information which is the information related to the pages. The plurality of management entries include two or more page entries and two or more statistical entries. A statistical entry about a certain media type corresponds to M pages based on the storage media of the certain media type (M is an integral number which is 2 or larger). The statistical entry corresponding to the M pages comprises the information related to the I/O performance value for those M pages.

Abstract: A logical page identity for a logical page containing data storage application data can be mapped to a physical storage page location in a storage where the data of the logical page are stored. The mapping as well as additional page data can be retained within a persistence layer accessible to the data storage application. The additional page data can include at least one of a size of the page and a next page linkage indicating a second page that follows the page in a page sequence of related pages. The retained mapping and additional page data can be retrieved from the persistence layer to initiate a page operation on the related pages, and the page operation can be executed on the related pages based on the retrieved mapping and additional page data. Related methods, systems, and articles of manufacture are also disclosed.

Abstract: A memory block that includes a physical storage page holding data of a data storage application in a page buffer can be cached in a page buffer upon the memory block being designated for a change in status from a used status to a shadow status. Upon occurrence of a trigger event, all pages stored in the page buffer can be processed in a first batch process that can include converting each of the pages in the page buffer from the used status to the shadow status and emptying the page buffer. Upon receiving a call to free the pages in the page buffer from the shadow status to a free status without the trigger event occurring, the pages in the page buffer can be converted from the used status directly to the free status in a second batch process. Related methods, systems, and articles of manufacture are also disclosed.

Abstract: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine.

Abstract: A method for creating virtual machine, a virtual machine monitor and a virtual machine system are provided in the embodiments of this application. The method comprises: mapping guest frame number (GFN) corresponding to a pseudo-physical memory of a virtual machine to a shared zero page, the shared zero page being a page having content of all zeros in physical memory; when the GFN is written by the virtual machine and if a page exception occurs, allocating a physical memory page to relieve the mapping relation between the guest frame number (GFN) and the shared zero page, and establishing a mapping relation between the guest frame number (GFN) and a machine frame number (MFN) of the physical memory page. The method can reduce the amount of memory used in virtual machine startup, improve virtual machine density, and support the concurrent startup of a memory overcommitted number of virtual machine.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

Abstract: A virtual computer system having a plurality of virtual computers, the virtual computer system including: an area assignment unit operable to, when a virtual computer attempts to perform writing to a basic area which is assigned to and shared by the plurality of virtual computers, change an assignment to the virtual computer from the basic area to a copy area to which the basic area is copied and the writing is performed; and an area freeing unit operable to, when a content of the basic area matches a content of at least one copy area, change area assignment to one or more virtual computers, to which have been assigned one or more other areas than one area among the areas whose contents match each other, to the one area, and free the one or more other areas.

Abstract: Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and including a physical address space accessed via a virtual address; and a virtual memory control section configured to manage the physical address space of the nonvolatile memory in page units, map the physical address space and a virtual address space, and convert an accessed virtual address into a physical address; wherein the virtual memory control section is configured to expand a physical memory capacity allocated to a virtual page in which rewriting occurs.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid.

Abstract: A method for modeling memory compression is provided in the illustrative embodiments. A subset of candidate pages is received. The subset of candidate pages is a subset of a set of candidate pages used in executing a workload in a data processing system. A candidate page is compressible uncompressed data in a memory associated with the data processing system. The subset of candidate pages is compressed in a scratch space. A compressibility of the workload is computed based on the compression of the subset of candidate pages. Page reference information of the subset of candidate pages is received. A memory reference rate of the workload is determined. A recommendation is presented about a memory compression model for the workload in the data processing system.

Abstract: An apparatus, system, and method for application direct virtual memory management. The method includes detecting a system memory access to a virtual memory address within a monitored page of data not loaded in main memory of a computing system. The method includes determining a first swap address for a loaded page of data in the main memory. The first swap address is defined in a sparse virtual address space exposed by a persistent storage device. The first swap address is associated in an index with a first deterministic storage location. The index is managed by the persistent storage device. The method includes storing the loaded page on a persistent storage device at the first deterministic storage location. The method includes moving the monitored page from a second deterministic storage location to the main memory. The second deterministic storage location is associated with a second swap address in the index.

Abstract: A partition adjunct is provided for a logical partition running above a hypervisor of a data processing system. The partition adjunct, which is a separate dispatchable partition from an instantiating logical partition, provides one or more services to the logical partition. A service request received from the logical partition is processed by the partition adjunct utilizing virtual address space donated to the partition adjunct from the logical partition. The partition adjunct and the logical partition share a common virtual address to real address page table, and context switching the current state machine from the logical partition to the partition adjunct occurs without invalidating or modifying state data of selected memory management and address translation hardware of the data processing system. In a hardware multithreaded system, the partition adjunct is dispatched on a single thread, while another thread continues to run in the logical partition initiating the service request.

Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.

Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.

Abstract: Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.

Abstract: The memory management unit includes a page table correlating respective virtual addresses with corresponding physical addresses, first translation lookaside buffer (TLB) lookup logic that provides one of a first virtual address and a first physical address according to whether a page number of the first virtual address matches a frame number of the first physical address, a first queue buffer that stores and provides the first virtual address, and second TLB lookup logic that determines and provides a first page physical address using the first virtual address to access the page table when the page number of the first virtual address does not match the frame number of the first physical address.

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.

Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.

Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.

Abstract: A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.

Abstract: A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: Methods for providing shadow page tables that virtualize processor memory protection. In one embodiment, virtualization software maintains the following: (a) a mapping ? from guest domain identifier to a set of shadow L2 page tables that back guest L1 sections marked with a domain identifier; and (b) with each such shadow L2 page table, a set ? of back-pointers to “potentially referencing” shadow L1 descriptors.

Abstract: In response to detecting a PCI host bridge (PHB), a first address translation table may be allocated in a first portion of a memory. The first address translation table may be associated with the PHB. If an input/output adapter accessible to the PHB is configured as a virtualized adapter, a first table manager may be assigned to manage the first address translation table. The first address translation table may be configured for an initial number of virtual functions. If a requested number of virtual functions is greater than the initial number of virtual functions, additional virtual functions may be configured. A second address translation table may be allocated in a second portion of the memory. The second portion of the memory may be non-contiguous with reference to the first portion of the memory. Entries may be created in the second address translation table for the additional virtual functions.

Abstract: In a computing system including a processor and virtualization software including a guest operating system (OS) that utilizes a guest domain access control register (DACR) containing domain access information and guest page tables including first level page tables (L1 page tables) and second level page tables (L2 page tables), which guest page tables contain: (a) domain identifiers used to obtain domain access information from the guest DACR and (b) access permission information, wherein the domain access information and the access permission information are combined to provide an effective guest access permission, in accordance with one embodiment, a method for providing shadow page tables and processor DACR settings that virtualize processor memory protection includes: the virtualization software providing a shadow page table wherein: (a) domain identifiers in the shadow page table are used to identify domain access information in the processor DACR that are mapped from the domain access information in the

Abstract: Methods of memory management are described which can accommodate non- maskable failures in pages of physical memory. In an embodiment, when an impending non-maskable failure in a page of memory is identified, a pristine page of physical memory is used to replace the page containing the impending failure and memory mappings are updated to remap virtual pages from the failed page to the pristine page. When a new page of virtual memory is then allocated by a process, the failed page may be reused if the process identifies that it can accommodate failures and the process is provided with location information for impending failures. In another embodiment, a process may expose information on failure-tolerant regions of virtual address space such that a physical page of memory containing failures only in failure-tolerant regions may be used to store the data instead of using a pristine page.

Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.

Abstract: The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log.

Abstract: In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: A lightweight technique for sharing memory pages within a virtual machine (VM) is provided. This technique can be used on its own to implement intra-VM page sharing or it can be augmented with sharing across VMs. Memory pages whose content can be described by some succinct grammar, such as a regular expression or simple pattern, are identified for sharing within a VM. If the content of a page matches some simple pattern, it is proposed to share such a page, but only in the scope of the VM to which it belongs, i.e., intra-VM sharing. All other pages, i.e., those that are not simple patterns, can be candidates for sharing in the scope of all currently active VMs, i.e., inter-VM sharing. Either fully functional page sharing across VMs and/or page sharing in the context of each VM can be implemented.

Abstract: Multiple types of storage devices which have different performance are appropriately allocated to multiple virtual volumes in accordance with the performance requirements of the respective virtual volumes. In cases where, among virtual volumes 82 for which response times have been specified, there is a [virtual volume] that has a shortage of pages to which SSDs 70 should be allocated and that does not satisfy the performance requirement when its Tier boundary value ? is adjusted to Tier boundary value ?? and, if unallocated pages as the pages to which SSDs 70 should be allocated do not exist, Tier boundary value ? or Tier boundary value ? of another virtual volume is adjusted to Tier boundary value ?? or the Tier boundary value ??, and pages to which SSDs 70 are allocated are secured in the virtual volume 82 for which the Tier boundary value has been adjusted.

Abstract: A processor includes a prefetch aware prefetch unit having a storage with a number of entries, and each entry corresponds to a different prefetch data stream. Each entry may be configured to store information corresponding to a page size of the prefetch data stream, along with, for example, an address corresponding to the prefetch data stream. For each entry, the prefetch unit may be configured to determine whether a prefetch of data in the data stream will cross a page boundary associated with the data stream based upon the page size information.

Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.

Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

Abstract: Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.

Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Abstract: A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module.

Abstract: A method to perform a least recently used (LRU) algorithm for a co-processor is described, which co-processor in order to directly use instructions of a core processor and to directly access a main storage by virtual addresses of said core processor comprises a TLB for virtual to absolute address translations plus a dedicated memory storage also including said TLB, wherein said TLB consists of at least two zones which can be assigned in a flexible manner more than one at a time. Said method to perform a LRU algorithm is characterized in that one or more zones are replaced dependent on an actual compression service call (CMPSC) instruction.

Abstract: In an embodiment, a first plurality of rows of a first table are read from memory in an order of page addresses of pages in the memory that comprise the first plurality of rows. First selected rows from the first plurality of rows that meet a query predicate are stored into a result set. After the reading the first plurality of rows in the order of the page addresses, a second plurality of rows of the first table are read from secondary storage, in an order of row identifiers of the second plurality of the rows in the first table. Second selected rows from the second plurality of rows that meet the query predicate are stored into the result set.

Abstract: A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configured to receive from the load unit a physical address of a first cache line that includes the page table entry specified by the load request. The prefetch unit is further configured to responsively generate a request to prefetch into the cache memory a second cache line. The second cache line is the next physically sequential cache line to the first cache line. In an alternate embodiment, the second cache line is the previous physically sequential cache line to the first cache line rather than the next physically sequential cache line to the first cache line.

Abstract: Updating contents of certain memory pages in a virtual machine system is deferred until they are needed. Specifically, certain page update operations are deferred until the page is accessed for a load or store operation. Each page within the virtual machine system includes associated metadata, which includes a page signature characterizing the contents of a corresponding page or a reference to a page with canonical contents, and a flag that indicates the page needs to be updated before being accessed. The metadata may also include a flag to indicate that a backing store of the memory page has contents of a known content class. When such a memory page is mapped to a shared page with contents of that known content class, a flag in the metadata to indicate that contents of the memory page needs to be updated is not set.