Abstract: Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.

Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.

Abstract: Embodiments of an invention for using a translation lookaside buffer to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.

Abstract: A method in one example implementation includes synchronizing a first memory page set with a second memory page set of a virtual guest machine, inspecting the first memory page set off-line, and detecting a threat in the first memory page set. The method further includes taking an action based on the threat. In more specific embodiments, the method includes updating the first memory page set with a subset of the second memory page set at an expiration of a synchronization interval, where the subset of the second memory page set was modified during the synchronization interval. In other more specific embodiments, the second memory page set of the virtual guest machine represents non-persistent memory of the virtual guest machine. In yet other specific embodiments, the action includes at least one of shutting down the virtual guest machine and alerting an administrator.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes a first virtual layer interfacing with the hosts, operable to represent a logical address space available to said hosts and characterized by an Internal Virtual Address Space (IVAS); a second virtual layer characterized by a Physical Virtual Address Space (PVAS), interfacing with the physical storage devices, and operable to represent an available storage space; and an allocation module operatively coupled to the first and second virtual layers and providing mapping between IVAP and PVAS. Each address in PVAS is configured to have a corresponding address in IVAS. The allocation module facilitates management of IVAS and PVAS, enabling separation of a process of deleting certain logical object into processes performing changes in IVAS and PVAS, respectively.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: A physical memory management scheme for handling page faults in a multi-core or many-core processor environment is disclosed. A plurality of memory allocators is provided. Each memory allocator may have a customizable allocation policy. A plurality of pagers is provided. Individual threads of execution are assigned a pager to handle page faults. A pager, in turn, is bound to a physical memory allocator. Load balancing may also be provided to distribute physical memory resources across allocators. Allocations may also be NUMA-aware.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, sub-pages can be virtually addressed at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, sub-pages can be virtually addressed at a granularity that is 1/(2M)-th of a memory page. The granularity of page sizes can be selected according to particular use cases. In the case of COW optimization, page sizes can be set statically between 4 KB and 2 MB or configured dynamically among multiple page sizes.

Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.

Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.

Abstract: A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.

Abstract: Provided are techniques for managing an amount of real storage used by a database management system. A value of a real storage management parameter is received, wherein the real storage management parameter indicates conditions under which one or more virtual storage pages are analyzed to identify one or more unused, virtual storage pages that are to be discarded. The database management system and consumption of real storage and auxiliary storage is monitored. In response to determining that the value of the real storage management parameter is set to on, the one or more unused virtual storage pages are discarded. In response to determining that the value of the real storage management parameter is set to auto and that paging has occurred, the one or more unused, virtual storage pages are discarded. Health values are recorded.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.

Abstract: A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.

Abstract: Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor circuit. A memory unit may be coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines. A memory management application may be operative on the first processor circuit and the second processor circuit in a shared manner to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages. The memory management application may perform sequential memory de-duplication operations on the first processor circuit, and parallel memory de-duplication operations on the second processor circuit. Other embodiments are described and claimed.

Abstract: In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address con

Abstract: Machine memory fragmentation in a computer system having a host operating system and virtual machine running on a hypervisor hosted by the host operating system is reduced by having the hypervisor identify and release those machine memory pages that are more likely than others to reduce the fragmented state of the host machine memory.

Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.

Abstract: A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.

Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.

Abstract: In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level 210. The memory management system may assign an initial priority level 212 to a memory page in a page priority list 202. The memory management system may change the memory page to a target priority level 214 in the page priority list 202 after a protection period 238 has expired.

Abstract: A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage.

Abstract: A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.

Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.

Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Abstract: A system and method for rootkit protection in a hypervisor environment includes modules for creating a soft whitelist having entries corresponding to each guest kernel page of a guest operating system in a hypervisor environment, wherein each entry is a duplicate page of the corresponding guest kernel page, generating a page fault when a process attempts to access a guest kernel page, and redirecting the process to the corresponding duplicate page. If the page fault is a data page fault, the method includes fixing the page fault, and marking a page table entry corresponding to the guest kernel page as non-executable and writeable. If the page fault is an instruction page fault, the method includes marking a page table entry corresponding to the guest kernel page as read-only. Redirecting changing a machine page frame number in a shadow page table of the hypervisor to point to the corresponding duplicate page.

Abstract: A system and method in one embodiment includes modules for creating a soft whitelist having entries corresponding to each guest kernel page in a guest operating system in a hypervisor environment, generating a page fault when an access attempt is made to a guest kernel page, fixing the page fault to allow access and execution if the guest kernel page corresponds to one of the entries in the soft whitelist, and denying execution if the guest kernel page does not correspond to any of the entries in the soft whitelist. If the page fault is an instruction page fault, and the guest kernel page corresponds to one of the entries in the soft whitelist, the method includes marking the guest kernel page as read-only and executable. The soft whitelist includes a hash of machine page frame numbers corresponding to virtual addresses of each guest kernel page.

Abstract: An aspect of the invention relates to a method of managing data location of plural files in a storage system having a mixed volume which includes plural pages having a fixed page size, the pages belonging to different tiers. The method comprises mapping pages of different tiers to storage devices of different speeds in the storage system, the storage devices including at least a high speed storage device corresponding to a high tier page and a low speed storage device corresponding to a low tier page; and for each file that is a large file which is larger in size than the page size, performing sub-file tiered management on the large file to assign the large file among pages of different tiers according to access characteristics of different portions of the large file by matching the access characteristics of each portion of the large file with a corresponding tier of the assigned page of the mixed volume.

Abstract: A system and method in one embodiment includes modules for detecting an access attempt to a critical address space (CAS) of a guest operating system (OS) that has implemented address space layout randomization in a hypervisor environment, identifying a process attempting the access, and taking an action if the process is not permitted to access the CAS. The action can be selected from: reporting the access to a management console of the hypervisor, providing a recommendation to the guest OS, and automatically taking an action within the guest OS. Other embodiments include identifying a machine address corresponding to the CAS by forcing a page fault in the guest OS, resolving a guest physical address from a guest virtual address corresponding to the CAS, and mapping the machine address to the guest physical address.

Abstract: A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that corresponds to a first data block including the page; receiving an update request for the page; and performing a write operation on a second log block that corresponds to the first data block. The memory card system includes: at least one non-volatile memory including a data block and a log block for updating the data block; and a memory controller controlling an operation of the non-volatile memory. During a write operation for a predetermined page, the controller controls writing of a first log block corresponding to a first data block including the predetermined page, and controls writing of a second log block during an update operation of the predetermined page.

Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.

Abstract: For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added.

Abstract: Systems and methods disclosed herein uniquely define each type of Fortran type descriptor within an executable file or shared library to allow for a rapid determination of how the dynamic type of one object (e.g., a first polymorphic entity) relates to that of another object (e.g., a second polymorphic entity) while allowing for the lazy loading of shared libraries. In one aspect, type descriptor definitions are instantiated (e.g., during compile-time) in each object file in which polymorphic entities are defined, each type descriptor definition is marked with a singleton attribute, and each group of common type descriptor definitions is associated with a COMDAT group to ensure that only a single copy of each type descriptor is defined in a corresponding executable file at a particular address in memory to which polymorphic entities can reference. Type descriptor addresses can be compared to determine dynamic type relations between polymorphic entities.

Abstract: Embodiments of the present invention provide a method, system and computer program product for dynamic main memory reconfiguration in virtual memory management. In an embodiment of the invention, a method for dynamic main memory reconfiguration in virtual memory management can include receiving a memory access directive in a host computer, determining a low free space condition in a memory allocation to satisfy the memory access directive, augmenting the memory allocation with a mapping to additional memory in the host computer in lieu of page swapping in response to the low free space condition, and satisfying the memory access directive. Additionally, the method can include determining an excess free space condition in the memory allocation and removing from the memory allocation a selection of allocated memory in the host computer.

Abstract: A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios.

Abstract: A method is provided for symmetric live migration of virtual machines. According to the method, a first least recently used map is generated for a set of memory pages of a first virtual machine. The first least recently used map includes metadata including memory page physical address location information. A first memory page of the first virtual machine and the metadata for the first memory page is sent from the first virtual machine to a second virtual machine while the first virtual machine is executing. A first memory page and meta data associated therewith of the second virtual machine is received from the second virtual machine. The memory pages of the first virtual machine are ordered from a first location of the first least recently used map to a last location of the first least recently used map based on how recently each of the memory pages of the first virtual machine has been used.

Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded.

Abstract: The present invention discloses a method and a device for storing a routing table entry. The method includes: splitting a routing table entry into two points according to a range matching policy; obtaining a storage location of the routing table entry in a hierarchical binary tree; and adding each segment related to the routing table entry to the binary tree of each segment according to the storage location. According to the present invention, the routing table entry is stored in the hierarchical binary tree in segments, which significantly reduces the total amount of memory required to be occupied by storage of the routing table entry.

Abstract: A method for simulating remote memory access in a target machine on a host machine is disclosed. Multiple virtual memory spaces in the host machine are divided and a virtual address space of each target application process is set to one virtual memory space that corresponds to a target application process and is in the multiple virtual memory spaces. Access of the target application process is captured to a virtual memory space other than the virtual memory space corresponding to the target application process in the multiple virtual memory spaces.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: building at least one local page address linking table containing a page address linking relationship between a plurality of physical page addresses and at least a logical page address, wherein the local page address linking table includes a first local page address linking table containing a first page address linking relationship of a plurality of first physical pages, and a second local page address linking table containing a second page address linking relationship of a plurality of second physical pages that are different from the first physical pages; building a global page address linking table according to the local page address linking table; and accessing the memory apparatus according to the global page address linking table.

Abstract: A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree.

Abstract: A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page table level that has a page table base address. A designated page table base address is received in response to the match. The page table walk starts at the designated page table, thereby skipping over earlier page tables.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a physical block; receiving a second access command from the host; and analyzing the second access command to obtain a second host address. For example, the method may further include: linking the second host address to the physical block, wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block. In another example, the method may further include: linking the first host address to at least a page of the physical block; and linking the second host address to at least a page of another physical block.

Abstract: In one embodiment, a virtual machine manager may use dynamic memory balancing and greedy ballooning to improve guest memory performance. A memory 130 may have a system memory page set with a system memory page set size associated with the virtual machine to support a guest memory page set of the virtual machine with a guest memory page set size. A processor 120 may instruct the virtual machine to execute a reduction of the guest memory page set size. The processor 120 may maintain the system memory page set size during the reduction.