Abstract: For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: Provided is a method, which may be performed on a computer, for prefetching data over an interface. The method may include receiving a first data prefetch request for first data of a first data size stored at a first physical address corresponding to a first virtual address. The first data prefetch request may include second data specifying the first virtual address and third data specifying the first data size. The first virtual address and the first data size may define a first virtual address range. The method may also include converting the first data prefetch request into a first data retrieval request. To convert the first data prefetch request into a first data retrieval request the first virtual address specified by the second data may be translated into the first physical address. The method may further include issuing the first data retrieval request at the interface, receiving the first data at the interface and storing at least a portion of the received first data in a cache.

Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

Abstract: Relocating data in a virtualized environment maintained by a hypervisor administering access to memory with a Cache Page Table (‘CPT’) and a Physical Page Table (‘PPT’), the CPT and PPT including virtual to physical mappings. Relocating data includes converting the virtual to physical mappings of the CPT to virtual to logical mappings; establishing a Logical Memory Block (‘LMB’) relocation tracker that includes logical addresses of an LMB, source physical addresses of the LMB, target physical addresses of the LMB, a translation block indicator for each relocation granule, and a pin count associated with each relocation granule; establishing a PPT entry tracker including PPT entries corresponding to the LMB to be relocated; relocating the LMB in a number of relocation granules including blocking translations to the relocation granules during relocation; and removing the logical addresses from the LMB relocation tracker.

Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Abstract: Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.

Abstract: A pool that is a storage area group composed of a plurality of real pages based on a plurality of RAID groups is managed. The storage system carries out the rebuild processing that includes the steps of copying each of data that has been stored into all allocated real pages among all real pages based on a specific RAID group to an unallocated real page based on at least one RAID group separate from the specific RAID group, allocating a real page of each copy destination to each virtual page of an allocated destination of an allocated real page of each copy source, and canceling an allocation of an allocated real page of each copy source to a virtual page.

Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.

Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: Methods of maintaining an address table for mapping logical addresses to physical addresses include continuously consolidating main address maps and an update address map, and periodically compacting the update address map. Consolidating includes selecting a main address map, reading valid mapping entries from the main and update address maps, constructing a mapping set including the valid mapping entries, and writing the mapping set to a second main address map. The update address map is compacted if a criterion is met, and includes copying the valid mapping entries to an unwritten block or metablock and assigning the unwritten block or metablock as a new update address map. The length of consolidation may depend on the average length of compacted mapping entries following a compaction operation. Increased performance due to lower maintenance overhead may result by using these methods.

Abstract: A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information.

Abstract: Methods, systems, and computer-readable media of data storage that include storing page identities of individual pages and logical relationships between pages are disclosed. A particular system includes a plurality of data storage devices. A storage manager is configured to store data as pages at the data storage devices. Each page includes a page payload and a page identity. The storage manager is also configured to store one or more relationships indicating logical order between pages.

Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract: A virtual memory method for allocating physical memory space required by an application by tracking the page space used in each of a sequence of invocations by an application requesting memory space; keeping count of the number of said invocations; and determining the average page space used for each of said invocations from the count and previous average. Then, this average page space is recorded as a predicted allocation for the next invocation. This recorded average space is used for the next invocation. If there is any additional page space required by said next invocation, this additional page space may be accessed through any conventional default page space allocation.

Abstract: One embodiment includes a personal computer device comprising at least one machine to execute a primary user operating system, a first physical memory to be used by the primary user operating system, at least one appliance operating system that is independent from the primary user operating system, a second physical memory to be sequestered from the primary user operating system and an access violation monitor to restrict access from the at least one appliance operating system to the second physical memory, wherein the access violation monitor is to run only when the at least one appliance operating system is invoked and at least one appliance operating system is to be invoked only after the primary user operating system has been suspended to a standby state.

Abstract: An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored.

Abstract: In a method to accelerate address translation into a physical address, a computer maps a virtual memory area with a large page, the virtual memory area including multiple virtual pages satisfying a predetermined condition and being handled in units of pages, the large page having a larger area than each of the virtual pages, and under a condition in which one of the virtual pages mapped with and included in the large page has a memory protection attribute different from a memory protection attribute of the other virtual page, sets physical memory protection information for protecting a physical page corresponding to the one virtual page having the different memory protection attribute.

Abstract: A method, data processing system and computer program product enables efficient transfer of a virtual machine from a first data processing system (DPS) to a second DPS using a combination of Transmission Control Protocol (TCP) and Uniform Data Protocol (UDP). A virtual machine migration (VMM) utility identifies all memory pages of the first virtual machine. The VMM utility notifies the second DPS via TCP of the scheduled transfer of the virtual machine. The VMM utility copies and transfers the memory pages of the virtual machine to the second DPS via UDP. When all expected components of the virtual machine are not received by the second DPS and/or memory data is modified within the memory pages during the migration, the VMM utility combines the missing data and the modified data and transfers the final components of the virtual machine using TCP. Execution of the virtual machine resumes on the second DPS.

Abstract: A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a corresponding physical address page. The processing system also includes a translation lookaside buffer adapted to cache page table information. The processing system also includes memory management software responsive to changes in the page table to consolidate a run of contiguous page table entries into one or more page table entries having a larger memory page size, Y. The memory management software further determines whether the run of contiguous page table entries may be cached in an entry of the translation lookaside buffer that caches multiple page table entries, X, in a single translation lookaside buffer entry.

Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.

Abstract: An information processing apparatus includes: a ROM for storing a program therein; a RAM for temporarily storing therein the program read from the ROM; a program execution unit that is adapted to read and execute the program from the ROM or the RAM; a memory management unit that translates a virtual address output by the program execution unit to a physical address of the ROM or the RAM; a page table storage unit for storing therein a page table which is referred to by the memory management unit, and in which mapping data of a virtual address with a physical address of the ROM or the RAM corresponding to the virtual address is stored; a detection unit that detects change of an event in the information processing apparatus; an operation switching unit that is adapted to instruct, when the detection unit detects the change of the event during a ROM-operation in which the program execution unit reads the program from the ROM, switching from the ROM-operation to a RAM-operation in which the program execution unit

Abstract: A method and system to handle an asynchronous page fault in a virtual machine system. A computer hosts a virtual machine that includes a virtual central processing unit (CPU). The virtual CPU requests access to a page that is not resident in memory. The host operating system of the computer receives an indication of a page fault, and informs the virtual CPU of the page fault. The host operating system provides an identifier associated with the page fault. The host operating system performs page swapping operating in parallel with a new task rescheduled by the virtual CPU, and sends a wake-up signal to the virtual CPU when the page has been brought back into the memory.

Abstract: A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones.

Abstract: A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, can perform data caching. In some implementations, a method and system include receiving information that includes a logical address, allocating a physical page in a non-volatile memory structure, mapping the logical address to a physical address of the physical page, and writing, based on the physical address, data to the non-volatile memory structure to cache information associated with the logical address. The logical address can include an identifier of a data storage device and a logical page number.

Abstract: A method for monitoring a data structure maintained by guest software within a virtual machine is disclosed. Changes to the contents of the data structure are determined, such as by placing write traces on the memory pages containing the data structure. Also, the method involves determining when memory pages containing the data structure are swapped into and/or out of guest physical memory by the guest software, such as by placing write traces on the memory pages containing the guest page table and detecting changes to the present bit of page table entries involved in mapping virtual addresses for the data structure. Information about the contents of the data structure is retained while memory pages containing the data structure are swapped out of guest physical memory.

Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.

Abstract: A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry.

Abstract: A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.

Abstract: Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

Abstract: A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.

Abstract: Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache.

Abstract: This disclosure provides a method for assigning data in a plurality of physical storage resources for an information handling system. The plurality of physical storage resources includes a first tier of physical storage resources and a second tier which has a lower performance and cost relative to capacity than each of the first tier. A tier manager may be hosted on the information handling system and in electronic communication with the plurality physical storage resources. The tier manager may: determine a seek distance value for each page, determine an operation rate for each page, determine an operation size value for each page, determine an elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page.

Abstract: Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Abstract: The present invention is directed to a virtualization system using a solid-state drive for disaster recovery.

Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector.

Abstract: A method for managing a plurality of blocks of a Flash memory includes: dynamically determining a link type regarding a logical block address according to at least one criterion, where the link type is selected from a plurality of predetermined link types; and regarding the logical block address, recording/updating the link type and linking information corresponding to the link type. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks.

Abstract: Memory controller page management devices, systems, and methods are disclosed. In one embodiment, a memory controller is configured to access memory in response to a memory access request. The memory controller is configured to apply a page management policy to either leave open or close a memory page based on at least identification information of a requestor. In this manner, a memory page management policy can be applied by the memory controller to optimize memory access times and reduce latency based on the identification of the requestor. For example, the requestor may be associated with sequential or series of memory access requests to the same memory such that a leave open page management policy would be optimal for reduced memory access times. As another example, the requestor may be associated with memory access requests to random memory pages such that a close page management policy would be optimal for reduced memory access times.

Abstract: In one embodiment, a mechanism for out-of-synch virtual machine memory management optimization is disclosed. In one embodiment, a method for out-of-synch virtual machine memory management optimization includes receiving a memory management unit (MMU) synchronization event issued from a VM virtualized by a VM monitor (VMM) of a host server device, and synchronizing one or more unsynchronized page tables (PTs) of a shadow PT hierarchy maintained by the VMM with one or more corresponding guest PTs of a guest PT hierarchy maintained by the VM, wherein the one or more unsynchronized PTs include an unlimited number of unsynchronized PTs in a visible address space of the shadow PT hierarchy that is determined by a current CR3 register address of the shadow PT hierarchy.

Abstract: A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set is associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible.

Abstract: The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table.

Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.

Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format.

Abstract: A method and apparatus for managing memory allocation using memory pages. A first physical memory page is compared with a second physical memory page, wherein the first physical memory page is associated with a first page table and the second physical memory page is associated with a second page table. If the second physical memory page matches the first physical memory page, the second physical memory page is deallocated, and the second page table is associated with the first physical memory page.

Abstract: Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method.

Abstract: A method for performing random writing on a NV memory includes: writing page mapping information regarding a portion of a full range of addresses of the NV memory and providing at least one page mapping table corresponding to a predetermined size; and accessing the NV memory according to the page mapping information. An apparatus for performing full range random writing on an NV memory includes: a controller arranged to perform the full range random writing; and a program code, at least a portion of which is embedded within the controller or received from outside the controller. The controller executing the program code writes page mapping information regarding at least a portion of a full range of addresses of the NV memory and provides at least one page mapping table corresponding to a predetermined size. The controller executing the program code accesses the NV memory according to the page mapping information.