Abstract: In an embodiment of a method of making a conditional jump in a computer running a program, an input is provided, conditional on which a substantive conditional branch is to be made. An obfuscatory unpredictable datum is provided. Code is executed that causes an obfuscatory branch conditional on the unpredictable datum. At a point in the computer program determined by the obfuscatory conditional branch, a substantive branch is made that is conditional on the input.

Abstract: A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

Abstract: There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or each of a plural number of conditions, and for performing branching to a branch target specified, based on comparison operation between the results of the comparison operations performed and the branching condition value specified. The condition setting instruction is an instruction for setting the condition.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from.

Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Abstract: In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

Abstract: A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.

Abstract: A processor system includes a plurality of pipeline stages, a controller, and a transfer path. The plurality of pipeline stages is subjected to processing. The controller determines whether or not each of the executable instructions to be processed in the pipeline stages requires processing in a succeeding pipeline stage. The transfer path, if the controller determines the executable instruction does not require the processing in the succeeding pipeline stage, skips the pipeline stage including the unnecessary processing.

Abstract: Instruction execution is controlled by a single test that determines whether processing should continue in mainline processing or fall through to a test set. The single test compares a dynamically set variable to an instruction counter. If the test is met, mainline processing continues. Otherwise, processing falls through to a test set.

Abstract: A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

Abstract: A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes the exception condition. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the exception handler. The execution unit also saves a state in response to detecting the exception condition caused by the user program instruction. A second fetch unit fetches the exception handler instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.

Abstract: Techniques are disclosed for generating fast vector masking SIMD code corresponding to source code having a conditional statement, where the SIMD code replaces the conditional statements with vector SIMD operations. One technique includes performing conditional masking using vector operations, bit masking operations, and bitwise logical operations. The need for conditional statements in SIMD code is thereby removed, allowing SIMD hardware to avoid having to use branch prediction. This reduces the number of pipeline stalls and results in increased utilization of the SIMD computational units.

Abstract: A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state.

Abstract: A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state.

Abstract: A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data storing method applied to a processor having a pipelined processing unit is provided. The pipelined processing unit includes stages. The stages include a source operand fetch stage and a write-back stage. The method includes the following steps. Firstly, a storing instruction is fetched and decoded. Next, the storing instruction is entered to the source operand fetch stage, and whether there is a late-done instruction in the pipelined processing unit is determined. The late-done instruction not lagged behind the storing instruction generates a late-coming result before entering the write-back stage. If it is determined that there is a late-done instruction in the pipelined processing unit, then the late-coming result is fetched before the storing instruction is entered to the write-back stage. Thereafter, the storing instruction is entered to the write-back stage, and the late-coming result is stored to a target memory which the storing instruction corresponds to.

Abstract: Apparatus and methods are disclosed for a computation processor that can execute a semi-absolute branch instruction, as well as methods of operation and of generating the semi-absolute branch instruction.

Abstract: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.

Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Abstract: A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Abstract: A method for performing at least one jump in a program executed by a processor, including determining a result over several bits as an indicator that a desired condition has been complied with, the result corresponding to an operation taking into account at least one predetermined value and at least one current value; and calculating a jump address which is a function of the result.

Abstract: A method, system, and computer program product for optimizing runtime branch selection in a flow process are provided. The method includes gathering performance metrics of flow branch behavior for executed flows in a runtime system over time and using aggregated performance metrics for the behavior to determine an optimal ordering of branches for a currently running flow. The optimal ordering is determined by identifying one or more branch points in the flow, generating ordering permutations for at least a portion of the branches in the branch point for the flow to identify any permutations that have not been executed, gathering metrics for permutation(s) of the branch point in the flow, comparing the metrics to performance metrics of executed flows having substantially similar flow branch behavior, and identifying optimal branch ordering for the permutation(s) based upon the comparison. The method also includes executing the flow according to the optimal branch ordering.

Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.

Abstract: A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.

Abstract: A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted.

Abstract: A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

Abstract: Disclosed is a method for processing multimedia data at a mobile communication terminal having at least one sub processor besides a main processor, including the steps of analyzing information of multimedia data to be processed at the main processor, selecting a processor at the main processor for processing the multimedia data according to analyzed result of the information, calling codec needed for the data processing at the selected processor, and processing the multimedia data at the selected processor by using the called codec.

Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Abstract: A technique for run-time tracking changes to variables and memory locations during code execution to increase efficiency of execution of the code and to facilitate in debugging the code. In one example embodiment, this is achieved by determining whether a received instruction in a trackable instruction during code execution. The trackable instructions can include one or more trackable variables. The trackable instruction is then decoded and a track instruction cache and a track variable cache are then updated with associated decoded trackable instruction and the one or more trackable variables, respectively.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A controlling process may enable or disable the launching of a predicated process that has already been queued for launching, e.g. via a pushbuffer. The controlling process generates a report so that launching of the predicated process is enabled or disabled based on the report. The predicate may be global in application to enable or disable all subsequent launch commands. Alternatively, the predicate may be specific to one or more predicated processes. In an embodiment with a central processing unit (CPU) coupled to a graphics processing unit (GPU), the CPU may generate the controlling process that enables or disables the launch of the predicated process. Alternatively or additionally, the GPU may generate the controlling process that enables or disables the launch of the predicated process.

Abstract: The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a program memory and creating an instruction bundle consisting of a sequence of instructions to be processed in parallel. A compression buffer is interposed between the program memory and an instruction decompression unit, such that a compression code read in a previous clock cycle is ready at the beginning of a decompression cycle of the subsequent instruction bundle thereby avoiding a delay due to memory read latency.

Abstract: When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 group. The data of the strand 0 and the data of the strand 1 are allocated to the respective entries by switching a select circuit. When an entry is released from the branch reservation station, the select circuit switches the strands so that a branch instruction in one strand can be released in order, thereby releasing the entry.

Abstract: The present invention provides a data processor capable of automatically discriminating a loop program and performing a reduction in power by size-variable lock control on an instruction buffer. The instruction buffer of the data processor includes a buffer controller for controlling a memory unit that stores each fetched instruction therein. When an execution history of a fetched condition branch instruction suggests condition establishment, and in the case that the branch direction of the fetched condition branch instruction is a direction opposite to the order of an instruction execution and the difference of instruction addresses from the branch source to the branch target based on the condition branch instruction is a range held in the storage capacity of the instruction buffer, the buffer controller retains an instruction sequence from a branch source to a branch target based on the condition branch instruction in the instruction buffer.

Abstract: A processor simulation environment includes a processor execution model operative to simulate the execution of processor instructions according to the characteristics of a target processor, and branch override logic. When the processor execution model decodes a branch instruction, it requests a branch directive from the branch override logic. In response to the request, the branch override logic provides a branch directive that resolves the branch evaluation. The request may include a branch instruction address. The branch override logic may index an execution trace of instructions executed on a processor compatible with the target processor, using the branch instruction address. The branch directive may include an override branch target address, which may be obtained from the instruction trace, or otherwise calculated by the branch override logic. In this manner, accurate program execution order may be simulated in a simulation environment in which complex I/O is not modeled.

Abstract: A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by the processing unit. The method may be applied to the securization of an integrated circuit.

Abstract: A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in the instruction. Based on the outcome of test, the subsequent instruction is executed or skipped. Further, the instruction includes at least one bit that specifies how the test is to be performed. The bit may specify that the immediate value is to be compared to the register value, or that the immediate value is used to mask the register value and the masked register value has one or more of its bits tested.

Abstract: Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.

Abstract: To prevent exposure or tampering of data by an illegal access to a memory of an LSI, a ROM (13) has two separate program regions corresponding to memory access authorities. Only when detecting a branch instruction generating signal from a CPU (12), an address decoding circuit (23) decodes a branch destination address. A mode setting circuit (24) determines to which of the program regions of the ROM (13) the decoded branch destination address corresponds, and sets the mode signal to a corresponding mode. An access control circuit (26) controls accesses to the respective memories (13, 14, 15) according to the mode signal set by the mode setting circuit (24).

Abstract: A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding pipeline for enabling the code to be executed without stall so that the number of cycles required to execute the code can be reduced effectively. Moreover, the multiple pipelines can save more cycles when the number of stages in one pipeline is large.

Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.