Abstract: Actual power savings achieved by using a power savings mode in a communications device may be increased by analyzing the effects of the power savings mode on delays and using the analysis on which to base a decision as to whether or not to enter the power savings mode.

Abstract: A system and method to determine a presence of devices coupled to one a more peripheral buses in a system, and dynamically reducing power consumption of a subset of the devices that are present, based on correlating application/device association and a predetermined power source budget. In one embodiment, the reducing of the power consumption is performed dynamically by having an agent reduce the power limit in a device register(s) corresponding to the subset of devices. Furthermore, in one embodiment, the power resource budget is based at least in part on a user-selected power/performance level.

Abstract: A performance scheduler creates performance schedule of a battery based on use schedule of applications and residual charge level. A mode controller monitors and controls performance levels of a laptop personal computer according to the performance schedule. Further, when a charge counter counts a number of charge cycles of the battery and estimates residual charge level, a reduction in a charging capacity is taken into consideration based on the number of the charging times.

Abstract: A method and system for controlling power consumption within a network node is disclosed. The method and system include dynamically controlling the power consumption of network processing engines based on predetermined thresholds. By dynamically controlling the power consumption of network processing engines based on predetermined thresholds, energy consumption of the overall network processing system is minimized, thereby reducing the operational costs of the system as well as increasing the overall efficiency of network operations. The method and system comprise allowing a queue to receive a plurality of data packets and dynamically controlling the power consumption of at least one of a plurality of processing engines based on a threshold.

Abstract: An information processing apparatus includes a first function block which controls rendering and a second function block which controls operation modes of the first function block. The rendering is finally performed in a display unit. The second function block shifts the operation mode to a power-saving mode in the first function block when the first function block completes generation of a screen to be rendered before completion of a unit rendering period, namely, a frame period. In the event of start of next unit rendering period, the second function block, on the other hand, shifts the power-saving mode back to a normal mode in the first function block, based on a vertical synchronizing signal indicative of the start of next unit rendering period.

Abstract: An inquiring apparatus and method thereof is provided for assisting the CPU to inquire the state of the peripheral device. When the CPU needs to perform an inquiring process to wait for a peripheral device to come to an expected state, an inquiring apparatus is activated, instead of the CPU, to perform an inquiring process. The CPU is placed in a power-saving state which stops outputting the clock to the CPU when the inquiring apparatus performs the inquiring process. The inquiring process includes outputting a read cycle to the peripheral device receiving a current state of the peripheral device in response to the read cycle; and comparing the current state with the expected state. If the current state and the expected state are the same, the clock is outputted to the CPU again.

Abstract: A battery management system includes a flash memory chip having a smart battery management program and a microprocessor. An interface model (I/F module) is installed in the microprocessor as a bridge between the flash chip and the microprocessor. The I/F module includes a data register and an address register as a data buffer and address buffer, respectively, between the CPU and the flash chip. The I/F module also includes a logic control circuit to generate signals for the flash chip to read and program.

Abstract: An embedded system optimally operates with minimal power consumption without sacrificing performance. Power consumption can be reduced by independently and dynamically controlling multiple power partitions, wherein components within a partition can have the same power profile. States of operation can be programmably defined in a table and enforced using hardware. Voltages in the table can be dynamically updated during a runtime of the system using a timing feedback module, which is connected to a critical path in a partition. The timing feedback module can output a vector that indicates the timing margin for that critical path. Using this timing margin, software can increase or decrease the voltage to optimize power consumption of that partition.

Abstract: A method of power management for use in a local area network, in which a plurality of local area network nodes are supplied power over communication cabling, the method comprising: supplying power to the plurality of local area network nodes over communication cabling; inputting total power availability; monitoring total power consumption; establishing a first limit for the monitored total power consumption; establishing a second limit for the monitored total power consumption, the second limit being lower than the first limit; in the event the first limit is exceeded, disconnecting the supplied power to at least one of the plurality of local area network nodes; and in the event the second limit is exceeded, supplying power to an additional node only after disconnecting the supplied power to at least one of the plurality of local area network nodes.

Abstract: A method and apparatus for a user to interface with a mobile computing device is disclosed.

Abstract: According to one embodiment of the present invention, there is provided a power management system for use in a computer system having a memory system incorporating a non-volatile memory and a controller which presents the logical characteristics of a disc storage device to a host, the power management system comprising means for monitoring the operational activity levels within at least some of the components of the controller and arranged, in response to the monitored levels, to vary the power consumed by selected components of the controller.

Abstract: One embodiment of the present invention provides a system for implementing a sleep proxy. The system starts by receiving a request at the sleep proxy for information pertaining to a service provided by a device. In response to this request, the system determines if the device is a member of a list of devices for which the sleep proxy takes action. If so, the system determines if the sleep proxy can answer the request. If so, the sleep proxy sends a response to the request on behalf of the device. In a variation on this embodiment, if the system cannot answer the request on behalf of the device, the system sends a wakeup packet to the device, wherein the wakeup packet causes the device to exit a power-saving mode so that the device can respond to the request directly.

Abstract: The present invention provides both a peripheral device that regulates its own temperature by adjusting its power consumption, and a method to accomplish the same. The method generally includes monitoring the temperature of the mass storage device and reducing power consumption when the temperature exceeds a certain threshold.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: A mechanism is provided for a personal computer to preserve user and system state data in the event of an AC power failure when the computer is in a standby state. When the AC power failure occurs, a switchover circuit connects a rechargeable energy storage medium, such as a rechargeable battery, to the power supply of the computer for powering components of computer, and the computer is awaken. A critical battery alarm is then issued to trigger the operating system of the computer to perform a transition into a hibernation state, during which the state data of the computer are persistently stored. The energy storage medium is disconnected from the power supply after the computer system has entered hibernation.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: A system and method for information preservation on a portable electronic device. A signal indicating an energy capacity threshold remaining in the battery of a hand held device may be generated. Then, responsive to such a signal, information may be copied from a volatile memory into a non-volatile memory. The non-volatile memory may be configured to provide instructions for direct execution by a processor, or the non-volatile storage may be attached via an expansion interface. The non-volatile memory may be a removable card. The copy function is typically done in low power modes. Alternatively, the information is only copied provided sufficient battery capacity remains to perform the copy function.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: A home network system with a standby power saving function and a method for saving standby power thereof, wherein various home appliances exchange information with a home server from time to time. At least one home appliance for a home network is provided in the home network system to exchange information with the home server over a network line. The home appliance includes a controller for analyzing data received over the network line and generating and outputting a home appliance control signal in accordance with the analyzed result, a load for operating/stopping the home appliance in response to the home appliance control signal from the controller, a low voltage transformer (LVT) for receiving an external voltage and supplying a drive voltage to the controller to operate the load and controller, and an LVT relay and a power supply unit for cooperating to selectively supply the drive voltage and a standby voltage to the controller according to whether the home appliance is in operation.

Abstract: A method and system for efficiently managing power consumption in a digital processor controls the CPU clock rate based on actual CPU workload by monitoring a measure of the CPU's activity to estimate the required clock speed consumption and adjusting the clock rate up or down to meet the actual estimated speed consumption. In an exemplary embodiment, a measure of the CPU's idleness is monitored and used, along with other parameters, to compute required clock speed changes.

Abstract: Power consumption by a computer system may vary all the time based upon software and the workload. Facility such as data centers host multiple of computer systems. With continuous growing demand for power and cooling of computer systems, data centers face limitations on their ability to provide the power and cooling capability. These limitations are occasionally exasperated by problems in either power or cooling systems. The computer systems may have a method to maintain total power consumption below a set target level. An enterprise power and thermal manager, EPTM, may change this setting dynamically to improve efficiency of supporting power and cooling infrastructure. In addition, the EPTM may use this ability to improve performance, availability and to provide ability to implement various administrative policies.

Abstract: The invention describes a switching power supply system for automatically regulating circuit operating power and the method thereof. The switching power supply system has a sensing and monitoring unit connected to the computer system for detecting the operating status of the computer system and outputting a detection value, a setting unit for setting a trigger condition value, a storage unit connected to the setting unit for storing the trigger condition value, a comparator unit connected to the storage unit and the sensing and monitoring unit for comparing the detection value with the trigger condition value and outputting a comparison result signal, and a dual power system switching regulator unit connected to the comparator unit and to the converter through at least one dual power system unit for receiving the comparison result signal and regulating connection/disconnection between the dual power system unit and the converter based on the comparison result signal.

Abstract: A power control driver of a BIOS has a function of changing a frequency of clock supplied to a CPU. According to the function of the power control driver, it is possible to set a normal mode for showing the CPU capability to the maximum and a power saving mode for preferentially taking power saving rather than the CPU capability. A power control utility program carries out the following power saving control. The program shifts a system to the normal mode when an AV application program operating an encoder and a decoder required for showing the CPU capability to the maximum is operating. In addition, the program shifts the system to the power saving mode when the program is not operating even if application programs other than the program are operating.

Abstract: A system and method is provided to allow a computer network system to keep a device in a powered off state over a power cycle. A service processor stores the power state information or power mask corresponding to the field replaceable unit (FRU) slots in a non-volatile storage location. As a result, after the system has been powered off and on, the power mask information is retained. Accordingly, a hotswap controller may then retrieve the power mask from storage to determine whether a given FRU should be powered on or kept in a powered off state. Depending on the power mask, the service processor will not power on the FRU if the power mask indicates that the device should remain in a powered off state. A management entity may update the power mask information depending on predetermined parameters or the condition of the FRU. As a result, a power mask may be maintained for several power cycles to keep a device in a powered off state.

Abstract: The present invention provides method, interface and computer-readable medium for enabling enclosure services in a computer system including a multi-device enclosure generally remote from a host bus adapter. The method provides a communications port between the multi-device enclosure and the host bus adapter. The method further provides a plurality of slots for removably receiving respective devices in the enclosure, with at least one of the devices comprising an Advanced Technology Attachment (ATA)-accessible device, and respective transceivers for asynchronously interconnecting the enclosure processor and the host bus adapter through the communications port.

Abstract: Embodiments of the present invention generally provide methods, apparatus, systems, and articles of manufacture for gradually dimming backlit displays. The backlit displays may be gradually dimmed by reducing a level of the backlighting from an initial level to a final level in a plurality of steps over a dimming interval. The gradual dimming operations may be performed by any suitable combination of software and hardware components. For some embodiments, parameters used for the dimming, such as the dimming interval and final level of the backlighting, may be specified by a user.

Abstract: An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Abstract: An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses.

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract: A method and apparatus for controlling the operation of an air conditioning system and a plurality of auxiliary devices, with both the air conditioning system and the auxiliary devices being adapted to operate in a setback condition. The auxiliary devices are operated in a setback condition in response to the operation of the setback operation of the air conditioning system such that, generally, the auxiliary devices are operated in a setback condition when the air conditioning system is operating in a non-setback condition and vice versa so as to thereby achieve load balancing. In addition, the auxiliary devices can, at the same time, be operated in the setback mode on the basis of duty cycle.

Abstract: A system and method to resume execution of a client system from a saved system state without executing a boot-up process. A data storage unit and the client system having volatile system memory are coupled to a network. Data stored on the data storage unit is received via the network and loaded into the volatile system memory of the client system. The data contains information for the client system to resume execution from the saved system state without executing a boot-up process after a power-off state. The client system is then capable of resuming operation from the saved system state.

Abstract: An integrated circuit provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down mode. Prior to removing the main power supply execution of data processing instructions within the instruction pipeline preceding a restart instruction are completed so as to reduce the amount of state data which needs to be stored across the power down event. Thus, a compromise is achieved between rapid power down through the use of dedicated storage cells and the circuit area requirements of such storage cells and the need to complete execution of some partially executed data processor instructions within the instruction pipeline and other operations such as, pending writes within the integrated circuit.

Abstract: Disclosed is a printer which performs efficient power save control by keeping track of the condition of each client of the printer without having to send wasteful packets, that is, without affecting the network environment. The printer includes: a unit for monitoring packets flowing on a network, and for updating and storing a client-associated last receive time each time a packet is received from any client of the printer; a unit for determining, by referring to the stored client-associated last receive time, that any client from whose associated last receive time has elapsed a prescribed time is in an idle condition, and for computing a printer usage rate by summing the past average usage rates of the clients that have been determined not to be in an idle condition; and a unit for setting, based on the computed printer usage rate, the length of time allowed before a transition is made to the power save mode.

Abstract: A method and system for power management including local bounding of device group power consumption provides the responsiveness of local power control while meeting global system power consumption and power dissipation limits. At the system level, a global power bound is determined and divided among groups of devices in the system so that local bounds are determined that meet the global system bound. The local bounds are communicated to device controllers associated with each group of devices and the device controllers control the power management states of the associated devices in the group to meet the local bound. Thus, by action of all of the device controllers, the global bound is met. The controllers may be memory controllers and the devices memory modules, or the devices may be other devices within a processing system having associated local controllers.

Abstract: In one embodiment of the present invention, a method includes determining utilization values for a plurality of processors having power utilization dependencies, and identifying a target frequency for the plurality of processors based on the utilization values.

Abstract: A computer system comprising a plurality of computing entities includes automatic power management logic that automatically transitions the system to a state in which less power is consumed when appropriate. The determination as to when this transition should occur is based on determining when demand for the processing abilities of the system are reduced. Once the decision has been made to transition to a reduced power state, the system's power management logic makes this transition in such a way to preferably minimize or at least reduce the performance impact on the system. Also, rather than altering the power state of one of the computing entities in the system, the entity can be deployed as part of another computing system.

Abstract: Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.

Abstract: Energy detect with auto pair select. The present invention is operable without ‘a priori’ knowledge of the pairs' connectivity. In addition, the present invention is operable within systems performing automatic detection of connectivity in systems that employ the Ethernet based media dependent interface crossover (MDIX). Where there has been some cross-over of pairs within the system, a situation not uncommon in many networks, the present invention is operable to perform energy management even without having any knowledge of the pair connectivity. Knowledge relating to the energy of multiple pairs is used to perform energy detect and management. A state machine operates in performing the analysis of the energy using a qualified energy level. The present invention is also operable within systems that do not employ auto-negotiation. In systems where auto-negotiation is performed, the present invention is performed before the auto-negotiation to determine if an operable partner exists within the network.

Abstract: A combination portable computer and mobile telephone device sends the portable computer portion into a sleep mode during periods of non-use; it can periodically and temporarily wake itself up so as to monitor the power consumption of a slave device, the mobile telephone, which depends on the same battery or power source.

Abstract: Performing power saving control which can be inherited and standardized easily, and which keeps power devices from having to become larger is made possible. A current In flowing through an electrical path is detected as a voltage Vs by a current detection section, and is outputted as a voltage Vout by an amplifying section. When a level corresponding to the voltage Vout exceeds a limit level, a power limit detection section outputs a power limit detection signal. When a controller receives the power limit detection signal via a detection signal holding section, the controller outputs a throttle control command signal. When a chip set receives the throttle control command signal, the chip set initiates throttle control that lowers the clock frequency of a CPU. The present invention may be applied to laptop personal computers.

Abstract: A power management controller for conserving power in a device implementing power conservation states and a calendar-scheduler is disclosed. The calendar-scheduler records calendar-based events with associated time-of-occurrences. The controller is constructed and arranged to determine a maximum duration of time the device can remain in a reduced-power state while insuring the device can perform operations associated with a calendar-based event when that event occurs.

Abstract: The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. The digital circuit includes one or more circuit elements of respective circuit element types. In the method, idle power values including idle power values for each circuit element type. The idle power values for each circuit element type correspond to different states of the inputs of a circuit element of the circuit element type. Additionally the idle power values are used to determine, for each circuit element, states of the inputs of the circuit element that would set the circuit element to a lowest-allowable idle power state when the digital circuit is in the idle state. The states determined for those of the inputs that constitute the circuit inputs define the input state vector. The states are also determined accounting for the logic constraints of the digital circuit.

Abstract: A computer system that optimizes the power efficiency of a portable computer system is described. Specifically, the secondary memory of the system is partitioned. A standard hard disk drive is used to store lower utilization applications, while a micro storage unit is used to store high utilization applications.

Abstract: A computer system includes a voltage regulator that supplies power to a component. The component may provide a signal indicating an amount of current the component consumes under a high utilization operating condition. The voltage regulator may then determine the slope of a load line using this signal.

Abstract: A system for managing utility power use by ascertaining the amount of resources to be purchased from a power supplier, identifying transactions that balance energy needs with various users, and production of schedules that maximize or minimize potential revenue from surplus energy. To accomplish this, there are studied forecasted weather, historical weather patterns, industrial and seasonal loads, and other factors affecting timing and use of power.

Abstract: A method and system for optimizing energy consumption during data file read/write operations in a battery powered disk-based memory system is provided.

Abstract: A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

Abstract: HDD boxes 831 to 83n are each incorporated with a secondary battery box 87, a non-isolated DC/DC converter 89, and an HDD 91. Logical circuit boards 851 to 85n are each incorporated with the secondary battery box 87, fast-transient-response-type non-isolated DC/DC converters 931 to 933, and a plurality of loads 951 to 953. Every secondary battery box 87 is provided with a charge/discharge circuit 97, and a plurality of in-line secondary batteries 99. In the HDD box, the output voltage from the secondary battery box 87 goes to an HDD 91 via the DC/DC converter 89. In the logical circuit board, the output voltage from the secondary battery box 87 goes to the corresponding loads 951 to 953 via the DC/DC converters 931 to 933. With such a structure, in a disk array apparatus, realized are higher energy efficiency and less space occupation through reducing power loss and optimizing power capacity setting for a backup power.

Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A method and device is disclosed for implementing dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one or several hardware units (201, 202, 203), a hardware based power control logic (204) substantially implemented with logic circuits, as well as a programmable power control mode register (208) containing information about powered-down modes defined for said one or more hardware units. To transfer a single hardware unit (201, 202, 203) from the powered-down mode to the operational mode, the hardware unit transmits to the power control logic (204) a first level sensitive status signal (201a, 202a, 203a) for transferring the hardware unit from the powered-down mode to the wake up mode, and further a second level sensitive status signal (201b, 202b, 203b) for transferring the hardware unit from the wake up mode to the actual operating mode.