Abstract: An information processing apparatus that is powerable by a battery includes a main body in which the battery is detachably mounted, a processor that is provided in the main body, a unit that acquires battery type information that is indicative of a rating of the battery from the battery that is mounted in the main body, and a control unit that executes a power control process that sets an upper limit of an operation speed of the processor in accordance with the acquired battery type information.

Abstract: An electronic circuit having built-in self testing capabilities for optimizing power consumption. Typically, the electronic circuit includes a component circuit that operates at some known or unknown optimal operating power level. Further, the electronic circuit includes a power supply coupled to the component circuit such that the power supply provides power to the component circuit. Further yet, the electronic circuit includes a test circuit coupled to the component circuit and coupled to the power supply. The test circuit is operable to monitor the power supplied to the component circuit and operable to control the power supply. In an iterative manner, the test circuit reduces the power supplied to the component circuit until the power supplied to the component circuit is operating at the optimal operating power level.

Abstract: A method and system of controlling powers of a plurality of servers with a power control command mechanism. The system for controlling powers of a plurality of servers compatible with an intelligent platform management interface comprises a console unit, a command mechanism and a plurality of control modules. The console unit generates a request to control a plurality of powers of the servers. The command mechanism coupled to the console unit transforms the request coming from the console unit into a plurality of commands and sends the commands to the servers sequentially; and the control modules coupled to the command mechanism and corresponding to the servers respectively implement the commands to control the powers of the servers sequentially.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Abstract: An information handling system (IHS) includes a system board including a processor, a first battery for supplying power to the system board, a second battery for supplying power to the system board, and a switching circuit. The switching circuit is configured to repeatedly switch between the first battery and the second battery for supplying power to the system board to provide more power to the IHS than is possible if only one battery were continuously providing power to the IHS.

Abstract: A computer including a CPU, a power output unit to output driving power needed for driving the CPU, a CPU state output unit to output a first state information signal when it is detected that the CPU is driven in a power saving mode, a signal switching unit to output the second state information signal when the first state information signal is maintained beyond a predetermined reference time, and a PWM control unit to control the power output unit to output the driving power having a first level corresponding to the power saving mode upon receipt of the second state information signal from the signal switching unit. Thus, embodiments of the present invention set forth a computer reducing the generation of noise from a power management of a CPU.

Abstract: The disclosed systems and methods relate to improving PCI Express (PCI-E) L1 Active State Power Management (ASPM) exit latency by speculatively initiating early L1 exit based on a network stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may minimize operational cost by reducing latency in processes that utilize a PCI-E interface. Aspects of the present invention may be embodied in a Network Interface Controller (NIC) or any other device with a PCI-E interface that supports ASPM.

Abstract: A display control device and a display control method for use in a portable electronic apparatus are disclosed. The portable electronic apparatus includes a main controller and a display panel. The display control device includes a digital data register in communication with the main controller for storing a digital data display signal received from the main controller, and a digital-to-analog converter in communication with the digital data register, converting the digital data display signal stored in the digital data register into an analog data display signal and outputting the analog data display signal to the display panel to be revealed. The main controller keeps on outputting refreshed digital data display signals in a normal mode, and suspends the output of any further digital data display signal in an idle mode. In the idle mode, the digital data register reiteratively outputs a last stored digital data display signal to the digital-to-analog converter.

Abstract: A USB control system includes a first voltage controller, a control switch, a second voltage controller, and a PHY unit. The first voltage controller outputs a first internal voltage from an external voltage and a reference voltage, and the control switch regulates supplying and suspending the external voltage. The second voltage controller outputs a second internal voltage from the reference voltage and the external voltage applied through the control switch, and the PHY unit receives a request from a host using the first or second internal voltage as a voltage source. The power for certain internal blocks is suspended to reduce power consumption in the USB control system during a power-saving mode.

Abstract: A system that causes a computing device to enter a hibernation mode. During operation, the system creates a hibernation image for the computing device by identifying processes that do not have visible user interface elements, and generating the hibernation image so that processes with visible user interface elements can be reanimated from the hibernation image first to get the computing device reanimated quickly, while the identified processes are reanimated later. Next, the system stores the hibernation image in non-volatile storage. The system then causes the computing device to enter the hibernation mode, wherein the active state of the computing device is preserved in non-volatile storage while power to volatile storage is turned off.

Abstract: Embodiments of the current invention describe an approach for configuring a platform resource table. The platform resource table is configured using information from both the platform management system and the platform resource provider system. The platform resource table is then communicated to the platform resource provider system via a platform interface to select and invoke platform state transitions to improve power efficiency.

Abstract: A method is provided that includes receiving a classification voltage at a powered device from a powered network and providing a classification signature to the powered network in response to receiving the classification voltage to specify a power requirement of the powered device. The method further includes deriving a reference current within the powered device and adjusting a current limit as a function of the reference current.

Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.

Abstract: A method of N-division algorithm for switching operation voltage of CPU is provided. The method of N-division algorithm comprises the following steps, comparing desired operation voltage and original operation voltage of CPU to obtain a differential value for switching high and low potential level of operation voltage. Further, dividing the differential value by N times, and the N number is depending on tolerant variate of operation voltage of CPU and the differential value. Furthermore, having a unit by a tolerant variate of operation voltage of CPU for switching the original operation voltage of CPU further by the N times for adjusting operation voltage to desired one.

Abstract: Energy detect with auto pair select for energy management without ‘a priori’ knowledge of the wire pairs connectivity. The energy detect with auto pair select is operable within systems performing automatic detection of connectivity in systems that employ the Ethernet based media dependent interface crossover (MDIX). Where there has been some cross-over of pairs within the system, a situation not uncommon in many networks, the energy detect with auto pair select is operable to perform energy management without knowledge of the pair connectivity. Selection or detection of coupled wire pairs is acquired by energy detection of coupled wire pairs via a state machine that analyzes a qualified energy level.

Abstract: A system and method for implementing a common control bus in a multi-regulator power supply integrated circuit. The integrated circuit may, for example, comprise first and second power regulator modules that control at least one characteristic of respective power signals. The integrated circuit may also, for example, comprise a communication interface module that receives power control information related to operation of the first and second power regulator modules over a shared data bus. An exemplary method may, for example, comprise receiving power control information over a data bus. The method may also, for example, comprise determining which of a plurality of power regulators corresponds to the received power control information. The method may further, for example, comprise determining a regulator control signal, based at least in part on the received power control information, and provide the regulator control signal to the determined regulator(s) to control operation of the determined regulator(s).

Abstract: Adjusting input power in response to a clock frequency change is disclosed. In some embodiments, a clock signal is input into a buffer, and if an increase in clock frequency is detected at the buffer input relative to the buffer output, the supplied power is increased so that an increased supplied power is provided to an associated system before the increased frequency clock signal is output from the buffer and applied to the system. In some embodiments, the current operating frequency is compared with the operating frequency associated with the next operating state. If the next operating frequency is higher than the current operating frequency, the supplied power is increased, and application of the next operating frequency is delayed so that the next operating frequency is not applied before the increased supplied power is available.

Abstract: A computer system includes an operating system. An advanced configuration and power interface (ACPI) system is in communication with the operating system and receives an ACPI request from the operating system. A cache is in communication with the ACPI system and receives the ACPI request from the ACPI system and provides ACPI data to the operating system via the ACPI system.

Abstract: The present invention features a personal computing device that may be powered by a single battery having a single lithium-ion cell or by a plurality of lithium-ion cells connected in parallel. The personal computing device may provide computing power comparable to that of conventional laptop computers and execute an operating system and application software comparable to that executed by conventional laptop computers. Furthermore, the battery's time between charging, when used to power the personal computing device, may be similar to the time between charging of a multi-cell battery when used to power a conventional laptop computer.

Abstract: A method and system are disclosed to enable and control power reduction in a blade/chassis system. A “maximum power reduction” attribute is stored in the VPD of the blade (or can otherwise be input to or retrieved or calculated by the management entity). The management module of the chassis in which the blades and power supplies are located uses this information to manage the power reduction of blades when the system is operating in an over-subscription mode and a power supply fails. If throttling is required, the system knows the amount of power reduction available for each blade and controls the throttling by spreading it out among the blades in the system so that, ideally, no blade will cease operation altogether.

Abstract: A remote access power (“RAP”) hub for kiosks and information booths with multiple peripherals. The RAP hub provides power at different levels to accommodate different electronic devices and peripherals. The RAP hub also acts as a powered USB hub for connecting multiple USB devices to the devices and peripherals. The RAP hub further has communications functionality so that signals can be transmitted through a network to the hub for controlling the devices and peripherals remotely. The RAP hub is an all-in-one power hub with various power outputs and remote access command. It is designed to support and manage a number of devices and peripherals while avoiding multiple power adapters. A connector block allows the routing of power within multifunction devices, thus eliminating the need for special-ordered wiring harness.

Abstract: Embodiments of the present invention are directed at identifying an idle state for a processor that minimizes power consumption. In accordance with one embodiment, a method for identifying a target idle state that does not require a linear progression into any intermediate states is provided. More specifically the method includes collecting data from a plurality of data sources that describes activities occurring on the computer and/or attributes of the hardware platform. Then, using the collected data, a target idle state for the processor is calculated. Finally, if the current idle state of the processor is different than the target idle state, the method causes the idle state of the processor to be changed to the target idle state.

Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.

Abstract: Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

Abstract: Embodiments of the present invention are directed at minimizing power consumption of a computer while permitting the execution of meaningful tasks by programs installed on the computer. In accordance with one embodiment, a method that implements power conserving measures based on the amount of capacity that is available from a power source is provided. More specifically, the method includes identifying the current amount of power that is available from a power source. Then a determination is made regarding whether the current amount of power available is associated with a reduced performance state. If the current amount of power is associated with a reduced performance state, the method changes the configuration of the power consuming devices to place the computer in the reduced performance state.

Abstract: A power supply system for personal computers aims to provide an additional sub-power supply needed when a personal computer requires a power greater than what can be provided by the original main power supply. This invention provides a sub-power supply in the spare space of the existing chassis of the personal computer without removing the main power supply to augment the power supply. The starting power of the sub-power supply is provided by the main power supply. Hence when the personal computer is in the machine stop condition, only the main power supply consumes electric power. Thereby this invention can preserve a green power.

Abstract: Reducing power to a minimum permissible value based on temperature of a component may permit savings in power consumption.

Abstract: A controller in PSE (Power Sourcing Equipment) controls how to provision uninterruptible power through corresponding ports (and cables) of the PSE to network devices. For example, the controller of the PSE receives a signal indicating a transition of powering the PSE from a primary power input to a backup power supply. The backup power supply has a limited ability to provide backup power to the PSE. In response to receiving the signal, the controller of the PSE utilizes a powering/de-powering algorithm to generate control information used by the controller to selectively discontinue providing power through the certain ports to respective network devices. Consequently, the PSE and, more specifically, the controller provisions power from the PSE depending on a priority level associated with network devices, extending the power life of critical powered network devices and more efficiently using the backup power supply in the case of a power failure.

Abstract: A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.

Abstract: Methods and apparatus to reduce power consumption in arbiters of interconnection routers are described. In one embodiment, an arbiter may be turned off for a select number of clock cycles if no arbitration is to be performed on the corresponding buffer.

Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

Abstract: A system and method for information preservation on a portable electronic device. A signal indicating an energy capacity threshold remaining in the battery of a hand held device may be generated. Then, responsive to such a signal, information may be copied from a volatile memory into a non-volatile memory. The non-volatile memory may be configured to provide instructions for direct execution by a processor, or the non-volatile storage may be attached via an expansion interface. The non-volatile memory may be a removable card. The copy function is typically done in low power modes. Alternatively, the information is only copied provided sufficient battery capacity remains to perform the copy function.

Abstract: An information processing apparatus includes an information processing unit, an interface supplying electrical power to and communicating a signal with an external electronic device through a single connector, a unit supplying electrical power to the electronic device through the interface and including a rechargeable battery. Detection units detect a connection of the electronic device to the apparatus, an external power supply. The power supply control, when the connections are detected, keeps supplying electrical power to the electronic device through the interface even after deactivation of the apparatus, in the event an instruction to turn off a power supply of the apparatus or deactivate the apparatus is issued. When the connection of the external power supply for charging the rechargeable battery to the apparatus is not detected, the power supply does not supply electrical power to the electronic device even during operation of the apparatus.

Abstract: In at least some embodiments, a multi-processor power module comprises components that are replicated at least for each of the plurality of processors. The multi-processor power module further comprises control logic that is configured to detect a demand from each of the plurality of processors and to direct the replicated components to provide a regulated power based on the demand, the regulated power being output for sharing among the plurality of processors.

Abstract: A power consumption control method for collectively controlling the power consumption of electronic apparatuses connected to a network is provided. When an electronic apparatus is connected to the network, a management device performs power-saving control for the electronic apparatus. When the electronic apparatus is disconnected from the network, the electronic apparatus performs the power-saving control for itself. Thus, the power consumption of the clients connected to the network can be effectively reduced.

Abstract: An optical recording apparatus with a small form factor optical drive for driving an optical record carrier is operable in different accessing modes having different data rates depending on the power mode of the recording apparatus. A Switch is provided in the recording apparatus for switching a controller for accessing the optical record carrier for reading data from or recording data to the optical record carrier. A first accessing mode has a low data rate and is used in a low power mode, while a second accessing mode has a high data rate and is used or allowed to be used in a high power mode.

Abstract: A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. When the motherboard powers up, the clock selector sends the peripheral device an external clock signal from the motherboard.

Abstract: A controller includes a first memory of non-volatile that stores a program; a processor that executes the program; and a second memory that provides a work area for the processor. In this controller, the processor executes the program read from the first memory and stored in the second memory as a first mode, and executes the program stored in the first memory as a second mode.

Abstract: An on-die voltage regulator having a suspend mode voltage generator and an active mode voltage generator. Output drivers of the active mode voltage generator are disabled in stages to reduce voltage droop when transitioning between the active mode voltage generator and the suspend mode voltage generator.

Abstract: A system has a power consuming component, power source circuitry, and power control circuitry. The power source circuitry is to supply power from a number of different sources, including some extracted from a local area network (LAN) cable that is attached to the system. The power control circuitry is to supply the power to operate the component from all of the different sources.

Abstract: Improved techniques involve provisioning power for a remote device through a data communications cable. Such techniques involve providing a first electrical stimulus (e.g., a first voltage, V1) to the data communications cable and the remote device, and sensing a first electrical response (e.g., a first current, I1) to the first electrical stimulus from the data communications cable and the remote device. Additionally, the techniques involve providing a second electrical stimulus (e.g., a second voltage, V2) to the data communications cable and the remote device, and sensing a second electrical response (e.g., a second current, I2) to the second electrical stimulus from the data communications cable and the remote device, the second electric stimulus being different than the first electrical stimulus. Furthermore, the techniques involve identifying a power demand for the data communications cable and the remote device. The power demand is based on the first and second electrical responses.

Abstract: An embodiment may comprise a counter to provide a count value, enable logic coupled with the counter, and circuitry coupled with the enable logic, the circuitry to be powered up or down if the counter value is outside of a resonance bandwidth for the circuitry to be powered up or down. An embodiment may comprise a method of initializing a counter while circuitry is placed in a standby mode, reading the counter, and powering up the circuitry if the counter does not indicate a resonance bandwidth. An embodiment may be a system comprising a device including a power delivery network to deliver power, a link coupled with the device, the link to electrically communicate with the device, and control circuitry coupled with the link, the control circuitry to limit the link from powering up or down at a resonant frequency of the power delivery network.

Abstract: A USB control circuit for saving power and the method thereof employs a first logic circuit to generate a control signal that turns on the power of a transmitting module, so as to enable the transmitting module just before sending data. The above-mentioned USB control circuit and the method thereof also employs a second logic circuit to select the control signal, so as to solve the problem in USB handshaking processes and to provide a selection for changing the control signal.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: The invention relates to a standby circuit, an electrical device with a standby circuit, a method for the control of the electrical device and a power supply assembly. Whereas the power supply unit and the control electronics are in permanent operation when conventional devices are in the standby mode and consequently have a high power consumption, the invention proposes a solution for saving energy while retaining convenience of operation by which the power supply unit is switched off in the standby mode. A standby circuit, preferably fed by an energy buffer element, remains active in the standby mode and monitors signal inputs for activation events. When an activation event occurs, the standby circuit switches on the power supply unit.

Abstract: An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Abstract: A multifunctional device shifts the states of plural reception units from a state that the device operates in a power saving state to a state that the device operates in an operating state, according to which of the plural reception units a reception request of data is input to. The multifunctional device can shorten a time from the reception of the reception request of the data to the reception unit to a start of a data process of the data.

Abstract: One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the clock frequency to the new clock frequency. More specifically, the system starts an iteration by slewing the clock frequency toward the new clock frequency by an increment to reach an intermediate frequency without interfering with normal memory-system operation. Next, the system signals a memory controller to pause normal memory system operation by completing or cancelling all in-flight or outstanding memory system operations and not accepting additional memory operation requests.