Abstract: A low power media player is provided for an electronic device, such as a hand-held portable computer having capability to operate an application during a low power mode. During the low power mode, portions of hardware, software, services, and/or other components of the portable computer that are not necessary to the operation of the low power media player are suspended or otherwise deactivated. Rather than repeatedly accessing a hard disk to read media files for playback, the low power media player limits its number of access operations by reading as many media files as possible during each access operation, and then caching the read media files. When playback of the media files is to be performed, the media files are read from the cache, thereby reducing the amount of power consumption attributable to hard disk access operations.

Abstract: A rack equipment power purchase plan supervision system and method is presented. In one embodiment of the present invention, a rack equipment power purchase plan supervision system includes rack equipment for processing information. The rack equipment is supervised by a rack equipment power purchase plan supervision component in accordance with a power purchase plan. The power purchase plan defines operational settings of the rack equipment for various power supply conditions. A communication bus for communicating information communicatively couples the power purchase plan supervision component and the rack equipment.

Abstract: A system and method for improved activation of a personal computer and/or other processing devices is provided. Power and security states are combined and further reduced to three activation states which may be operated by a single secure device. The system may include any number of activation states for operating the computer using only the single secure device. The secure access device handles both security and power management by authenticating physical access to the computer and the identity of the user. For this purpose, a device containing a biometric reader may be integrated with a smart card and the biometric identification used as an authentication code to secure the smartcard. The secure access device may be inserted into a locking mechanism used by the user to transition between activation states.

Abstract: A printing apparatus is equipped with multiple interfaces adapted to connect external devices adapted to store image data and operated by power supplied from a first-connected external device, and is adapted to print images stored in the external devices. The state of the connection of the external devices to the plurality of interfaces is detected and, when it is determined that a plurality of external devices are connected to the printing apparatus, a determination is made as to whether or not an amount of power required by the plurality of external devices exceeds the amount of power the printing apparatus is capable of supplying. If the amount of power requested exceeds capacity, then the apparatus selects which external device to supply with power depending on the operating state of the first-connected external device.

Abstract: A method for monitoring the operating readiness of memory elements which are assigned to an electronic unit, an engine control unit for example. Furthermore, an electronic unit for executing the method and a computer program, as well as a computer program product are described. In the method described, a supply voltage of the electronic unit is monitored to ensure error-free operation of the memory elements.

Abstract: A power supply subsystem configured for connection between a LAN switch and at least one node, the power supply subsystem providing electrical power to the at least node over communication cabling, the power supply subsystem comprising: a management and control unit; at least one port for connection to a LAN switch; a combiner combining power into the communication cabling substantially without interfering with data communication between the LAN switch and the at least one node; and current limiting circuitry controlling current of the power delivered into the communication cabling via the combiner, wherein the management and control unit is operative to interrogate the at least one node to which it is intended to transmit power over the communication cabling in order to determine whether the node's characteristics allow it to receive power over the communication cabling.

Abstract: Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Abstract: A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be processed using “lower-precision” units with power efficient circuitry without any quality and performance sacrifice (e.g., realism, resolution, etc.). By classifying the primitives and selecting the more power-efficient processing unit to process the primitive, power consumption can be reduced without quality and performance sacrifice.

Abstract: A maximum power usage setting for a computing device is based on one or more of: a user-specified setting corresponding to how often a frequency of a processor of the computing device is likely to have to be decreased to reduce power usage by the computing device; an average frequency of the processor during a previous period in which the computing device was operated; a minimum frequency of the processor during the previous period; a maximum power that the computing device used during the previous period; and, a nominal frequency of the processor. When the computing device starts to use more power than the maximum power usage setting, the power used by the computing device is reduced so as not to exceed the setting, such as by decreasing the frequency at which the processor operates.

Abstract: A method for increasing an operating rate of a graphics card includes: raising a rotation rate of a radiator fan of a graphics processing unit chip of the graphics card to a first rotation rate according to a rate increasing command; raising a voltage inputted to the graphics processing unit chip to a first voltage, and raising a voltage inputted to a memory of the graphics card to a second voltage when the rotation rate of the radiator fan is approximately equal to the first rotation rate; and raising a timing of the graphics processing unit chip to a first timing, and raising a timing of the memory to a second timing when the voltage inputted to the graphics processing unit chip is approximately equal to the first voltage, the voltage inputted to the memory being approximately equal to the second voltage.

Abstract: An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A system and method for selecting a computer hardware component of a computing system to throttle based on a selection policy is disclosed. A co-thermal control system may receive a first signal indicating a first condition for a plurality of computer hardware components has occurred. The co-thermal control system may choose a course of action at least partially based upon the first signal using a table-based rule generator. The co-thermal control system may output instructions to participating components for the course of action.

Abstract: A computer system includes a memory module. Power management in the computer system is performed with at least one temperature rise parameter (?Tx) of the memory module.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: A power control method for a magnetic disk unit is disclosed. The method includes identifying a type of a last instruction sent to a magnetic disk unit and, in response to identifying the type, setting a wait time that varies according to the type. In response to the wait time having elapsed after a completion of processing ordered by the last instruction, an idle instruction is sent to the magnetic disk unit for placing the magnetic disk unit in an idle state in which power consumption is reduced.

Abstract: Embodiments include methods, apparatus, and systems for managing power consumption in a computer system. One embodiment includes a method that queries a blade for its power requirements when the blade is inserted into a blade computer enclosure. The method then determines, by the blade computer enclosure, whether the power requirements of the blade are within a power budget of the blade computer enclosure.

Abstract: A variable speed data processor includes a clock generator generating a plurality of clocks at different clock rates. Clock select circuitry synchronously selects one of the clocks as an output clock signal to data processing circuitry, based on a data activity indication. Activity logic generates the data activity indication based at least in part on the existence of data processing activity targeted to the data processing circuitry. When the data processing circuitry experiences bursty data processing activity, the clock rate can shift rapidly between the multiple clock rates, conserving power without substantially diminishing the availability of the data processing circuitry.

Abstract: A computer including a central processing unit, a cooling fan, an operating system (OS), a temperature sensor sensing a temperature within the CPU, a mode selector for selecting one of a fan off mode and a fan on mode for the cooling fan, a microcomputer controlling the cooling fan based on a selected mode, and outputting a selection signal corresponding to the selected mode, and a BIOS controlling a clock frequency of the CPU based on a sensing result of the temperature sensor if the BIOS receives the selection signal corresponding to the fan on mode from the microcomputer, and allowing the OS to control the clock frequency of the CPU if the BIOS receives the selection signal corresponding to the fan off mode. Here, a computer system can permit a user to turn on/off a cooling fan and efficiently control heat generated from the CPU.

Abstract: A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

Abstract: Provided is a multiprocessor control apparatus that restrains impairment of processing speed of entire operations, while pursuing power consumption saving for a multiprocessor. The multiprocessor control apparatus has: an execution control unit operable to control a processor to, when processors other than the processor have ended respective operations performed in parallel, start performing an operation that uses a result of the operations; and a power control unit operable to control power supply to the processor, where when the processor has been under power-supply restriction, the power control unit cancels the power-supply restriction before one of the other processors, which is the last of all the other processors to end a corresponding operation, ends the corresponding operation.

Abstract: An apparatus and method are provided which preferably combines temperature sensing and prediction for more accurate temperature control of integrated circuits. An IC temperature sensing and prediction device includes a current sensing device that measures current passing through an IC, and a temperature control apparatus that measures a surface temperature of the IC. The device further includes an electronic controller that calculates the power consumed by the IC according to the measured current and adjusts the temperature of a heater or cooler responsive to the measured surface temperature and power consumption.

Abstract: A computer program product is for use with a computer that includes a communication interface for sending and receiving information over a communication network and that is connected to an uninterruptible power supply (UPS) that monitors and supplies information regarding power status associated with the UPS. The computer program product resides on a computer-readable medium and includes computer-executable instructions for causing the computer to process data received from the UPS to which the computer is coupled to produce indicia of changes in power status associated with the UPS, provide the indicia of changes in power status associated with the UPS to the communication interface destined for a remote device, and provide geographic information associated with the indicia of changes in power status that indicates a geographic location associated with the UPS.

Abstract: A digitally controlled device is provided to interface between a user of adjustable power unit and an adjustable power module, where the user provides an analog user input signal for adjusting the performance of the adjustable module using a user defined standard. The digitally controlled device provides the adjustable power module an analog input signal adapted to the standard used by the module. The digital controller device for controlling adjustable power module that comprises at least one analog to digital converter for converting analog user input signal to digital input, a micro-controller adapted to receive the input digital information and operate at least one digital to analog unit in response to the digital input information and at least one digital to analog converter unit adapted to produce analog input signal for controlling adjustable module.

Abstract: A semiconductor integrated circuit includes a module configured to operate based on a clock signal, a voltage controlling unit configured to change a power supply voltage supplied to the module, a clock generating unit configured to supply the clock signal to the module, and a test circuit configured to operate at the power supply voltage based on the clock signal to emulate a delay of a critical path provided in the module, thereby testing whether the module properly operates at the power supply voltage, wherein the clock generating unit supplies a different signal, in place of the clock signal, to the module while the voltage controlling unit is changing the power supply voltage.

Abstract: A power management system for electrical and electronic apparatus has a number of components which may be switched to a low power state. A power controller (20) is coupled to each component in the apparatus and a plurality of power modules (22, 24, 26) are each associated with a component. Each power module is coupled to the power controller for each component its associated component makes use of. It sends signals to that power controller indicating whether or not its associated component wishes to make use of the component coupled to that power controller. The power controller switches its component to a low or high power state in dependence on the received signals.

Abstract: Provided is a method and apparatus for managing the power of a portable computer system, in which a convenient user interface is provided. The method includes calculating a range of a desired time-of-use based on power consumption of the portable computer system and a remaining battery capacity at a minimum power level of the portable computer system, providing the calculated range of the desired time-of-use and a desired time input box that allows a user to input the desired time-of-use, inputting the desired time-of-use through the desired time input box, and resetting the power level of the portable computer system according to the input desired time-of-use.

Abstract: A data processing device which can communicate with a computer terminal, comprises: a receiver to receive data transmitted from the computer terminal; a shifter to shift a state of the data processing device to a power saving state, after elapse of a predetermined time; and a releaser to release the power saving state according to specific data transmitted from the computer terminal, wherein, after the power saving state was released by the releaser, when the received data is first kind of data, the shifter shifts the data processing device to the power saving state after elapse of a first predetermined time, and, when the data received by the receiver is second kind of data different from the first kind of data, the shifter shifts the data processing device to the power saving state after elapse of a second predetermined time different from the first predetermined time.

Abstract: An object of the invention is to provide an image processing device having a sub-system performing a power saving control to support the use of a USB device or provided to allow the supporting of the use of a USB device, in which operational mismatching which may occur at a start of a the power saving mode between the USB device and a USB device driver provided in the main system of the image processing device can be effectively suppressed.

Abstract: A rack equipment power pricing plan control system and method is presented. In one embodiment of the present invention, a power pricing plan rack equipment control method is utilized to control operation of rack equipment. A power pricing plan for operating the rack equipment is established. The rack equipment is operated in accordance with the power pricing plan.

Abstract: Systems and methods for providing an extended battery system for a docking component such as a media slice. The extended battery system may be a high capacity battery system provided to power components of the docking component and to provide a relatively longer battery life than a conventional non-high capacity battery system. The docking component may be configured to be capable of charging the extended battery system, and/or the extended battery system may be configured so that it is also capable of use with a portable information handling system (e.g., notebook computer) that is configured for docking with the docking component. The extended battery may be configured as a frontal extending battery system for use with a docking component and/or portable information handling system.

Abstract: In a communications system, such as a Power-Over-Ethernet system, where power supply equipment (PSE) supplies power to powered requiring devices (PRDs), a system and method of dynamic power management is implemented. The system and method monitors the power consumed at each port by the PRDs. Based on this monitoring, the PSE dynamically determines the minimum power which can be allocated to each PRD, and so dynamically maximizes the available reserve power. The PSE maintains a queue or queues wherein PRDs are listed in order of a power allocation priority. When additional power is available, the PSE preferentially allocates power to a PRD or PRDs which have higher priority. The system and method of the present invention minimizes the power allocated to each individual network device, as a result of which the total number of network devices that can be supported with the available power may be maximized.

Abstract: An apparatus adapted to facilitate execution of task or tasks in response to a detection of an occurrence of one of one or more particular wake events while a system is in a reduced power consumption state, with the system remaining in the reduced power consumption state during the execution of the task, is described herein.

Abstract: A portable information handling system (IHS) is provided. The portable IHS includes a processor and a memory device coupled to the processor. The memory device is for storing instructions processable by the processor for determining whether a lid of the portable IHS is closed. Also, the instructions are processable by the processor for, in response to determining that the lid of the portable IHS is closed, determining whether the portable IHS is operating within a substantially sealed case. Moreover, the instructions are processable by the processor for, in response to determining that the portable IHS is operating within a substantially sealed case, reducing the portable IHS power consumption.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance is not critical. In one embodiment of apparatus the microprocessor is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator. In another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical. The shift in oscillator speed is mediated by a flip-flop latch circuit connected between one or more clock oscillators and the oscillator input of the controlled microprocessor.

Abstract: A system which includes a disk drive or other storage device coupled to a host system provides for reduction of the amount or rate of drive power consumption using procedures which are at least partially executed on the host. The system can be configured to reduce average power draw, maximum power draw, or both. Host-based procedures can be tailored to specific and/or changing environments and can decrease some or all expenses associated with previous attempts to reduce HDD power consumption.

Abstract: A processor-based system accessing a performance profile for a program executing on a predetermined data set, executing the program on the predetermined data set, and governing processor speed in a predictive manner based at least in part on the performance profile.

Abstract: One embodiment of the present invention provides a system for implementing a sleep proxy. The system starts by receiving a request at the sleep proxy for information pertaining to a service provided by a device. In response to this request, the system determines if the device is a member of a list of devices for which the sleep proxy takes action. If so, the system determines if the sleep proxy can answer the request. If so, the sleep proxy sends a response to the request on behalf of the device. In a variation on this embodiment, if the system cannot answer the request on behalf of the device, the system sends a wakeup packet to the device, wherein the wakeup packet causes the device to exit a power-saving mode so that the device can respond to the request directly.

Abstract: An electronic apparatus having the plurality of components, includes a storage section configured to store a plurality of power control profiles each defining different control information for executing power control with respect to each of the plurality of components, an environment determining section configured to determine at least each kind of currently applying power and network, a profile select section configured to select one of the plurality of power control profiles stored in the storage section based on a result determined by the environment determining section, and a power control section configured to execute power control based on control information defined in the power control profile selected by the profile select section.

Abstract: A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be processed using “lower-precision” units with power efficient circuitry without any quality and performance sacrifice (e.g., realism, resolution, etc.). By classifying the primitives and selecting the more power-efficient processing unit to process the primitive, power consumption can be reduced without quality and performance sacrifice.

Abstract: A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be processed using “lower-precision” units with power efficient circuitry without any quality and performance sacrifice (e.g., realism, resolution, etc.). By classifying the primitives and selecting the more power-efficient processing unit to process the primitive, power consumption can be reduced without quality and performance sacrifice.

Abstract: A technique to adjust a processor's operating voltage dynamically while preventing a user from placing the processor into a harmful operating voltage state in relation to the core/bus frequency ratio of the processor. More particularly, embodiments of the invention relate to a technique to control the operating voltage of the processor as a function of the processor's bus and/or core clock frequency.

Abstract: A method and system are provided for dynamically managing delivery of power to partitionable elements in a computer system while supporting terms of a Service Level Agreement (SLA). Parameters of the SLA are gathered in conjunction with the topology of the computer system. Transactions associated with the SLA are monitored and high and low usage periods are predicted based upon a history of transactions. Power to partitionable elements of the computer system may be adjusted during high and low usage periods. In addition, dynamic management of the partitionable elements is provided in response to current demands. Management of the partitionable elements are all made in compliance with the SLA.

Abstract: A method of allocating power to ports in an Ethernet switch, including: (1) determining the available capacity of a power pool used to supply the ports, (2) assigning a configuration power to each of the ports, (3) selecting a port to be enabled, (4) determining whether the available capacity of the power pool exceeds the configuration power assigned to the selected port, and, if the available capacity of the power pool exceeds the configuration power assigned to the selected port, then (4) subtracting the configuration power assigned to the selected port from the available capacity of the power pool, (5) enabling and powering the selected port and simultaneously detecting whether the selected port is connected to a powered device, and (6) adding the configuration power assigned to the selected port to the available capacity of the power pool if the port is not connected to a powered device.

Abstract: A network device may comprise an auxiliary processor to conserve the power of the network device. The auxiliary processor may modify one or more definition parameters of the programmable processing unit based on determining that the load value of the programmable processing unit is lower than a threshold value. The modifying of the definition parameters may comprise reducing an operating frequency of the programmable processing unit, reducing a number of a micro-programmable units resident on the programmable processing unit, or both.

Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

Abstract: If supply of power from a main power source is insufficient but power being supplied from a communication interface (such as a USB interface) is sufficient, an image sensing apparatus (such as a digital video camera or digital camera) supplies power from the communication interface to a limited number of components. As a result, the image sensing apparatus is capable of functioning as a bus-powered device.

Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Abstract: A dynamic performance circuit adjustment system and method that flexibly adjusts the performance of a logic circuit. The dynamic performance circuit adjustment system and method facilitates flexible power conservation. In one exemplary implementation, a dynamic performance adjustment control circuit controls performance adjustments to a logic circuit (e.g., a processor) and adjusts support functions for the logic circuit. The logic circuit performs operational functions (e.g., processing) or tasks that have different performance requirements. For example, some tasks performed by the logic circuit are required to be performed in a relatively short duration of time and other tasks performed by logic circuit have relatively longer time limitations.