Abstract: A mobile device includes a file storage portion, a file reading portion, an index creating portion, an electric storage portion, an electric energy input/output portion, and an index creation determining portion. The file storage portion stores files. The file reading portion is capable of reading the contents of the files stored in the file storage portion. The index creating portion controls the file reading portion so as to read the contents of the files stored in the file storage portion and creates index data that can be used for searching of the contents of the files read by the file reading portion. The electric storage portion is capable of being charged/discharged. The electric energy input/output portion is capable of acquiring electric energy input from the electric storage portion and an external power source, and is capable of outputting electric energy to the electric storage portion, the file reading portion, and the index creating portion.

Abstract: A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.

Abstract: In general, the disclosure is directed to techniques for reducing power consumption within computing devices, such as wireless communication devices. A device dynamically adjusts the CPU clock frequency based on CPU load in order to reduce power consumption. The device monitors the load of the CPU using a number of sample interrupts. The device determines whether to adjust the clock frequency based on the monitored load of the CPU. In general, the device increases the clock frequency when the load of the CPU is high and decreases the clock frequency when the load of the CPU is low.

Abstract: One embodiment disclosed relates to a system for power management of a group of computers. The system includes server side infrastructure (SSI) circuitry at each computer in the group and a centralized power management module (CPMM). The SSI circuitry includes local monitoring circuitry coupled to a central processing unit (CPU) of the computer. The CPMM has a management link to the SSI circuitry at each computer in the group. The local circuitry at each computer monitors power consumption at the CPU of that computer and transmits power consumption data to the CPMM. The CPMM applies a set of rules to the power consumption data to determine when and at which computers to enable and disable a CPU power throttling mode.

Abstract: The present invention relates to reduction of power consumption of electronic mass storage devices, and more particularly to such a reduction of power consumption in mobile infotainment products. These devices are equipped with a subsystem comprising a mass storage device (48) and a buffer memory (43, 44). The size of the buffer memory (43, 44) is adapted in such a way that optimally low power consumption is achieved. This accomplishment by activating or deactivating memory banks (45) comprised in the buffer memory chips. The amount of memory banks (45) activated is determined by operating characteristics of the subsystem, e.g. a desired bit-rate to be achieved for transmissions to/from the mass storage device (48).

Abstract: A semiconductor device comprises a semiconductor substrate, a basic module having a memory cell unit composed of first nonvolatile memory cells or a processor unit on a part of the substrate, an authentication module which has second nonvolatile memory cells in an area different from that of the basic module on the substrate, and stores an authentication code, and a lifetime control module which has aging devices configured by third nonvolatile memory cells in an area different from those of the basic module and the authentication module on the substrate, and which is turned on for a fixed period by storage of charges and permits reading of the authentication module only during an on-period of the aging devices.

Abstract: A sensor node for intermittently sensing data in a short cycle includes a control unit for acquiring information by driving the sensor, a radio communication unit for transmitting the information acquired by the control unit and a battery for supplying the control unit. The control unit includes a clock supply unit (RTC) for supplying the control unit with clocks at a predetermined frequency. A sensor control unit starts the supply of power to the sensor when the measurement period has begun, maintains the power supply to the sensor even if the control unit has shifted to the standby state during the measurement period, and shuts down the power supply to the sensor when the measurement period has been completed. A measurement unit is also provided for acquiring information from the sensor every time the latter has shifted to the operational state.

Abstract: The invention relates to a power supply device and a communication system. The power supply device supplies power to a main device. The communication system is provided with the main device mounting the power supply device therein and an external device connected to the main device. A feature of the invention is to offer a power supply device and a communication system that are capable of being responsive to external signals for returning to a normal operation mode with minimum power consumption in a power-saving operation mode. In the power saving operation mode, a main power supply circuit (60) is turned off and only an auxiliary power supply circuit (50) is operated.

Abstract: One embodiment of the present invention provides a system that facilitates temporarily increasing the operating frequency of an electronic circuit, such as a computer system, beyond a maximum sustainable operating frequency. Upon receiving a request to operate at a higher frequency, the system determines the thermal energy level of a cooling system for the circuit. If the thermal energy level is below a threshold level for the thermal capacity of the cooling system, the system increases the operating frequency of the circuit to a frequency that is greater than the maximum sustainable operating frequency for a period of limited duration. This period of limited duration is short enough to ensure that a temperature increase, caused by increasing the operating frequency, does not raise the operating temperature of the circuit above a maximum operating temperature.

Abstract: Methods and apparatus for re-acquiring a WiMAX network after a relatively long power saving mode (e.g., sleep or idle mode) using a “pre-wakeup” scheme are provided. According to this pre-wakeup scheme, a mobile station (MS) may power up receiving circuitry to search for the current channel or, if unsuccessful, a neighbor channel. After a successful network search during sleep mode, the MS may return to sleep for the remainder of the sleep window until the circuitry is powered up a second time to wakeup and then listen for an expected message. By pre-waking up and searching before waking up for the expected message, the MS may counteract the effects of the potential error in the local oscillator frequency accumulated during the long sleep mode. In this manner, the message miss rate may be reduced, thereby saving power and extending the time in which the MS may operate between battery rechargings.

Abstract: In standby mode, memory contents are saved to a hard disk. After AC power has been removed by disconnecting the AC plug, when the AC power is restored the data saved on the hard disk is automatically restored into memory to set the power-saving mode back to the standby mode. When the power is turned on next, quick resumption from standby mode can be accomplished.

Abstract: A method and device for adjusting communications power are used for detecting a communications condition between a connection port and a connection target, and a communications-supporting power of the connection port that includes at least one of a transmitting power and a receiving power is adjusted according to a detected communications condition. Therefore, accuracy of data transmission and reception is ensured, and power used for data transmission and reception is reduced.

Abstract: An electronic apparatus with a power saving function is provided. The electronic apparatus includes: one or more power managing subunits; a charge detecting module configured for detecting the remaining charge of the electronic apparatus; a charge range determining module configured for determining the charge range of the remaining charge of the electronic apparatus according to a power saving table; a managing module configured for determining whether the power managing subunit(s) should be in a statues of being enabled according to the power saving table and the determined charge range; and transmitting a control instruction to enable the power managing subunit(s) if the power managing subunit(s) should be enabled, and thus to keep the electronic apparatus in a power conserving state. A method for saving power of an electronic apparatus is provided.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract: In a communicating system including a base node, at least one adjacent node, and a start node transmitting data requested by the base node via the adjacent node or to the base node, data requested to the start node is transmitted by measuring a power required for data transmission between the nodes forming the communication system, selecting a path one by one depending on a minimum power consumption required for the data transmission from the base node to the start node using the measured power, and transmitting the requested data using the selected path.

Abstract: A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

Abstract: An information handling system is disclosed and can include at least one memory and at least two processor cores coupled thereto. Further, the information handling system can include a controller coupled to the at least two processor cores and the at least one memory. The controller can monitor the temperature within each processor core. Based on the temperature the controller can selectively steer one or more program threads away from an overheating processor core.

Abstract: A mobile computing device that dynamically and automatically manages all network adapters on the device to obtain the best and most effective balance of network connectivity and power consumption without requiring operator or user application intervention. Performance is increased by lowering power consumption (longer battery life) and decreasing transaction latencies, providing a device that has flexibility and ease of use. According to one aspect is a system that includes a data analysis component that monitors parameters associated with a device and a mobility policy manager component that provides balance of network connectivity and power consumption based at least in part upon the monitored stimuli.

Abstract: According to one embodiment of the invention, an activity detector comprises a resource partitioned into a plurality of chunks, a power controller and an activity detection unit. In communication with the activity detector and the resource, the power controller, based on measured activity by the activity detector, activates an additional chunk of the plurality of chunks and assigned the additional chunk to a specified agent or deactivates at least one chunk of the plurality of chunks.

Abstract: A printer has a controller configured to give an instruction to a LAN controller, the instruction specifying which one of communication speeds the LAN controller should communicate at. When it is determined that the mode of the printer is changed from a power mode in which power is supplied to the controller to a power mode in which power is not supplied to the controller, the controller instructs the LAN controller to reduce the communication speed. After the instruction to reduce the communication speed is given, a power supply unit cuts off power supply to the controller.

Abstract: A dynamic clock frequency module for a system-on-chip (SOC) including modules that communicate over a system bus includes a request evaluation module that receives requests to utilize the system bus from the modules. A frequency assignment module calculates a clock frequency value for the system bus based on the requests received by the request evaluation module. The request evaluation module includes a summing module that generates a sum of requests between the modules. A pulse stretch module increases a period of time that at least one of the requests is asserted. A low pass filter prevents changes to the clock frequency value when the sum at least one of increases and decreases for less than a predetermined period. A slew rate control module adjusts at least one of a rate of increase and a rate of decrease in the clock frequency value.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: An information processing apparatus includes a cooling fan, a temperature acquiring unit, and a control unit configured to accelerate the cooling fan in an n-stage and to decelerate it in an m-stage more than the n-stage based on temperature acquired by the temperature acquiring unit.

Abstract: An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry is responsive to a low power request signal received by the interrupt controller to communicate interrupt select information to the interrupt request monitoring circuitry prior to the first domain being switched to a low power mode, the interrupt select information identifying interrupt requests which indicate exit from the low power mode. The interrupt request monitoring circuitry comprises a select information store configured to store the select information communicated to the interrupt request monitoring circuitry by the interrupt control circuitry.

Abstract: A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. When the motherboard powers up, the clock selector sends the peripheral device an external clock signal from the motherboard.

Abstract: An information processing apparatus including a first data processor processing data sent from an external device, which can switch a power consumption mode thereof; a switcher configured to switch the mode of the first data processing device from the standard power mode to a power saving mode or vice versa; and a second data processor processing the data sent from the external device when the first data processor is in the power saving mode. The second data processor includes a first judging device making a judgment whether the data are to be processed by the first or second data processor depending on the data; and a connection establishing device establishing communication connection with the external device when the first judging device cannot make the judgment from the data.

Abstract: A server system includes a control device and plurality of server devices. The control device calculates an actual power consumption of the server system and notifies the actual power consumption to the server devices. Each server device compares the actual power consumption with a threshold value, and restricts power consumption of the server device based on a power-saving policy for the server device that represents a lower limit of power usable by the server device when the actual power consumption is greater than or equal to the threshold value.

Abstract: A physical layer for an inline power device of a network power system. The network power system includes inline power devices such as power source equipment and a plurality of powered devices and further includes a plurality of corresponding transmission media. The plurality of transmission media are connected to the corresponding power source equipment and powered devices through a power interface at each end of the transmission media. The multiple power interfaces of the power source equipment are often referred to as ports. For each port of the power source equipment and the plurality of powered devices, there exists a physical layer. The physical layer includes an inline power control signal source. The inline power control signal designates when to apply power to a port when there is no power applied to the port and when to remove power from the port when there is power applied to the port.

Abstract: A monitoring method and apparatus applied to a computer system having a computer case, a controller and a register for changing the power state of the computer system according to the assembling state of the computer case is disclosed. The method comprises steps of detecting whether the computer case of the computer system is disassembled, generating a trigger signal to the controller when the computer case of the computer system is disassembled, generating a power management signal in response to the trigger signal for changing a system power state indicator of the register, and polling the system power state indicator and driving the computer system into a hibernation mode according to the change of the system power state indicator.

Abstract: An information processing apparatus including at least one first processing unit that manages a resource and at least one second processing unit that accesses the resource, wherein the second processing unit stores a table in which an identifier identifying the resource is associated with the resource, and when accessing the resource, refers to the table and requests the first processing unit to allocate the identifier associated with the resource to the resource.

Abstract: A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

Abstract: A system is coupled to a network by a network interface. In a power savings mode the speed setting of the network interface is reduced to accommodate increased system latency.

Abstract: Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.

Abstract: Methods and associated apparatus to reduce electrical power consumption in an information channel may include identifying times at which to restore power to elements in the information channel, and restoring power to the elements at the identified times. Times for each element are identified based on a recovery time for that element to reach a sufficiently stable operating point before a transition to an active mode of operation. By maximizing the length of time individual elements may stay in the reduced power mode, power savings may be maximized without negatively affecting information channel performance.

Abstract: A computer system is presented which provides a trusted platform by which operations can be performed with an increased level trust and confidence. The basis of trust for the computer system is established by an encryption coprocessor and by code which interfaces with the encryption coprocessor and establishes root of trust metrics for the platform. The encryption coprocessor is built such that certain critical operations are allowed only if physical presence of an operator has been detected. Physical presence is determined by inference based upon the status of registers in the core chipset.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: A system and method for providing power control in a power management integrated circuit. A power management integrated circuit may comprise a communication interface module that receives power supply information from at least one electrical device external to the power management integrated circuit. The power supply information may, for example, comprise information related to a first electrical power. The power management integrated circuit may also comprise a power regulator module that determines a regulated power signal based, at least in part, on a portion of the power supply information. The regulated power signal may correspond to the first electrical power. For example, the regulated power signal may comprise the first electrical power or cause another circuit to output the first electrical power. The power management integrated circuit may then output the regulated power signal to at least one electrical device external to the power management integrated circuit.

Abstract: A control device includes a main control unit that serves as a main component for device control and to which power is supplied from a first power unit; a power control unit that controls the first power unit and to which power is supplied from a second power unit; a memory control unit that accesses a memory that stores therein a computer program and data and to which power is supplied from the second power unit; and a network control unit that receives packets through a network and transfers the packets to the memory through the memory control unit and to which power is supplied from the second power unit.

Abstract: A component of a computing device such as a processor is operated based on a clock signal oscillating at a frequency. Power management for the computing device is performed by adjusting the frequency of the clock signal applied to the component when warranted and also by idling the component when the component experiences a period of inactivity longer than an idle detection metric scaled according to the adjusted frequency.

Abstract: Combinations of clock frequencies, voltages, and currents at which a processor operates normally are determined. These combinations are stored to a component on which the processor is installed. Voltage identifiers are stored to a computer system in which the component is installed. The voltage identifiers are associated with combinations of the voltages and currents. A type of the computer system is also stored to the component. A first clock frequency at which the processor operates is determined that is assigned to the type of the computer system. A first voltage and a first current are selected that are assigned to the first clock frequency. A first voltage identifier is found that is assigned to the combination of the first voltage and first current, and the first voltage identifier is sent to a voltage regulator, which supplies voltage to the processor.

Abstract: An image processing apparatus comprising a data processing unit; a first interface unit, having a plurality of logical channels, adapted to connect with an external processing apparatus; a second interface unit, compliant with a same communication standard as the first interface unit and having a plurality of logical channels with a different configuration from the first interface unit, adapted to connect with the data processing unit; a control unit adapted to control overall operation of the image processing apparatus and data transfer between the first interface unit and the second interface unit; a power control unit adapted to control turning ON/OFF power supply to the data processing unit; and a signal line connected to the data processing unit, with which the power control unit controls the data processing unit to turn on when the data processing unit is turned off and is not provided with an automatic power resume feature.

Abstract: In a detection element for the current which flows from a power source to a disk apparatus internal circuit, a plurality of resistors are incorporated such that the detection resistance for consumption current can be selected. Based on apparatus identification information from an apparatus identification unit 31 such as a current identification signal outputting circuit or an apparatus identification structure provided in a disk apparatus unit, the detection element switching circuit switches the detection resistance value of the detection element. A voltage detection circuit detects the potential difference between both terminals of the detection element. When a current control circuit detects an excessive current based on the potential difference, the current control circuit turns off a transistor (FET).

Abstract: A first network device comprises first and second transformers that communicate with a second network device. A switch selectively connects power to the first and second transformers. A physical layer device communicates with the first and second transformers and includes a signal generator, a detector, and a controller that communicates with the switch, the signal generator and the detector. The signal generator generates a test signal comprising n sub-pulses, where n is an integer greater than 2. When the detector detects j pulses that are greater than a predetermined threshold, 1?j<n, the controller supplies power to the second network device, where j is an integer.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by performing simulation using one or more training programs to obtain average power consumption during one or more windows of operation, then using the results to select parameters and coefficients for a processor characterization equation that can estimate power consumption while minimizing error.

Abstract: A method for providing power conservation in a processor in which, depending on the respective embodiment, a relative amount of idle time, activity time, or idle time and activity time associated with the processor are measured or detected, results of the measuring being used by the processor for controlling a clock speed. Yet other embodiments disclose, depending upon the respective embodiment, a relative amount of Input/Output (I/O), relative importance of Input/Output (I/O), and/or relative amount of time between Input/Output (I/O), associated with the processor are measured, results of the measuring being used by the processor to control power dissipation associated with the processor.

Abstract: HDD boxes 831 to 83n are each incorporated with a secondary battery box 87, a non-isolated DC/DC converter 89, and an HDD 91. Logical circuit boards 851 to 85n are each incorporated with the secondary battery box 87, fast-transient-response-type non-isolated DC/DC converters 931 to 933, and a plurality of loads 951 to 953. Every secondary battery box 87 is provided with a charge/discharge circuit 97, and a plurality of in-line secondary batteries 99. In the HDD box, the output voltage from the secondary battery box 87 goes to an HDD 91 via the DC/DC converter 89. In the logical circuit board, the output voltage from the secondary battery box 87 goes to the corresponding loads 951 to 953 via the DC/DC converters 931 to 933. With such a structure, in a disk array apparatus, realized are higher energy efficiency and less space occupation through reducing power loss and optimizing power capacity setting for a backup power.

Abstract: A conditional access device is provided. The conditional access device typically includes conditional access decryption, interface, timing and control logic. The conditional access decryption logic decrypts an incoming signal for use in a consumer electronics device in accordance with previously received entitlement management messages. The interface logic receives a control signal including an entitlement management message window from a headend control system through a receiver in the consumer electronics device. The timing logic asserts an awake signal responsive to the entitlement management message window becoming active. The control logic sends a request to the consumer electronic device to activate a receiver coupled to the headend control system in expectation of receiving an entitlement management message via the control signal in response to assertion of the awake signal. The control logic also communicates the entitlement management message to the conditional access decryption logic.

Abstract: A network interface card in a networked client computer includes a network interface circuit that decodes and then compares incoming network packet addresses to known address bit patterns, the decoding and comparing circuitry being powered at all times. Receipt and recognition of certain addresses means the client computer must be powered-on, even if manually switched OFF. When such a server-transmitted address is recognized, a power-on signal is issued to a power control unit that causes full operating power to be coupled to the client computer. In this fashion, a server can broadcast power-on signals to a plurality of networked client computers or workstations.