Counting, Scheduling, Or Event Timing Patents (Class 713/502)
-
Patent number: 7657772Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.Type: GrantFiled: February 13, 2003Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Michael Stephen Floyd, Paul David Muench, Lawrence Joseph Powell
-
Patent number: 7653828Abstract: Embodiments include a timeout event management system that registers timeout events and checks for and corrects inaccuracies in timing caused by hibernation or system time changes. The timeout event management system may trigger an event after an intended delay time or at an intended expiration time. A handler program may be called in response to the triggered timeout. In an additional embodiment, the timeout system may track timeout events in a priority queue data structure.Type: GrantFiled: May 28, 2004Date of Patent: January 26, 2010Assignee: SAP AGInventors: Dimitar P. Kostadinov, Petio G. Petev, Hristo S. Iliev, Krasimir P. Semerdzhiev, Georgi N. Stanev, Jasen O. Minov
-
Publication number: 20100017640Abstract: Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of predefined time intervals. Furthermore, a set of pointers may be used to reference the set of arrays of counters. An index is maintained to provide time-based management of the arrays of counters. The index includes a timestamp and the set of pointers. Each pointer logically points to a distinct one of the set of arrays.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventor: John Kenneth Gallant
-
Patent number: 7650523Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.Type: GrantFiled: August 29, 2006Date of Patent: January 19, 2010Assignee: Infineon Technologies AGInventors: Jörn Angel, Georg Stäbner
-
Publication number: 20100011237Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Inventors: Lance S. P. Brooks, Darrell A. Teegarden
-
Patent number: 7646230Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.Type: GrantFiled: September 5, 2008Date of Patent: January 12, 2010Assignee: Siemens Industry, Inc.Inventor: Steven Perry Parfitt
-
Patent number: 7647521Abstract: A method, apparatus and computer instructions for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.Type: GrantFiled: December 11, 2006Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, David Kevin Siegwart
-
Patent number: 7640124Abstract: In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.Type: GrantFiled: March 14, 2007Date of Patent: December 29, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Hideaki Konishi, Ryuji Shimizu, Masayasu Hojo, Haruhiko Abe, Satoshi Masuda, Naofumi Kobayashi
-
Publication number: 20090319816Abstract: An information processing apparatus includes a versatile Operating System (OS) that performs a time measurement process in response to a request from an application, a storage unit that stores a process load of the versatile OS and a delay time of the time measurement process in combination, a detecting unit that detects a process load of the versatile OS when the application requests the time measurement process, an acquiring unit that acquires a delay time that corresponds to the process load, which is detected by the detecting unit, as an expected delay time from the storage unit, and a requesting unit that requests the versatile OS to measure a requested measurement time that is obtained by subtracting the expected delay time, which is acquired by the acquiring unit, from a measurement time that is requested by the application.Type: ApplicationFiled: August 26, 2009Publication date: December 24, 2009Applicant: FUJITSU LIMITEDInventor: Susumu Watanabe
-
Publication number: 20090307519Abstract: The disclosed system and methods include a power saving scheduler that maintains timed events in an event table. Each timed event has an associated tolerance period within which the event should begin execution following a trigger, and a timestamp indicating a scheduled execution time for the event. When a device is in a low-power sleep mode, a trigger may wake up the device to a wake state. The power scheduler then accesses the event table of upcoming timed events, and reorders the event table from the event having the shortest tolerance period to the event having the longest tolerance period. Each event for which the timestamp is within the tolerance period as measured from the trigger time is executed. After a plurality of such events are executed, the device may return to the sleep mode.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Inventor: Edward Craig Hyatt
-
Publication number: 20090300402Abstract: An integrated circuit includes a processor and a circuit. The processor is configured to execute software. The software includes a plurality of software events. The circuit is configured to output a pulse on a single pin or pad of the integrated circuit in response to executing each software event. A pulse width of each pulse identifies a software event.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Applicant: Infineon Technologies AGInventor: Jeyur Patel
-
Patent number: 7627772Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.Type: GrantFiled: June 5, 2006Date of Patent: December 1, 2009Assignee: Micron Technology, Inc.Inventor: Dean Nobunaga
-
Publication number: 20090292939Abstract: According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program.Type: ApplicationFiled: May 22, 2009Publication date: November 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masashi Yasuzato
-
Publication number: 20090276653Abstract: A presence server of an apparatus in one example is configured to receive at least one event message from a network entity in continuous time. The presence server is configured to determine at discrete time intervals if an update message should be sent for the network entity. The discrete time intervals comprise instances of an epoch. The presence server is configured to determine if the update message should be sent upon an epoch boundary. The presence server is configured to dynamically determine a duration of the epoch.Type: ApplicationFiled: May 2, 2008Publication date: November 5, 2009Inventors: Ramesh V. Pattabhiraman, Kumar V. Vemuri
-
Patent number: 7610175Abstract: A signal monitor device that detects a signal propagating on a signal line and that generates a timestamp when the signal is detected. The timestamp may be used in a variety of applications including measuring the propagation delays on signal lines and determining the timing in a system.Type: GrantFiled: February 6, 2006Date of Patent: October 27, 2009Assignee: Agilent Technologies, Inc.Inventor: John C. Eidson
-
Patent number: 7610416Abstract: Systems and methods for controlling the rise and fall times of USB signals for USB devices and peripherals are provided. The rise and fall times of USB peripherals can be controlled, or changed, in order to match the electrical characteristics of the USB peripheral to a USB host. By sweeping through a range of rise and fall times, and testing the reliability of USB output, optimal rise and fall times for the characteristics of a USB peripheral can quickly be determined. In one embodiment, the controllability of the rise and fall times is provided in firmware that changes at least one characteristic of the USB peripheral that affects the amount of current flowing during USB signaling.Type: GrantFiled: April 13, 2005Date of Patent: October 27, 2009Assignee: Microsoft CorporationInventors: Richard S. Lum, Wei Guo
-
Publication number: 20090265573Abstract: The present invention provides a data transmission/reception circuit which stops the operation of a packet transmission/reception circuit during a data transfer-free time thereby to realize power savings. The data transmission/reception circuit includes a packet transmission/reception circuit for performing transmission/reception of data to and from an external USB host via a USB bus at one data transfer intervals per predetermined frame, a clock generator for generating a clock signal and supplying the clock signal to the packet transmission/reception circuit, and a clock gating signal generating circuit for stopping the supply of the clock signal to the packet transmission/reception circuit by the clock generator during a frame free of the transmission/reception of the data by the packet transmission/reception circuit.Type: ApplicationFiled: March 25, 2009Publication date: October 22, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Hirohisa Tanabe
-
Publication number: 20090259877Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicant: DELL PRODUCTS, LPInventors: Nikolai Vyssotski, Allen C. Wynn, John Hentosh
-
Patent number: 7602744Abstract: The invention relates to a detection of a simultaneous occurrence of an event of a predetermined kind at a plurality of electronic devices. At least two devices detect the event and record at their end the time elapsing after this detection. Then, a communication channel is established between the devices. Once the communication channel has been established, an indication of the recorded elapsed times can be exchanged. At least one of the devices compares a recorded elapsed time with an indicated elapsed time received from another device. If both elapsed times are similar to each other, it can be assumed that the event occurred simultaneously at both devices. The invention relates equally to corresponding devices, to a corresponding data transfer system and to corresponding software program products.Type: GrantFiled: September 9, 2004Date of Patent: October 13, 2009Assignee: Nokia CorporationInventors: Terho Kaikuranta, Jakke Mäkelä
-
Patent number: 7600141Abstract: A data processing system is provided having a processor 46 which generates control signals for controlling further circuits, such as a clock generator 4 and voltage controller 6, to operate so as to support a desired performance level of the processor. Whilst changing between performance levels, the further circuits are capable of supporting intermediate levels of operation and the processor exploits these by operating at those intermediate levels pending the final target level being reached.Type: GrantFiled: November 19, 2003Date of Patent: October 6, 2009Assignee: ARM LimitedInventor: David Walter Flynn
-
Patent number: 7599459Abstract: A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew circuit. The corresponding data sequence is written into each elastic buffer. A predetermined number of consecutive timing control symbols are inserted into the data sequences as markers for data blocks to be read from the data sequences at the same cycle. The elastic buffers adjust numbers of the timing control symbols included in the written data sequences, respectively. The data sequences, in each of which the number of the timing control symbols has been adjusted, are read from the elastic buffers in synchronization with a reading clock. The data sequences are written into the deskew circuit. The deskew circuit adjusts the number of the timing control symbols included in each data sequence so as to be equal to the predetermined number.Type: GrantFiled: May 17, 2006Date of Patent: October 6, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Ken Okuyama
-
Publication number: 20090249108Abstract: Computers and other electronic devices typically include a timing operation such as a clock in an operating system. It is anticipated that hackers may tamper with this clock. This tampering might be especially advantage in the context of systems which provide for rental of audio and video content, such as movies. Tampering with the system clock on the playing device would allow an extension of the rental period to the detriment of the provider of the rental content. Hence the present method is directed to detecting clock modifications both in terms of time shifting and clock rate tampering. This detection is done using digital signal processing.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: Pierre Betouin, Mathieu Ciet, Augustin J. Farrugia
-
Publication number: 20090249109Abstract: A storage apparatus stores data in a storage area, and includes a judgment unit and an internal information management unit. The judgment unit judges whether a preconfigured given condition is satisfied. The internal information management unit associates the satisfied preconfigured condition with internal information relating to an operation or a status of the storage apparatus and manages the condition and the internal information when the judgment unit judges that the given condition is satisfied.Type: ApplicationFiled: March 11, 2009Publication date: October 1, 2009Applicant: FUJITSU LIMITEDInventor: Shunsuke Aoki
-
Patent number: 7596669Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.Type: GrantFiled: May 17, 2005Date of Patent: September 29, 2009Assignee: Broadcom CorporationInventor: Joseph Herbst
-
Publication number: 20090240972Abstract: Time-related properties may be modeled independent of a base object. Rather than storing time properties with the object, they may be stored independently. A given object may be stored once, even if it has a recurrent time property. The description of a “meeting,” for example, may be stored once. Each occurrence of that object over time may be stored in a “timeslot” (object <foo> occurs at time ‘t’ on day ‘d’). If it is a recurring property, recurrence information may be stored independently. “Exception” information may be stored independently as well.Type: ApplicationFiled: February 5, 2009Publication date: September 24, 2009Applicant: Microsoft CorporationInventors: Christopher Michael Simison, Remi Alain Lemarchand, Robert C. Combs
-
Patent number: 7594146Abstract: A time correcting apparatus includes a data input section which inputs all event trace data generated for each event executed on computing devices and outputs the event trace data in order of occurrence time of the event data. An inter-machine communication-time-table generating section extracts transmission and reception events from the output event trace data and generates a communication time table indicating communication times between computing devices based on the differences in occurrence time between the corresponding transmission and reception events. A time-offset deriving section generates a time offset table indicating a time offset value for each computing device based on the communication time table. A time correcting section corrects the event occurrence times of all event data based on the time offset table. A data integrating section inputs all event data whose occurrence times have been corrected and outputs the event data in order of corrected occurrence time.Type: GrantFiled: February 23, 2005Date of Patent: September 22, 2009Assignee: NEC CorporationInventors: Takashi Horikawa, Toshiaki Yamashita
-
Patent number: 7590880Abstract: The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for providing a delayed signal of the test signal, and circuitry for comparing the logical state of the test signal and the delayed signal and issuing an attack indication whenever the signals are different.Type: GrantFiled: September 13, 2004Date of Patent: September 15, 2009Assignee: National Semiconductor CorporationInventor: Ziv Hershman
-
Patent number: 7590871Abstract: An operation mode control program is a program for carrying out an operation mode changeover control. A user interface section sets time zone corresponding to each operation mode. A time acquire section periodically acquires system time from an internal clock section of an operating system, and transfers the system time to an operation mode changeover section. The operation mode changeover section carries out the operation mode changeover control in accordance with time zone set by the user interface section while receiving the system time from the time acquire section.Type: GrantFiled: November 13, 2003Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Toshikazu Morisawa
-
Publication number: 20090228735Abstract: In an information processing apparatus and elapsed time measuring method of the present invention, a microcomputer for power supply control measures an elapsed time when the product is in an operating condition, a time when the product is powered off is read from an RTC in a system LSI and written to a storage unit in a BIOS, a time when the product is next powered on is read from the RTC, and a difference between the two times is calculated in order to obtain an elapsed time for when the product is in a non-operating condition. An elapsed time of the product is calculated by adding together two types of elapsed times in the BIOS. This structure enables providing an information processing apparatus and elapsed time measuring method that can accurately measure the elapsed time of the product without being influenced by a user operation.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: PANASONIC CORPORATIONInventors: Seiji IKEDA, Yoichi AYABE
-
Publication number: 20090222147Abstract: A temperature controlling apparatus determines a fan rotation speed from a surrounding noise and a fan noise, measures a temperature of a large scale integration (LSI) device or the like that is a controlled object, determines, in a cooling capacity range of the determined fan rotation speed, an operating clock frequency that falls within an allowable temperature range, and controls the LSI to be connected.Type: ApplicationFiled: March 2, 2009Publication date: September 3, 2009Applicant: FUJITSU LIMITEDInventors: Yoshiyasu Nakashima, Satoshi Kazama
-
Publication number: 20090210740Abstract: A system, apparatus, and method are provided which allows for reducing power consumption in dynamic voltage and frequency scaled processors while maintaining performance within specified limits. The method includes determining the off-chip stall cycle in a processor for a specified interval in order to characterize a frequency independent application workload in the processor. This current application workload is then used to predict the application workload in the next interval which is in turn used, in conjunction with a specified performance bound, to compute and schedule a desired frequency and voltage to minimize energy consumption within the performance bound. The apparatus combines the aforementioned method within a larger-scale context that reduces the energy consumption of any given computing system that exports a dynamic voltage and frequency scaling interface. The combination of the apparatus and method form the overall system.Type: ApplicationFiled: February 17, 2009Publication date: August 20, 2009Inventors: Song HUANG, Wu-chun Feng
-
Patent number: 7577254Abstract: A method (300) of performing photon detector autocalibration in quantum key distribution (QKD) system (200) is disclosed. The method (300) includes a first act (302) of performing a detector gate scan to establish the optimum arrival time of a detector gate pulse (S3) that corresponds with a maximum number of photon counts (NMAX) from a single-photon detector (216) in the QKD system (200). Once the optimal detector gate pulse arrival time is determined, then in an act (306), the detector gate scan is terminated and in an act (308) a detector gate dither process is initiated. The detector gate dither act (308) involves varying the arrival time (T) of the detector gate pulse (S3) around the optimal value of the arrival time established during the detector gate scan process. The detector gate dither provides minor adjustments to the arrival time to ensure that the detector (216) produces maximum number of photon counts (NMAX).Type: GrantFiled: January 29, 2004Date of Patent: August 18, 2009Assignee: MagiQ Technologies, Inc.Inventors: Harry Vig, Jonathan Young, Paul A. Jankovich
-
Publication number: 20090199037Abstract: A power saving sleep timer has a first clock and a second clock having greater frequency and temporal stability than the first clock. The second clock has an associated second clock period value which is accumulated once for each said second clock interval during one or more first clock periods, thereby forming a calibrated period value. During an operational interval, the calibrated period value is accumulated once per first clock interval until the accumulated value is equal or greater than a sleep time value, after which a power-up output is asserted.Type: ApplicationFiled: February 1, 2008Publication date: August 6, 2009Inventors: Narasimhan Venkatesh, Subba Reddy Kallam, Alukuru Trikutam Sivaram
-
Patent number: 7570669Abstract: A system and method for determining a common time base among nodes in a network by iteratively propagating timing constraints among the nodes, and determining a time-shift to apply to the time base of each node that conforms to these constraints. “Trace” files record the time of transmission or reception of packets at each node, based on the time base at the node. A fundamental constraint in a common time-based system is that the time of reception of a packet at a destination node cannot be prior to the time of transmission of the packet from a source node. A further constraint in a common time-based system is that the time of reacting to an event cannot be prior to the time of the event.Type: GrantFiled: August 9, 2004Date of Patent: August 4, 2009Assignee: OPNET Technologies, Inc.Inventors: Patrick J. Malloy, Antoine D. Dunn
-
Patent number: 7571341Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.Type: GrantFiled: September 22, 2006Date of Patent: August 4, 2009Assignee: Intel CorporationInventors: Kiran Padwekar, Arvind Mandhani, Durgesh Srivastava
-
Patent number: 7571338Abstract: Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.Type: GrantFiled: May 18, 2005Date of Patent: August 4, 2009Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Jacob Österling, Torbjörn Aarflot
-
Patent number: 7571266Abstract: A computerized system is described (i) which includes an interface connected with a peripheral device and (ii) which is incapable of dynamically extending bus cycle timing if required by the peripheral device to carry out a particular current operation. This computerized system includes a given peripheral device which, during normal operation of the device, can require an extension of bus cycle timing to carry out the current operation. This device generates a specific signal when the extension is required. The device is connected with the interface of the computerized system and the system is configured to cause the system (i) to recognize the specific signal and (ii) to instruct the peripheral device to retry the current operation responsive to the specific signal. In a particular embodiment, the peripheral device is a disk drive having an ATA interface and the specific signal generated by the disk drive is an IORDY signal.Type: GrantFiled: February 6, 2006Date of Patent: August 4, 2009Inventor: Lance R. Carlson
-
Patent number: 7568118Abstract: In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2005Date of Patent: July 28, 2009Assignee: Intel CorporationInventors: Warren R. Anderson, Maurice B. Steinman, Richard M. Watson, Horst W. Wagner, Christopher C. Gianos, Suresh Balasubramanian, Tim Frodsham
-
Patent number: 7562105Abstract: Methods, apparatus, and articles of manufacture for generating a delay time using a counter are disclosed. In particular, the methods, apparatus, and articles of manufacture determine a number of loops value associated with the delay time and at least one characteristic value associated with a counter. A remaining count value is then determined based on the number of loops value. The delay time is generated with the counter based on the number of loops value and the remaining count value.Type: GrantFiled: November 26, 2003Date of Patent: July 14, 2009Assignee: Intel CorporationInventors: Yan Liu, Lechong Chen
-
Patent number: 7561598Abstract: A system and method are provided which add, via an add-on module, synchronization functionality to an instrument that does not otherwise support such synchronization functionality. Various synchronization techniques may be supported by the synchronization module. For instance, in certain embodiments the synchronization module supports message-based synchronization techniques and/or time-based synchronization techniques. Accordingly, in certain embodiments, the add-on module supports synchronization with another device (e.g., another instrument or another add-on module coupled to an instrument) via synchronized local clocks (e.g., IEEE 1588) and messaging over a communication network. In certain embodiments, the add-on module additionally or alternatively supports the use of “time bombs” to trigger scheduled actions on the instrument with which the synchronization module is interfaced.Type: GrantFiled: September 13, 2004Date of Patent: July 14, 2009Assignee: Agilent Technologies, Inc.Inventors: John B. Stratton, Leon K. Werenka, Daniel L. Pleasant, Gopalakrishnan Kailasam, Robert T. Cutler
-
Publication number: 20090168997Abstract: A method for detecting a communication relay attack involves the steps of counting a number of clock cycles occurring in a clock signal between transmission of two predetermined elements of data with a data transmission device, counting a number of clock cycles occurring in the clock signal between receipt of the two predefined elements of data and comparing the number of clock cycles counted by the data transmission device with the number of clock cycles counted by the data receiving device.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Inventor: Simon Blythe
-
Patent number: 7552446Abstract: Complex software systems often require time-based processing, such as delayed or periodic timer event handling. A timer service provides an Application Programming Interface (API) for managing timers, and therefore provides a developer abstraction for representing time-based processing. In operation, the timer service infrastructure employs a plurality of timer events, each having a corresponding timer handler, in which each of the timer events is associated with a generic timer reference, employed by a timer interface. The generic reference, therefore, may refer to any of the plurality of timers. The timer service may disable, or passivate modules including subscribers having timer handlers without disrupting timer continuity and invocation. Upon timer expiration, the timer service enables modules having subscribers to the timer. The timer service therefore seamlessly enables inactive modules upon timer expiration.Type: GrantFiled: December 31, 2003Date of Patent: June 23, 2009Assignee: EMC CorporationInventors: Stanislav Sosnovsky, Ruben Michel, Ilya Liubovich
-
Patent number: 7552226Abstract: Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.Type: GrantFiled: April 6, 2005Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Andreas Ch. Doering, Silvio Dragone
-
Patent number: 7546481Abstract: A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.Type: GrantFiled: March 7, 2006Date of Patent: June 9, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Hiroyuki Hanamori
-
Patent number: 7546480Abstract: In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. The invention is directed to a system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries. The invention is also directed to a method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries.Type: GrantFiled: December 6, 2007Date of Patent: June 9, 2009Assignee: Extreme Networks, Inc.Inventors: Erik R. Swenson, Sid Khattar
-
Patent number: 7543173Abstract: A method of generating a timestamp includes measuring a time period between two events, automatically determining a precision for an indication of the time period, and storing the timestamp. The precision for the indication of the time period is decreased as the time period increases. The timestamp includes an indication of the precision and the indication of the time period, wherein the indication of the time period in the timestamp is stored according to the automatically determined precision.Type: GrantFiled: August 2, 2005Date of Patent: June 2, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard Adkisson
-
Publication number: 20090138746Abstract: Pulse width modulation signals are generated by identifying an event table having a plurality of events, each event including a time to next event parameter. Each desired pulse width modulation signal is characterized by a first event designating a transition from a first state to a second state and a second event designating a transition from the second state back to the first state. An event pointer is set to select a current event and the event table is repeatedly cycled through by updating the output for at least each pulse width modulation signal associated with the current event having a designated state transition, detecting that a time period has lapsed corresponding to the time to next event parameter associated with the current event, incrementing the event pointer to point to a next event in the event table and conveying each pulse width modulation signal to a corresponding circuit.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Inventor: Daniel Richard Klemer
-
Patent number: 7539803Abstract: A bi-directional single-conductor interface is provided, comprising (1) a switching means for applying a voltage level to the interface that is outside a normal voltage operating range for the interface and for removing the applied voltage level at an end of a specified time duration; and (2) a timer initiated by detection of the applied voltage and arranged to include a timing interval following removal of the applied voltage. With the interface of the invention, data is caused to be transmitted via the interface in a first direction during the timing interval of the timer, and in an opposite direction during other times.Type: GrantFiled: June 13, 2003Date of Patent: May 26, 2009Assignee: Agere Systems Inc.Inventors: Jonathan H. Fischer, Walter G. Soto
-
Patent number: 7539890Abstract: A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every read of the monotonic time from the clock object. The clock object can also include an indication of a level of trust of the clock time.Type: GrantFiled: April 25, 2006Date of Patent: May 26, 2009Assignee: Seagate Technology LLCInventor: Robert H. Thibadeau
-
Patent number: RE41031Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.Type: GrantFiled: March 2, 2006Date of Patent: December 1, 2009Inventor: Jacques Majos