Counting, Scheduling, Or Event Timing Patents (Class 713/502)
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Publication number: 20120192004Abstract: A method disclosed herein provides for receiving information relating to an event that occurred while processing server request from a compiled code snippet inserted into a compiled computer program, calculating diagnostic information relating to execution of the server request based on the received information, and providing the diagnostic information. Alternatively, a computer-readable medium, storing a set of instructions, is provided for, the instructions, when executed by a processor perform a method including, while a server request is being executed, receiving information from a compiled code snippet, in inserted into a compiled computer program, the received information relating to a thread starting to process the server request.Type: ApplicationFiled: January 24, 2011Publication date: July 26, 2012Inventor: Piotr Findeisen
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Patent number: 8225128Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.Type: GrantFiled: February 27, 2008Date of Patent: July 17, 2012Assignees: Conemtech AB, Imsys ABInventors: Stefan Blixt, Christian Blixt
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Publication number: 20120166862Abstract: A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.Type: ApplicationFiled: March 5, 2012Publication date: June 28, 2012Applicant: ROUND ROCK RESEARCH, LLCInventor: Simon J. Lovett
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Patent number: 8208594Abstract: A method for the recovery of a clock signal from a data signal is provided where the edges of the signals are each represented as a chronologically-ordered sequence of timing points. In one procedural stage, a plurality of timing points of the data signal are processed in parallel as follows: resolving the timing points of the data signal by a nominal clock pulse; estimating the bit-period deviations for the adjusted timing points; and injecting the nominal clock pulse to the estimated bit-period deviations.Type: GrantFiled: August 20, 2008Date of Patent: June 26, 2012Assignee: Rohde & Schwarz GmbH & Co. KGInventors: Rubén Villarino-Villa, Markus Freidhof, Thomas Kuhwald
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Patent number: 8209451Abstract: An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.Type: GrantFiled: September 2, 2009Date of Patent: June 26, 2012Assignee: Wistron CorporationInventors: Wen-Tse Huang, Po-Hsu Chen
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Patent number: 8209534Abstract: For achieving the protection of copyright, by suppressing illegal copy production thereof, in particular, when transmitting contents with using a wired or wireless LAN, as well as, for preventing the transmission of contents from deviating from a range of a personal use thereof, a contents transmitter apparatus and a contents receiver apparatus make an authentication, mutually, before transmitting contents therebetween.Type: GrantFiled: October 7, 2010Date of Patent: June 26, 2012Assignee: Hitachi, Ltd.Inventors: Chiyo Ono, Hiroo Okamoto
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Patent number: 8209562Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.Type: GrantFiled: January 7, 2010Date of Patent: June 26, 2012Assignee: Mosaid Technologies IncorporatedInventors: Jody Defazio, Oswald Becca, Peter Nyasulu
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Patent number: 8209561Abstract: A real time clock for outputting data indicating a time of day includes: an event detection circuit for detecting that an event detection signal has been inputted from outside; a timing circuit for generating the time-of-day data according to a signal outputted from an oscillator circuit; a memory; and a control circuit for, if the event detection circuit detects input of the event detection signal, recording event data in the memory, the event data including additional data indicating an operating state of the real time clock and the time-of-day data generated by the timing circuit.Type: GrantFiled: July 17, 2008Date of Patent: June 26, 2012Assignee: Seiko Epson CorporationInventors: Toru Shirotori, Toshiya Usuda
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Patent number: 8195973Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.Type: GrantFiled: April 14, 2008Date of Patent: June 5, 2012Assignee: Dell Products, LPInventors: Nikolai Vyssotski, Allen C. Wynn, John Hentosh
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Patent number: 8189723Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.Type: GrantFiled: August 15, 2008Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
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Patent number: 8190944Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.Type: GrantFiled: December 11, 2009Date of Patent: May 29, 2012Assignee: ATI Technologies ULCInventors: Kevin D. Senohrabek, Natale Barbiero, Gordon F. Caruk
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Patent number: 8190941Abstract: The field control system includes: a field device; a field controller which is connected to a control network and which executes a computation processing for controlling the field device according to a given control cycle while executing a data communication between the field controller and the field device, the field controller including a communication unit configured to execute the data communication with the field device, and a control computation unit configured to execute the computation processing independently from the communication unit; and an operation monitor which is connected to the control network and which operates and monitors the field device, the operation monitor including a network clock which provides a common network time to the control network. The control computation unit and the communication unit execute the computation processing and the data communication in synchronism with each other in accordance with a timer clock based on the network time.Type: GrantFiled: February 4, 2010Date of Patent: May 29, 2012Assignee: Yokogawa Electric CorporationInventors: Satoshi Kitamura, Senji Watanabe, Hideharu Yajima, Masafumi Kisa, Kazushi Sakamoto, Hiroyuki Takizawa, Kuniharu Akabane, Yoshinori Kobayashi, Kenji Habaguchi, Kiyotaka Kozakai, Mitsuhiro Kurono, Hiroaki Nakajima
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Patent number: 8185774Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.Type: GrantFiled: May 14, 2009Date of Patent: May 22, 2012Assignee: Texas Instruments IncorporatedInventors: Horst Diewald, Joerg Schreiner
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Patent number: 8185772Abstract: Methods and apparatuses for determining a number of clock cycles during an execution of a command by a processor, determining a value associated with the number of clock cycles, storing an indicator indicative of the command, responsive to the value indicative of the execution time exceeding a threshold value.Type: GrantFiled: September 4, 2007Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Andreas Siggelkow, Thomas Zettler
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Patent number: 8185773Abstract: A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.Type: GrantFiled: December 31, 2008Date of Patent: May 22, 2012Assignees: STMicroelectronics S.r.l., Freescale Semiconductor, Inc.Inventors: Giuseppe D'Angelo, Antonio Anastasio, Leos Chalupa
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Patent number: 8176351Abstract: One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement signal (or input signal) acquired by the data acquisition device and also a sample clock signal. The counter unit may sample the measurement signal based on the selected operational mode and timing of the sample clock, and at a rate that is independent of the frequency of the measurement signal. Furthermore, the counter unit may sample the measurement signal based on a selected one of a plurality of timing modes associated with the sample clock signal. The counter units may take samples of the measurement signal to perform at least one of the following types of measurements: period, frequency, pulse-width, semi-period, time separation, or event counting.Type: GrantFiled: June 26, 2007Date of Patent: May 8, 2012Assignee: National Instruments CorporationInventors: Rafael Castro, Brian Keith Odom
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Patent number: 8166544Abstract: Host malware (or change) may be detected by (1) receiving baseline set of response time information for each of one or more transactions involving (A) the host and (B) at least one peer of the host, (2) determining or receiving a later set of response time information for each of the one or more transactions involving the host and the at least one peer of the host, and (3) determining whether or not host slowdown has occurred using the baseline set of response time information and the later set of response time information. The execution of a host malware (or change) protection policy may be controlled using at least the determination of whether or not host slowdown has occurred.Type: GrantFiled: February 26, 2008Date of Patent: April 24, 2012Assignee: Polytechnic Institute of New York UniversityInventors: Nasir Memon, Husrev Taha Sencar, Kulesh Shanmugasundaram
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Patent number: 8156366Abstract: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.Type: GrantFiled: November 15, 2007Date of Patent: April 10, 2012Assignee: MediaTek Inc.Inventors: Poul R. Jensen, Thorkild Leth Moller, legal representative, Morten Nielsen, Mogens Christiansen
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Patent number: 8150648Abstract: A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.Type: GrantFiled: December 26, 2008Date of Patent: April 3, 2012Assignee: Advantest CorporationInventors: Daisuke Watanabe, Toshiyuki Okayasu
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Patent number: 8149844Abstract: Determining a next time to communicate via a network with a source of updates is disclosed. In some embodiments, determining a next time to communicate via a network with a source of updates comprises receiving from a request source an update request, and scheduling a next time for the request source to check for updates. In some embodiments, determining a next time to communicate via a network with a source of updates comprises monitoring network communication activity, and in the event anomalous network communication activity is observed, reducing a time remaining until a next check for updates is performed.Type: GrantFiled: October 25, 2009Date of Patent: April 3, 2012Inventors: James A. Roskind, Aaron T. Emigh
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Patent number: 8151098Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.Type: GrantFiled: February 5, 2009Date of Patent: April 3, 2012Assignee: DENSO CORPORATIONInventors: Akimasa Niwa, Masahiro Kamiya, Hideaki Ishihara, Yoshinori Teshima
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Patent number: 8145934Abstract: A soft start sequencer is disclosed for starting a plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit for ramping a reference signal from a first value to a second value over a ramp time after a delay time. Each soft start circuit comprises a divider operable to divide the first clock by an integer N to generate a second clock, a first counter clocked by the first clock, the first counter operable to time the delay time, and a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.Type: GrantFiled: July 31, 2009Date of Patent: March 27, 2012Assignee: Western Digital Technologies, Inc.Inventors: Timothy A. Ferris, John R. Agness
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Patent number: 8145935Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.Type: GrantFiled: August 8, 2008Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Geun Park, Chul Joon Choi, Hyuk Jun Sung, Byung Yoon Kang
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Publication number: 20120072760Abstract: A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset.Type: ApplicationFiled: September 9, 2011Publication date: March 22, 2012Inventor: Jong-Lae Park
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Patent number: 8140883Abstract: Pipelined loop operations are efficiently scheduled. A preliminary as soon as possible (ASAP) schedule for a data operation in a pipelined loop is determined. A producer operation clock cycle associated with a producer operation in the pipelined loop is determined. The producer operation provides a data value for use by the data operation in a subsequent loop. A consumer operation clock cycle associated with a consumer operation in the pipelined loop is determined. The consumer operation obtains the data value from the data operation in a previous loop. The data operation is scheduled at the half-way point between the producer operation clock cycle and the consumer operation clock cycle.Type: GrantFiled: May 1, 2008Date of Patent: March 20, 2012Assignee: Altera CorporationInventor: David James Lau
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Patent number: 8140885Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.Type: GrantFiled: February 12, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Daniel Becker, Rafael Keggenhoff, Thuyen Le, Tobias Webel, Matthias Woehrle
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Patent number: 8140726Abstract: The present invention discloses a single wire transmission interface comprising: a signal detection circuit detecting level switchings of a transmission signal from a single wire, and generating an enable signal and a decoded signal corresponding to the transmission signal, the level switchings including first switchings from a first level to a second level and second switchings from the second level to the first level, wherein the enable signal starts according to one first switching of the transmission signal, and stops when no first switching occur in a predetermined period after one second switching of the transmission signal, and wherein rising edges (or falling edges) of the decoded signal correspond to the first switchings of the transmission signal; a counter, under enablement by the enable signal, counting a number of the rising edges (or the rising edges) of the decoded signal or the first switchings of the transmission signal, and generating a count; a single short pulse generator generating a shorType: GrantFiled: October 23, 2009Date of Patent: March 20, 2012Assignee: Richtek Technology Corporation, R.O.C.Inventors: Nien-Hui Kung, Kwan-Jen Chu
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Patent number: 8140882Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.Type: GrantFiled: February 18, 2009Date of Patent: March 20, 2012Assignee: Genesys Logic, Inc.Inventors: Wei-te Lee, Shin-te Yang, Yen-fah Chu
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Patent number: 8140884Abstract: Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of predefined time intervals. Furthermore, a set of pointers may be used to reference the set of arrays of counters. An index is maintained to provide time-based management of the arrays of counters. The index includes a timestamp and the set of pointers. Each pointer logically points to a distinct one of the set of arrays.Type: GrantFiled: July 18, 2008Date of Patent: March 20, 2012Assignee: Verisign, Inc.Inventor: John Kenneth Gallant
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Patent number: 8132040Abstract: Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includes receiving a first channel output signal and a second channel output signal from the first and second channels, respectively; detecting a phase difference between the first channel output signal and the second channel output signal; and controlling, based on the detected phase difference, a signal delay within at least the first channel or the second channel to reduce skew between the first channel output signal and the second channel output signal.Type: GrantFiled: October 25, 2007Date of Patent: March 6, 2012Assignee: Lattice Semiconductor CorporationInventor: Robert Bartel
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Patent number: 8132038Abstract: A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The system implements steps for obtaining samples of timing values of a computing device in the network, the values including a physical clock value maintained at that device and a TOD-offset value; computing an oscillator skew value from the samples; setting a fine steering rate value as equal to the opposite of the computed oscillator skew value; and, utilizing the fine steering rate value to adjust the physical clock value and correct for potential oscillator skew errors occurring in the oscillator crystal at the computing device.Type: GrantFiled: November 13, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Dennis J. Dahlen, David A. Elko, Ronald M. Smith, Sr., Lin Zhang
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Patent number: 8127168Abstract: A data processing device including an inter-VM notification management unit 1242, a resuming judgment unit 1244 and a scheduled interruption time acquisition unit 1245, such that, when it is necessary to notify a virtual machine in a power-saving state, the resuming judgment unit 1244 judges whether to cause the virtual machine to return from the power saving state, based on a time until an interruption acquired by the scheduled interruption time acquisition unit 1245. This structure prevents unnecessary transitions between states, and realizes the power saving for the apparatus.Type: GrantFiled: June 4, 2008Date of Patent: February 28, 2012Assignee: Panasonic CorporationInventors: Manabu Maeda, Tomoyuki Haga, Takayuki Ito, Hideki Matsushima, Yuichi Futa
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Patent number: 8122279Abstract: Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.Type: GrantFiled: April 21, 2008Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Hiroaki Yamaoka
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Patent number: 8117482Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.Type: GrantFiled: November 14, 2008Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventor: Yasuhiro Takata
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Patent number: 8117449Abstract: A method for detecting a communication relay attack involves the steps of counting a number of clock cycles occurring in a clock signal between transmission of two predetermined elements of data with a data transmission device, counting a number of clock cycles occurring in the clock signal between receipt of the two predefined elements of data and comparing the number of clock cycles counted by the data transmission device with the number of clock cycles counted by the data receiving device.Type: GrantFiled: December 27, 2007Date of Patent: February 14, 2012Assignee: MasterCard International, Inc.Inventor: Simon Blythe
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Patent number: 8117483Abstract: A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.Type: GrantFiled: May 13, 2009Date of Patent: February 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James A. Welker, Michael P. George
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Publication number: 20120030495Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.Type: ApplicationFiled: July 27, 2010Publication date: February 2, 2012Inventors: Sundeep Chandhoke, Lee E. Mohrmann, Adam C. Ullrich, Rodney D. Greenstreet
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Publication number: 20120025944Abstract: Systems and methods for timing of a passing of an object past a monitored location where the monitored location is being monitored by timing system having at least one automated object detection system for wirelessly detecting the passing of the object at the monitored location. The system comprises a remote entry computer system having a processor for executing computer executable instructions, a clock for determining a present time, a user interface for receiving user input data, a memory being a computer readable medium storing the computer executable instructions and the received user input data, and a communications interface for communicating with the timing system.Type: ApplicationFiled: July 29, 2011Publication date: February 2, 2012Applicant: INNOVATIVE TIMING SYSTEMS, LLCInventor: Kurt S. Hansen
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Publication number: 20120030499Abstract: Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.Type: ApplicationFiled: June 28, 2011Publication date: February 2, 2012Applicant: ARM LimitedInventor: Andrew Brookfield Swaine
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Patent number: 8108709Abstract: A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency.Type: GrantFiled: December 2, 2008Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ji-Eun Jang, Seok-Cheol Yoon
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Patent number: 8103897Abstract: Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a receiving circuit, stabilized communication is possible; and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit.Type: GrantFiled: August 27, 2007Date of Patent: January 24, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masami Endo, Takayuki Ikeda, Daisuke Kawae, Yoshiyuki Kurokawa
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Patent number: 8099731Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.Type: GrantFiled: January 18, 2007Date of Patent: January 17, 2012Assignee: Industrial Technology Research InstituteInventors: Cheng-Wei Li, Chung-Chou Shen
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Patent number: 8099618Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.Type: GrantFiled: October 23, 2008Date of Patent: January 17, 2012Inventors: Martin Vorbach, Volker Baumgarte
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Patent number: 8094765Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.Type: GrantFiled: November 15, 2010Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8090971Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.Type: GrantFiled: December 4, 2007Date of Patent: January 3, 2012Assignee: Synopsys, Inc.Inventor: Jose Angelo Rebelo Sarmento
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Patent number: 8086892Abstract: A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.Type: GrantFiled: September 20, 2010Date of Patent: December 27, 2011Assignee: Finisar CorporationInventors: Gerald L. Dybsetter, Jayne C. Hahain
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Patent number: 8087074Abstract: A token calculates a one time password by generating a HMAC-SHA-1 value based upon a key K and a counter value C, truncating the generated HMAC-SHA-1 value modulo 10^Digit, where Digit is the number of digits in the one time password. The one time password can be validated by a validation server that calculates its own version of the password using K and its own counter value C?. If there is an initial mismatch, the validation server compensate for a lack of synchronization between counters C and C? within a look-ahead window, whose size can be set by a parameter s.Type: GrantFiled: October 17, 2005Date of Patent: December 27, 2011Assignee: Symantec CorporationInventors: Nicolas Popp, David M'Raihi, Loren Hart
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Patent number: 8074093Abstract: Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the processing unit. In the optimization method, the software initially counts the number of operations completed during an initial subtask duration for the current process task, then recounts the number of operations completed during a repeat subtask duration when the voltage to the processing unit was increased incrementally based on its die size. The software then determines whether to (a) repeat such steps until the operations count stops increasing (and save the completed-operations count of that subtask duration), or (b) whenever the temperature of the processing unit exceeds a failsafe temperature, save the completed-operations count of the immediately preceding subtask duration. The task may be processed continuously at that optimized performance level and power level.Type: GrantFiled: June 3, 2011Date of Patent: December 6, 2011Inventor: Daniel L. Johnson
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Patent number: 8067955Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state machines generate the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.Type: GrantFiled: August 21, 2009Date of Patent: November 29, 2011Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8065552Abstract: A clock generation circuit is provided that multiplies an input signal of a specific frequency by a specific multiplication factor and generates an output clock signal. The clock generation circuit includes a PLL circuit that multiplies the input signal and generates the output clock signal, and a correction circuit that changes the multiplication factor of the PLL circuit. The correction circuit changes the PLL circuit multiplication factor by increasing or decreasing the specific multiplication factor, the change being performed only during a correction interval for each correction cycle, the correction cycle being longer than one cycle of the input signal, and being performed such that a time difference between an input synchronizing signal synchronized with the input signal and an output synchronizing signal synchronized with the output clock signal is reduced. The PLL circuit multiplies the input signal by the changed multiplication factor during the correction interval.Type: GrantFiled: May 27, 2008Date of Patent: November 22, 2011Assignee: Sony CorporationInventor: Tatsushi Sano