Counting, Scheduling, Or Event Timing Patents (Class 713/502)
  • Patent number: 7765315
    Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: July 27, 2010
    Assignee: Apple Inc.
    Inventors: James D. Batson, John S. Bushell, Gregory R. Chapman, Christopher L. Flick
  • Publication number: 20100185888
    Abstract: The invention relates to a microchip (1) for monitoring an electrical subassembly (12). Said microchip (1) comprises a means (3) for monitoring a supply voltage (9, 11) of the subassembly as well as a watchdog unit (4) for monitoring a program flow of a microprocessor (6). The invention makes it possible to reduce the space requirements of circuits used for performing safety-related functions in order to monitor an electrical subassembly (12).
    Type: Application
    Filed: July 28, 2006
    Publication date: July 22, 2010
    Applicant: Siemens Aktiengesellschaft
    Inventors: Ulrich Hahn, Rainer Siess
  • Patent number: 7761729
    Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: July 20, 2010
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekaran N. Gupta, Dean C. Moss
  • Patent number: 7757019
    Abstract: A mobile hub is proposed, the mobile hub includes a circular buffer for storing events, a timer for monitoring the storage period of an event stored in the buffer, and an event manager designed for discarding an event from the buffer when a time-out of the associated timer is exceeded. As no event can block the buffer any more a small-scale buffer can be used for the mobile hub.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dirk Husemann, Michael E. Nidd, Jonathan T. Waddilove
  • Patent number: 7750963
    Abstract: A circuit for generating a timing signal, the circuit having a memory and a pulse generator, the timing signal consisting of a number of pulses. The memory stores pulse count data, including an indication of the number of pulses in the timing signal, and rising edge and falling edge position data of the timing signal. The pulse generator produces the timing signal in accordance with the pulse count data and has a first circuit for generating rising edge signals, a second circuit for generating falling edge signals, an active control circuit for setting, in correspondence only with the pulse count data, corresponding rising edge signals as active state rising edge signals, and corresponding falling edge signals as active state falling edge signals, and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 6, 2010
    Assignee: Sony Corporation
    Inventors: Takashi Shimono, Hiroyasu Tagami
  • Patent number: 7752477
    Abstract: A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the reference clock. A frequency controller is configured to sample a count value of the counter by utilizing an input clock, to compare an increment value increased from the last sampled value with an expected value, and to control a frequency of the reference clock in accordance with a comparison result.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Goichi Otomo
  • Patent number: 7752481
    Abstract: According to one embodiment, there is provided an information processing apparatus, including a first clock portion to output a first signal when a measurement value coincides with first set time, a second clock portion to output a second signal when a measurement value coincides with second set time, and a controller to perform control to execute resume processing for a first purpose when the first clock portion outputs the first signal, and execute resume processing for a second purpose when the second clock portion outputs the second signal.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Morisawa
  • Patent number: 7752476
    Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: July 6, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Macri, Steven Morein, Ming-Ju E. Lee, Lin Chen
  • Patent number: 7747888
    Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Tim Frodsham, Michael J. Tripp, David J. O'Brien, Muraleedhara Navada, Naveen Cherukuri, Sanjay Dabral, David S. Dunning, Theodore Z. Schoenborn
  • Patent number: 7747890
    Abstract: A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signals are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Seonghoon Lee
  • Patent number: 7747892
    Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eskinder Hailu, Kazuhiko Miki, Jieming Qi
  • Patent number: 7743271
    Abstract: A method, system and program are provided for determining if a system clock has been reset backwards in time by using a randomly generated set of bytes (such as a randomly generated or type 4 UUID) as a time epoch. By generating a time epoch at boot time and whenever the system clock is set back in time, an application can compare the time epoch value at an earlier point in its execution, with the current time epoch. If the time epoch values are different, the application will know that the system clock has been set back in time.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: June 22, 2010
    Assignee: International Business Machines Corporation
    Inventor: Theodore Y. Tso
  • Patent number: 7739440
    Abstract: This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 15, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoming Zhu
  • Patent number: 7730495
    Abstract: An extensible control design framework is utilized to declaratively define a control (both visual and non-visual) and other components. The functionality of a control may be expanded by declaratively adding behaviors and semantics via an object called an action. The control does not become unduly complex by the addition of the behaviors and semantics. The action object encapsulates well-defined functionality and is associated with an existing control. The action object is also associated with an event or trigger such that the functionality is automatically executed when the event is raised. The functionality may be packaged in an independent application component such that a user who is not familiar with programming code may easily define logic and functionality for an application in a design environment.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: June 1, 2010
    Assignee: Microsoft Corporation
    Inventors: Nikhil Kothari, Andres M. Sanabria
  • Patent number: 7725757
    Abstract: In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the counter may be a control logic to generate a control signal to change from the first bus ratio to a second bus ratio, where the control logic is coupled to receive the counter value and control the counter based on this value. In this way, the bus ratio can change without draining the transaction queues of a processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Kiran Padweka, Arvind Mandhani, Durgesh Srivastava
  • Patent number: 7725756
    Abstract: A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding the delta to a previous accumulative offset for each clock period of the first clock signal. Whenever an overflow is encountered, the value of the accumulative offset is truncated. The second clock signal is interpolated between adjacent values.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: May 25, 2010
    Assignee: GoBack TV, Inc.
    Inventors: Javier Solis, Xuduan Lin, Michael Field
  • Patent number: 7725758
    Abstract: A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 25, 2010
    Assignee: STMicroelectronics SA
    Inventors: Jean-François Link, Dragos Davidescu, Sandrine Lendre
  • Patent number: 7725755
    Abstract: Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: May 25, 2010
    Assignee: Altera Corporation
    Inventors: Yan Chong, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan, Tzung-Chin Chang
  • Patent number: 7725591
    Abstract: Methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Andreas Ch. Doering, Silvio Dragone
  • Patent number: 7725759
    Abstract: A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 25, 2010
    Assignee: Sigmatel, Inc.
    Inventor: Matthew Henson
  • Patent number: 7725754
    Abstract: A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: May 25, 2010
    Assignee: Xilinx, Inc.
    Inventor: Laurent Fabris Stadler
  • Patent number: 7720186
    Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 18, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7719996
    Abstract: A logging system comprising counting logic adapted to generate a raw timestamp. The system further comprises encoding logic coupled to the counting logic and adapted to insert a group of bits of the raw timestamp into a predetermined timestamp template to produce an encoded timestamp. The template is selected based on a position of a most significant bit of the raw timestamp.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: May 18, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Michael Schroeder
  • Patent number: 7716513
    Abstract: A scaling factor used in time interpolation calculations is tuned so as to compensate for clock sources that generate timer interrupts both slower and faster than expected. The scaling factor is decreased when the timer interrupts are late and the scaling factor is increased when the timer interrupts are early. By being able to account for timer interrupts that are generated too early, time skips are minimized. The adjusted scaling factor is used in calculating system time and interpolation offset values.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: May 11, 2010
    Assignee: Graphics Properties Holdings, Inc.
    Inventor: Christoph Lameter
  • Patent number: 7716436
    Abstract: A system is disclosed that includes a host system to issue a write command, a primary storage controller to write data to a primary volume, and a secondary storage controller to mirror the data to a secondary volume. In the event the secondary storage controller is unable to mirror the data due to a busy state, a busy signal may be sent to the primary storage controller. The primary storage controller may initiate a timer in the event it receives the busy signal, and, in the event the busy state does not end before expiration of the timer, notify the host system that the primary and secondary volumes are in a suspended state. To alter the duration of the timer, the host system may be configured to dynamically alter the duration of the timer by sending a command to the primary storage controller.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Juan Alonso Coronado, Dinh Hai Le, Jayson Elliott Tsingine, Warren Keith Stanley
  • Patent number: 7716510
    Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 7716437
    Abstract: A system is disclosed that includes a host system to issue a write command, a primary storage device to write data to a primary volume, and a secondary storage device to mirror the data to a secondary volume. A task timer may be initiated upon sending the data from the primary storage device to the secondary storage device. The secondary storage device may also send an acknowledge signal to the primary storage device in the event it successfully mirrors the data to the secondary volume. In the event the acknowledge signal is not received before the timer expires, the primary storage device may notify the host system that the primary and secondary volumes are in a suspended state. To alter the duration of the timer, the host system may be further configured to dynamically alter the duration of the timer by sending a command to the primary storage device.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Juan Alonso Coronado, Dinh Hai Le, Jayson Elliott Tsingine, Warren Keith Stanley
  • Patent number: 7711975
    Abstract: In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the Universal Serial Bus cable is calculated, and the speed of the Universal Serial Bus cable is increased beyond 480 Mb per second in response to the determining and the calculating. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: James J. Choate
  • Publication number: 20100100759
    Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.
    Type: Application
    Filed: February 27, 2008
    Publication date: April 22, 2010
    Applicant: NANORADIO AB
    Inventors: Stefan Blixt, Christian Blixt
  • Patent number: 7702943
    Abstract: A real time clock comprises a counter which stores a count value, the count value representing a time signal. The counter may be written, for example by a host processor (not shown), such that the time signal can be set to any desired value. The real time clock comprises a check register that stores a check value. The content of the check register (i.e. the check value) is modified each time a write operation is performed on the counter. For example, the content of the check register can be updated by a control signal each time a write operation is performed on the counter. The check value stored in the check register is used for determining whether a write operation performed on the counter is an authorized write operation or an unauthorized write operation. The check value may be incremented each time a write operation is performed, replaced with a new random number each time a write operation is performed, or a combination of both.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: April 20, 2010
    Assignee: Wolfson Microelectronics plc
    Inventors: Holger Haiplik, Clive Robert Graham
  • Patent number: 7698582
    Abstract: An apparatus and method for compensating digital input delay in an intelligent electronic device is provided. A method is provided which provides for accurate SER data recording while facilitating the reduction of processing burden on the IED and optimization of system performance during the processing of SER data flow. An apparatus is further provided which generally includes a time delay element coupled to a sequential events recorder for compensating for delay in communication of a data signal such that the sequential events recorder records a compensated time for a select event based on the clock and the time delay. An apparatus is provided which includes an edge detection element for detecting either a rising or falling edge from the data signal.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: April 13, 2010
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Bai-Lin Qin, Max B. Ryan, Daniel P. Dwyer, Carl V. Mattoon
  • Patent number: 7698588
    Abstract: The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Chulwoo Kim, Stephen Douglas Weitzel
  • Publication number: 20100088536
    Abstract: The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a program memory and creating an instruction bundle consisting of a sequence of instructions to be processed in parallel. A compression buffer is interposed between the program memory and an instruction decompression unit, such that a compression code read in a previous clock cycle is ready at the beginning of a decompression cycle of the subsequent instruction bundle thereby avoiding a delay due to memory read latency.
    Type: Application
    Filed: May 18, 2009
    Publication date: April 8, 2010
    Inventors: Sang-suk LEE, Tai-song Jin
  • Patent number: 7693248
    Abstract: A timing recovery system and method for accelerated clock synchronization of remotely distributed electronic devices is provided. The system includes a phase locked loop, a linear estimator and control logic. The method includes sampling a clock signal received from an electronic device, applying a linear estimation technique to estimate the frequency and phase of the received signal and providing those estimates to a phase locked loop to accelerate the phase locked loop acquisition rate and secure signal lock quickly.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: April 6, 2010
    Assignee: Broadcom Corporation
    Inventors: Kevin Miller, Anders Hebsgaard
  • Publication number: 20100083024
    Abstract: An electronics device comprising a time information acquisition unit which acquires time information representing present time from an external device, an update unit which updates reference time stored in a reference time storage unit to time represented by the latest time information acquired by the time information acquisition unit each time the time information is acquired, a counter circuit which is formed by hardware and updates its count value at fixed cycles, an elapsed time measurement unit which measures an elapsed time since the update of the reference time by use of the counter circuit, a present time calculation unit which calculates present time by adding the elapsed time to the reference time stored in the reference time storage unit, and a response unit which makes the present time calculation unit calculate the present time and outputs the calculated present time if a present time output request is issued.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Hiroshi SHIBATA
  • Patent number: 7688925
    Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 30, 2010
    Assignee: ATI Technologies, Inc.
    Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji Menokki Kandiyil, Gin Yee, Joseph Macri
  • Patent number: 7689818
    Abstract: A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 30, 2010
    Assignee: Via Technologies, Inc.
    Inventor: Jen-Chieh Chen
  • Patent number: 7681199
    Abstract: Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 16, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul Gootherts, Douglas V. Larson
  • Patent number: 7676679
    Abstract: Nodes in a network include a pseudo-timestamp in messages or packets, derived from local pseudo-time clocks. When a packet is received, a first time is determined representing when the packet was sent and a second time is determined representing when the packet was received. If the difference between the second time and the first time is greater than a predetermined amount, the packet is considered to be stale and is rejected, thereby deterring replay. Because each node maintains its own clock and time, to keep the clocks relatively synchronized, if a time associated with a timestamp of a received packet is later than a certain amount with respect to the time at the receiver, the receiver's clock is set ahead by an amount that expected to synchronize the receiver's and the sender's clocks. However, a receiver never sets its clock back, to deter attacks.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 9, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Brian E. Weis, David A. McGrew
  • Publication number: 20100058103
    Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 4, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Andreas Menkhoff
  • Publication number: 20100058102
    Abstract: This invention relates to methods for managing the transmission and reception of data fragments that contains one or more data blocks using a single timer. The methods include the following steps: A method for managing the transceiving of data fragments, comprising the steps of: processing said fragments sequentially, wherein each fragment having a processing index that corresponds to the sequential processing of that fragment; processing each of said fragments until a termination upon the meeting of a first pre-defined condition; assigning a timer to an un-terminated fragment having the lowest processing index; starting said timer having a timeout value; and running said timer until the processing of said un-terminated fragment is terminated. The methods of this invention use only one timer for each connection and therefore reduce memory and operational needs in the management of the data fragments that are being received or transmitted.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicant: APACEWAVE TECHNOLOGIES CORPORATION
    Inventors: Yalun Li, William Li
  • Patent number: 7673166
    Abstract: An embodiment of the invention provides an apparatus for computation of processor clock frequency ratios in a multi-processor system. The apparatus includes a computation engine configured to determine a processor clock frequency ratio by reading counter values of a first counter and of a second counter within a frequency ratio computation interval, and configured to determine a value of the second counter at an end of a frequency ratio valid interval where the frequency ratio is applied, wherein the frequency ratio valid interval is subsequent to the frequency ratio computation interval, and wherein the frequency ratio valid interval does not overlap the frequency ratio computation interval.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 2, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan Yu Han Liu, James Mankovich
  • Patent number: 7669072
    Abstract: A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: February 23, 2010
    Assignee: Atmel Corporation
    Inventors: Alain Vergnes, Ludovic Dupre, David Dumas
  • Publication number: 20100037083
    Abstract: A method controls time based signals that are outputted from at least two processes of unit. A first signal is converted into a first signal value and indicates over a first time range of a first process with a first defined start time and a defined end time, in which present time is signalized by a spatially extensible and uniformly highlighted portion of the first time range defined between the first start time and the present time. A second signal is converted into a second signal value and indicates over a second time range of a second process with a second defined start time and free of an end time, in which the present time is signalized by a spatially extensible portion of the second time range onto which a variably highlighted and superposed section is overlaid, the section being defined between the second start time and the present time.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 11, 2010
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Giorgio Corsini, Laurent Cloutot
  • Publication number: 20100037082
    Abstract: In a remote controller, a startup time or a first time duration until the startup time is input into an input unit. A timer unit counts a clock time or a second time duration. A control unit generates a signal to turn on an electrical apparatus when the second time duration reaches the first time duration, or when the clock time equals to the startup time. A transmitting unit transmits the signal. In the electrical apparatus, a main unit operates main function. A transformer supplies electricity from an external power source to the main unit through a switch. A rectifier rectifies the signal. A signal identifying unit identifies it. A reservation memory unit keeps parameter for main function. A control unit turns on the switch and controls the main unit according to the parameter when the signal is received. A battery supplies electricity to above units.
    Type: Application
    Filed: July 13, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takafumi SAKAMOTO, Toshiyuki Nakanishi, Makoto Tsuruta, Keisuke Mera, Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20100037084
    Abstract: A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal and is stored, and a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal is provided.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 11, 2010
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: Alan LLOYD
  • Publication number: 20100036986
    Abstract: A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Inventor: SALIL SHIRISH GADGIL
  • Publication number: 20100037081
    Abstract: A computer system is arranged with a circular buffer that includes a piecewise linear map from a high-resolution counter arranged to maintain International Atomic Time. The piecewise linear map includes a current leg that is currently being used and also a future leg that will be used in the future. The future leg is computed while the current leg is still being used.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Inventors: Steven Froehlich, Michel H.T. Hack, Xiaoqiao Meng, Li Zhang
  • Patent number: 7661009
    Abstract: Apparatus and methods for discriminating late software commands sent to hardware from software executed by a processor. The apparatus, in particular, includes a storage device configured to receive information concerning a timing requirement for software commands transmitted from a microprocessor, where the timing requirement is dependent on a system time. A time counter is also included and configured to determine the system time. The apparatus further includes a comparator configured to determine whether the timing requirement has been met, and a switching circuit configured to selectively allow the software command to be issued from the processor to a hardware circuit based on the determination of whether the timing requirement has been met. Complementary methods are also disclosed.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: February 9, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: Tadeusz Jarosinski
  • Patent number: 7657770
    Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: February 2, 2010
    Assignee: LG Electronics Inc.
    Inventors: Hyung Sun Kim, Kang Soo Seo, Byung Jin Kim, Soung Hyun Um