Abstract: Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.

Abstract: A tick source device (10) configured to accept a plurality of input signals and then to select one of said plurality of input signals and to use said one of said plurality of input signals as a source to generate a single output signal (12) to drive a processing device. A method of generating a signal to drive a processing device in accordance with the above is also disclosed.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.

Abstract: A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full screen mode is executed, and a control hot key is enabled. Afterwards, an input of the control hot key is received to display a user interface. Finally, an input frequency inputted from the user interface is received, and the working frequency of the graphic chip is adjusted according to the input frequency in the frequency adjustment range. Therefore, even though the application program is executed in full screen mode, the working frequency of the graphic chip can still be adjusted according to requirements in any time, which is convenient for the user.

Abstract: A method and a receiver for recovering clock timing information from a serial data signal by determining data symbol transition times. The method comprises determining data symbol transition times of the serial data according to a first determination scheme, and further data symbol transition times of the serial data according to a second determination scheme. The transition times are then combined by a voting process, wherein the first determination scheme votes for the transition times that it determined, and wherein the second determination scheme votes for the transition times that it determined. The actual transition times are then determined as being the times that have the most votes.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

Abstract: The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used to plug at least one memory module; the flash memory is used to store BIOS programming codes, in which the BIOS programming codes are provided with at least one memory configuration programming codes for configuring the memory frequency and memory timing of the memory module; the central processing unit socket is used to plug the CPU, and the CPU is at least used to execute the memory configuration programming codes, so, after execution, they could provide a plurality of parameter options for memory frequency and memory timing of the memory modules to be selected one from them.

Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: The present invention discloses a power-saving trigger-type control device for dynamically and instantly varying frequency and a method thereof. The device comprises a signal control unit having at least two signal input terminals, a counting control unit, and a clock generator. The two signal input terminals respectively receive increment trigger actions and decrement trigger actions and then generate increment trigger signals and decrement trigger signals each counting to the same number as the corresponding trigger actions. The counting control unit counts the increment trigger signals or decrement trigger signals. The clock generator linearly increments or decrements output frequency according to the count of the increment trigger signals or decrement trigger signals. The device of the present invention further has a power controller to regulate output voltage.

Abstract: Methods and apparatuses for manufacturer to present Web-based edu-games so as to train retail staff member about the manufacturer and its products and to access edu-game data and retail sales data from a database. A Website can be created to provide a point of interaction between the manufacturer, retailer, and retail staff member. By accessing this Website, the retail staff member is presented with the web-based edu-games and learns about the manufacturer and its products. The retail staff member can be presented with incentives by the manufacturer for completing the web-based training off time, which may prevent the retailer from paying for the costs of training the retail staff member. Alternately, retailers can also do training in-house (e.g., if required by statute). Manufacturers and retailers compare education levels to sales data to determine the effects of the training.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Abstract: According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchronization module (30) comprises: a transfer register (31) for storing data which is communicated between the two circuit modules, a control circuit (32) for controlling the register in response to a respective timing signal (St1, St2) from the first and the second circuit module, the control circuit comprising a control chain for generating a control signal (CR) for the transfer register (31). The control chain includes at least: a repeater (34) for inducing changes in the value of the control signal, at least one edge sensitive element (35) for delaying a change in the signal value until a transition in a selected one of the timing signals is detected.

Abstract: Techniques to bolster the security of an AlphaEta cryptosystem using spectral phase encoding. In one aspect, a spatial light modulator (SLM) is used to change the spectral code (spectral phase) of each optical bit in response to the output of an extended key generator based on a cryptographic algorithm. In other aspects, additional time and polarization modulations are used to maintain high security levels as well as good performance levels. Such methods are combined with traditional key generation methods such as key-distribution centers or one-way mathematical algorithms to bolster the security of traditional key generation as well.

Abstract: Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.

Abstract: A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value.

Abstract: An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: Simply constituted electronic apparatus that can definitely output an outputted data after predetermined length of time from a time when an inputted data processing is started, even if data processing time of the inputted data varies with the contents of the data.

Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.

Abstract: A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.

Abstract: A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Abstract: A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.

Abstract: A system that estimates a dominant computational resource which is used by a computer program. During operation, for each basic block in the computer program, the system determines a nesting level for the basic block. Next, the system selects basic blocks with nesting levels greater than a specified threshold. For each selected basic block, the system analyzes the basic block to estimate the dominant computational resource used by the basic block. The system then uses the estimated dominant computational resources for the selected basic blocks to estimate the dominant computational resource for the computer program.

Abstract: A method of receiving data packets. In the method of receiving data packets, a determination is made as to whether a received data packet is received out of an expected order. If the determining step determines a received packet is out of the expected order, a time period is calculated to wait for one or more missing data packets based at least in part on an expected time of receiving the one or more missing data packets.

Abstract: An efficiency-based workload manager samples multiple actual resource use characteristics while a process executes, where the actual resource use characteristics designate a portion of a total amount of system resources available to the process that are utilized by the process at multiple times over a sampling period. Next, responsive to detecting the conclusion of the sampling period, the efficiency-based workload manager determines an operation based resource utilization threshold for the process based on a maximum resource use within the multiple samplings of actual resource use characteristics. Then, the efficiency-based workload manager stores the operation based resource utilization threshold for access by a workload manager, where the workload manager uses the operation based resource utilization threshold to restrict the process to resource use up to the operation based resource utilization threshold within an execution environment managed by the workload manager.

Abstract: Event-driven processor architectures are particularly suited for use in multiple sensor node networks and simulators of such networks. A first variation of the processor is particularly suited for use in a sensor node in a wireless sensor network. Through use of the event-driven architecture and special message and timing coprocessors, this embodiment of the invention is optimized for low energy requirements and data monitoring operations in sensor networks. A second embodiment of the invention includes modifications necessary for use of the processor in a network simulation protocol.

Abstract: A sequencing control circuit includes a chip (30), a first control circuit (10), a second control circuit (20), and a lagging voltage terminal (700). The chip is connected to a first voltage terminal (100) and a second voltage terminal (300). The first control circuit is connected to the chip. The second control circuit is connected to a signal terminal (600) of an electronic component. The lagging voltage terminal is connected to the first control circuit for providing a signal posterior to a signal from the first voltage terminal. When the lagging voltage terminal and the signal terminal both input a high level signal, the output terminal of the first control circuit and the second control circuit both output a high level signal, thereby ensuring that the signal from the second voltage terminal is posterior to the signal from the first voltage terminal being input to the chip.

Abstract: A watchdog timer includes an execution address detection section comparing a value of a program counter of a central processing unit with an address of a predetermined area, a timer count section having a first overflow time set thereto when the execution address detection section indicates that the value of the program counter has entered the predetermined area, and a counter clear control section generating a request signal for clearing the timer count section when the execution address detection section indicates that the value of the program counter has exited from the predetermined area.

Abstract: A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.

Abstract: A timer circuit includes a storage unit to store a series of first data content relating to a time into a specified address area, a target value generation unit to read the first data content from a read address of the storage unit and to generate, as a target value, third data content in which second data content is added to the first data content, a counter to perform counting and to output a count-up signal when the counting is performed up to the target value, and a control unit to sequentially designate a next read address of the storage unit at each count-up and to cause the series of operations of the target value generation unit and the counter to be executed.

Abstract: To provide a method for enabling a microprocessor to be restarted after rewriting a program without providing a dedicated circuit and an apparatus using the method, a timer means for counting a predetermined clock is controlled in the following first and second mode, where in the first mode, the timer means is rest (count-cleared) at predetermined intervals by a program so as to monitor an operating status of the program, and in the second mode, the microprocessor is restarted without resetting the timer means at predetermined intervals by the program.

Abstract: A multi-processing system includes: a selecting unit that selects a clock frequency for each processor chips based on lot-to-lot variation thereof; a calculating unit that calculates chip performance of the processor chips operating at the clock frequencies; a judging unit that judges whether a total of chip performance of the processor chips is equal to or higher than a predetermined system performance; and a setting unit that sets the clock frequencies to the processor chips when the total is equal to or higher than the predetermined system performance.

Abstract: An apparatus is disclosed. The apparatus comprises a device and a counter system coupled thereto. The counter system provides an indication of a number of times the device is inserted into a slot. Through the use of the device disclosed above, a history and a number of insertions of a particular device within a system can be known and therefore it can be determined if the integrity of the device is threatened.

Abstract: A method for implementing multiple clock interfaces in a single media player. The method and accompanying device are configured to utilize the preferred secure clock. If the remote host cannot support a secure clock, the method can alternately implement an anti-rollback clock interface. For each download session the clock data is separately maintained for subsequent access during playback of the corresponding content. The method supports secure digital rights management content downloads.

Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.