Counting, Scheduling, Or Event Timing Patents (Class 713/502)
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Patent number: 8423815Abstract: An information processing device, such as cellular phone, includes a first timer set for executing count processing applied to a preassigned first processing, a second timer set for executing count processing applied to the preassigned first processing, a display state determination unit configured to determine a display state of a display unit, and a timer switching unit configured to select and set the first timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “ON” state and to select and set the second timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “OFF” state.Type: GrantFiled: April 23, 2008Date of Patent: April 16, 2013Assignee: Fujitsu Mobile Communications LimitedInventor: Yasuhiko Abe
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Patent number: 8417981Abstract: A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located locally at each unit. Once a time conversion is initiated, a time stamp is received by the processor and the time counter in the new time domain commences calculating an adjustment count. Once the converted time is received from the processor, the received time plus the adjustment count are summed to provide a time base for the new time domain. The time counters continue counting in their respective time domains after conversion.Type: GrantFiled: January 27, 2010Date of Patent: April 9, 2013Assignee: Ruggedcom Inc.Inventors: Yuri Luskind, Petru Ovidiu Lupas, Roger Moore
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Patent number: 8413244Abstract: Techniques for classifying unknown files taking into account temporal proximity between unknown files and files with known classifications are disclosed. In response to a classification request for a target file, client systems hosting (or hosted) instances of the target file are identified. For each system, files created around the time the target file was created on the system are identified. Within the identified files, files with known classifications are identified, and a score is determined for each such file to measure temporal proximity between the creation of the file and the creation of the target file. Local temporal proximity scores aggregate the scores for the client system. Global temporal proximity scores measures an aspect of the local temporal proximity scores for all identified client systems. The global temporal proximity scores are fed into a classifier to determine a classification, which is returned in response to the classification request.Type: GrantFiled: November 11, 2010Date of Patent: April 2, 2013Assignee: Symantec CorporationInventor: Carey S. Nachenberg
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Publication number: 20130080819Abstract: A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Inventors: Stephen Bowling, Igor Wojewoda
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Patent number: 8407512Abstract: An apparatus for upgrading a standard PC system to a fail-safe computation system, comprising a plug device for plugging into the computation system, a memory module, a microcontroller, and a first device for generating a first time signal, wherein the microcontroller and the first device interact such that the computation system is provided with the first time signal through the plug device device.Type: GrantFiled: August 3, 2010Date of Patent: March 26, 2013Assignee: Siemens AGInventors: Jens Kydles, Markus Walter
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Patent number: 8407508Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.Type: GrantFiled: September 16, 2010Date of Patent: March 26, 2013Assignee: Genesys Logic, Inc.Inventors: Wei-te Lee, Shin-te Yang, Wen-ming Huang
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Publication number: 20130073891Abstract: A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the, external arithmetic unit.Type: ApplicationFiled: March 16, 2011Publication date: March 21, 2013Inventor: Eberhard Boehl
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Patent number: 8402302Abstract: An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The counter-based time generator is driven by an oscillator. The timer system further includes a temperature sensor placed in the proximity of the oscillator or a crystal used by the oscillator, and a look-up control table holding temperature values associated with corresponding control values representative of the configurable parameter value A. The look-up control table is generated when the timer system is synchronized with a synchronization source so that the temperature and control values are characteristic of the operation of the timer system in synchronization.Type: GrantFiled: June 12, 2009Date of Patent: March 19, 2013Assignees: IMSYS AB, Conemtech ABInventors: Stefan Blixt, Christian Blixt
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Publication number: 20130067265Abstract: An apparatus including an air filter for an air conditioning device, a warning device, a computer processor, a computer memory, a count setting device, and a reset device. The computer processor is programmed to set a value of a timer count variable to an operator input start value in the computer memory in response to the count setting device. The computer processor is programmed to count down the value of the timer count variable and when the value of the timer count variable has counted down to an alarm level, to activate the warning device. The reset device is actuated by an operator to cause the computer processor to deactivate the warning device and to reset the value of the timer count variable to the operator input start value, and to cause the value of the timer count variable to be counted down.Type: ApplicationFiled: November 1, 2011Publication date: March 14, 2013Inventor: Larry Grayson
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Patent number: 8397099Abstract: The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time.Type: GrantFiled: September 10, 2010Date of Patent: March 12, 2013Assignee: Microsoft CorporationInventors: Nicholas A. Allen, Justin D. Brown
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Patent number: 8396917Abstract: According to the present invention, it is possible to rearrange an arrangement unit on an appropriate storage device at a more appropriate timing in a complex computer system.Type: GrantFiled: March 8, 2010Date of Patent: March 12, 2013Assignee: Hitachi, Ltd.Inventors: Tomoaki Kakeda, Takato Kusama, Nobuo Beniyama
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Patent number: 8397098Abstract: A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a sampling cycle to obtain a sampling result. When the sampling result indicates a non-compliant pattern, the phase of at least one of the first clock signal and the second clock signal is adjusted. Desirably, the core logic circuit keeps on working with the current first and second clock signals while continuing the sampling procedure of the second clock signal based on the first clock signal when the sampling result indicates a compliant pattern.Type: GrantFiled: October 24, 2007Date of Patent: March 12, 2013Assignee: Via Technologies, Inc.Inventor: Paul Su
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Patent number: 8392686Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.Type: GrantFiled: September 18, 2008Date of Patent: March 5, 2013Assignee: Micron Technology, Inc.Inventors: Joseph M. Jeddeloh, Paul LaBerge
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Patent number: 8386828Abstract: Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.Type: GrantFiled: June 16, 2010Date of Patent: February 26, 2013Assignee: Xilinx, Inc.Inventors: Sai Lalith Chaitanya Ambatipudi, Seu Wah Low, Christopher J. Borrelli, Loren Jones
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Patent number: 8386667Abstract: This invention relates to techniques for managing the transmission and reception of data fragments that contains one or more data blocks using a single timer. One embodiment of the invention includes the following steps: processing the fragments sequentially, wherein each fragment has a processing index that corresponds to sequential processing of that fragment; processing each of the fragments until a termination upon meeting a first pre-defined condition; assigning a timer to an un-terminated fragment having a lowest processing index; starting said timer having a timeout value; and running said timer until the processing of said un-terminated fragment is terminated. This invention uses only one timer for each connection and therefore reduces memory and operational needs in the management of the data fragments that are being received or transmitted.Type: GrantFiled: August 26, 2008Date of Patent: February 26, 2013Assignee: Sun Management, LLCInventors: Yalun Li, William Li
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Patent number: 8384420Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention selects a set of the finite state machines to participate in an operation. If one or more of the finite state machines are selected for operation, the method waits until all selected finite state machines generate the ready signal. If none of the finite state machines are selected for operation, the method waits until at least one non-selected finite state machine generates the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.Type: GrantFiled: August 21, 2009Date of Patent: February 26, 2013Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Publication number: 20130047023Abstract: Adaptive clocking schemes for synchronized on-chip functional Hocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example, in embodiments, the docking schemes allow for the capacity utilization of a logic path to be increased.Type: ApplicationFiled: December 20, 2011Publication date: February 21, 2013Applicant: Broadcom CorporationInventors: Paul Penzes, Mark Fullerton
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Patent number: 8381234Abstract: A system for managing a application includes a clock unit outputting time signals, a storage unit storing an age table, a detection unit and a resetting unit. The application includes a logical pointer and a flag carrying a flag bit. The age table includes ordered logical headers and age values, each logical header associated with an age value, the logical pointer pointing to one logical header, the age value having an increment as the logical pointer moves forward along the logical headers. The detection unit receives the time signals and reads the flag bit and moves the logical pointer to a succeeding logical header with a first step if the flag bit changes and with a second step if the flag bit remains unchanged during interval between two time signals. The second step is larger than the first step. The resetting unit resets the flag bit.Type: GrantFiled: October 10, 2008Date of Patent: February 19, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Kim-Yeung Sip
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Publication number: 20130042138Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: Micron Technology, Inc.Inventors: Kang-Yong Kim, Jacob Robert Anderson, Huy Vo
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Patent number: 8375239Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.Type: GrantFiled: February 25, 2011Date of Patent: February 12, 2013Assignee: Renesas Electronics CorporationInventors: Yoshikazu Nara, Yasuhiko Takahashi
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Patent number: 8375231Abstract: A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number.Type: GrantFiled: July 28, 2010Date of Patent: February 12, 2013Assignee: Silison Laboratories Inc.Inventors: D. Matthew Landry, Russell J. Apfel
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Patent number: 8370677Abstract: A time synchronized measurement system has a master device and a slave device. The master device and the slave device each have a time measurement device for assigning a corresponding time of sending and/or receiving a piece of measurement information. The master device also has a reference clock pulse-generating device for transmitting a reference clock signal to the slave device. The reference clock signal is modulated by a piece of information on a common time basis for the master device and the slave device.Type: GrantFiled: May 13, 2010Date of Patent: February 5, 2013Assignee: Tektronix, Inc.Inventors: Sven Foerster, Steffen Schmack, Michael Schuricht, Hans-Ulrich Vollmer
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Patent number: 8364290Abstract: A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the system master signal, and carrying out at least one operation based on the value of the other master signal. For example, a machine controller may provide a system virtual master signal and synchronize one or more module virtual master signals to the system virtual master based on the system virtual master count value. One or more components of the module may operate based on the count value of the module virtual master signal. The use of an asynchronous control method may advantageously increase the flexibility of the machine. Because the operation of the components of the machine may depend on respective virtual master signals, a machine using asynchronous control methods may advantageously continue operating one component or module in the event of a fault involving other components.Type: GrantFiled: March 30, 2010Date of Patent: January 29, 2013Assignee: Kimberly-Clark Worldwide, Inc.Inventor: Kenneth Allen Pigsley
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Patent number: 8359489Abstract: A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.Type: GrantFiled: October 18, 2010Date of Patent: January 22, 2013Assignee: Etron Technology, Inc.Inventors: Huan-Hsiang Shen, Chih-Kao Chen, Chien-Cheng Kuo
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Patent number: 8352642Abstract: The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.Type: GrantFiled: November 2, 2010Date of Patent: January 8, 2013Assignees: Himax Technologies Limited, Himax Media Solutions, Inc.Inventors: Mu-Hsien Hsu, Chih-Haur Huang
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Publication number: 20120331331Abstract: A microcontroller includes a first voltage detector that detects whether a power supply voltage is equal to or lower than a first voltage value to generate a first signal, a second voltage detector that detects whether the power supply voltage is equal to or lower than a second voltage value to generate a second signal, the second voltage value being lower than the first voltage value, a real-time clock that includes a memory and a clock counter responsive to a clock signal, and a Central Processing Unit (CPU) that receives the first signal. The first voltage detector, the second voltage detector, the real-time clock and the CPU are formed on a single chip. The clock counter receives the second signal. The memory stores a first value according to a second signal, and stores a second value according to a setup of time information to the clock counter.Type: ApplicationFiled: September 10, 2012Publication date: December 27, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masataka Nakano
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Patent number: 8341453Abstract: A transmission apparatus that transmits data according to a protocol has a timer, a memory, a processor, and a transmission unit. The processor stores, in the memory, type data indicating a single type of time from a plurality of types of time that are to be measured according to the protocol. The transmission unit transmits data according to the protocol and starts the measurement of time of the type indicated by the type data stored in the memory using the timer after the data has been transmitted.Type: GrantFiled: September 12, 2008Date of Patent: December 25, 2012Assignee: Canon Kabushiki KaishaInventors: Daisuke Shiraishi, Kazuhiko Morimura
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Patent number: 8341443Abstract: A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC.Type: GrantFiled: May 11, 2007Date of Patent: December 25, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Cor Voorwinden, Michael Priel
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Patent number: 8327180Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.Type: GrantFiled: June 3, 2011Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
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Patent number: 8326364Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.Type: GrantFiled: May 13, 2010Date of Patent: December 4, 2012Assignee: Texas Instruments IncorporatedInventors: Gary F. Chard, T-Pinn R. Koh, Yilun Wang
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Patent number: 8321713Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.Type: GrantFiled: November 3, 2009Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventor: Dean Nobunaga
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Publication number: 20120297233Abstract: Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: John Ross
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Patent number: 8316456Abstract: A system and method for providing modified rights information to an application on an electronic device. A centralized component monitors both a system clock and a secure clock. The centralized component calculates the difference between the time of the system clock and the time of the secure clock and thereafter modifies the access rights information for the application by the difference between the times. The modified access rights information is then presented to the application for use.Type: GrantFiled: December 30, 2004Date of Patent: November 20, 2012Assignee: Nokia CorporationInventor: Juha Siukonen
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Patent number: 8316147Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.Type: GrantFiled: June 15, 2010Date of Patent: November 20, 2012Assignee: Apple Inc.Inventors: James D. Batson, John S. Bushell, Gregory R. Chapman, Christopher L. Flick
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Patent number: 8312309Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.Type: GrantFiled: March 5, 2008Date of Patent: November 13, 2012Assignee: Intel CorporationInventors: Eric L. Hendrickson, Sanjoy Mondal, Larry Thatcher, William Hodges, Lance Hacking, Sankaran Menon
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Patent number: 8312193Abstract: A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with the request to communicate at least after the period of cycles has passed since the master device sent the request to communicate to the switch without waiting to receive an acknowledgment from the switch that the master device can communicate with the slave device.Type: GrantFiled: January 8, 2010Date of Patent: November 13, 2012Assignee: International Business Machines CorporationInventors: Martin Ohmacht, Krishnan Sugavanam
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Publication number: 20120278648Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.Type: ApplicationFiled: October 27, 2011Publication date: November 1, 2012Inventors: Elyar E. Gasanov, Ilya V. Neznanov, Yurii S. Shutkin, Andrey P. Sokolov, Pavel A. Panteleev
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Patent number: 8300752Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.Type: GrantFiled: August 15, 2008Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
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Patent number: 8294722Abstract: An interface apparatus and method are provided. The interface apparatus includes a level detecting unit detecting a level of an inputted control signal, a counter unit increasing or decreasing a count value according to the level detected in the level detecting unit, and a driving control unit outputting a driving control information mapped into a count value of the counter unit.Type: GrantFiled: November 13, 2006Date of Patent: October 23, 2012Assignee: LG Display Co., Ltd.Inventors: Han Young Hong, Hyun Ha Hwang
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Patent number: 8291254Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.Type: GrantFiled: June 22, 2010Date of Patent: October 16, 2012Assignee: Texas Instruments IncorporatedInventors: Gary F. Chard, T-Pinn R. Koh
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Patent number: 8281178Abstract: A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every read of the monotonic time from the clock object. The clock object can also include an indication of a level of trust of the clock time.Type: GrantFiled: April 14, 2009Date of Patent: October 2, 2012Assignee: Seagate Technology LLCInventor: Robert H. Thibadeau
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Patent number: 8271824Abstract: A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit.Type: GrantFiled: October 29, 2009Date of Patent: September 18, 2012Assignee: Renesas Electronics CorporationInventor: Reiko Kuroki
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Patent number: 8271826Abstract: Write pointer generation units successively switch and indicate storage locations of data transmitted from a transmitter end LSI from plural buffers constituting FIFO circuits. A clock-step ring buffer delays a gated step signal to instruct an operation stop. When receiving the gated stop signal delayed by the clock-step ring buffer, the write pointer generation units stop switching instructions of the storage locations.Type: GrantFiled: August 22, 2008Date of Patent: September 18, 2012Assignee: Fujitsu LimitedInventor: Satoshi Nakagawa
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Patent number: 8271770Abstract: A computer motherboard with automatically adjusted hardware parameter values restarts automatically and proceeds with overclocking or power-saving operation in case the computer motherboard hangs due to preceding overclocking or power-saving operation.Type: GrantFiled: March 4, 2009Date of Patent: September 18, 2012Assignee: MSI Computer (Shenzhen) Co., LtdInventors: Chung-Hsing Chang, Tung-Jung Tsai, Yu-Tsung Kao
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Patent number: 8266466Abstract: The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters located on separate packet processing cards can be synchronized. The synchronizing of these packet processing cards provides tracking of how long it takes for packets to be processed, provides the ability to generate packet headers that include sequence numbers for robust header compression, and allows the use of encryption protocols without a time reference signal. The synchronization is provided by sending the cards with counter value information and this information can be used to update the card's internal counter value information so that the card is synchronized with other cards.Type: GrantFiled: May 21, 2007Date of Patent: September 11, 2012Assignee: Cisco Technology, Inc.Inventors: Hamed Eshraghian, Werner Niebel, Matthew H. Harper
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Patent number: 8261134Abstract: A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.Type: GrantFiled: January 28, 2010Date of Patent: September 4, 2012Assignee: Cray Inc.Inventors: Dennis C. Abts, Steven L. Scott, Aaron F. Godfrey
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Patent number: 8250399Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.Type: GrantFiled: January 7, 2010Date of Patent: August 21, 2012Assignees: Marvell International Ltd., Marvell Israel (M.I.S.L.) Ltd.Inventors: Tal Mizrahi, Carmi Arad, Martin White, Tsahi Daniel
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Patent number: 8250398Abstract: An electric vehicle charging station, which does not include a battery-backed Real Time Clock, is in a charging station network managed by a charging station network server. Upon booting, the charging station requests actual real time from a remote source. While the charging station has not received the actual real time, it records the time of charging station specific events in a local system time format that resets when the charging station loses power. The charging station maintains the events recorded in their local system time until actual time is received. When actual real time is received, the charging station synchronizes its local system clock with the actual real time and converts the time of each event into real time format. When actual time is received, the charging station converts the time of each event into real time format. After the time of the events are converted to real time format, they are communicated to the charging station network server for further processing.Type: GrantFiled: February 19, 2010Date of Patent: August 21, 2012Assignee: Coulomb Technologies, Inc.Inventors: James Solomon, Hongfei Cheng
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Patent number: 8245068Abstract: A device having a power supply monitoring capabilities, the device includes: a power supply unit; at least one real time clock generator counter adapted to receive a supply voltage from the power supply unit; a fixed value storage circuit that is un-accessible to software executed by a processor; wherein the fixed value storage circuit stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit, being accessible to the processor; wherein the volatile storage unit is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit is designed such that there is a low probability that the reset value equals the fixed value; and a comparator adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit.Type: GrantFiled: October 27, 2006Date of Patent: August 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Michael Priel, Asaf Ashkenazi, Dan Kuzmin
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Patent number: 8239703Abstract: A method controls time based signals that are outputted from at least two processes of unit. A first signal is converted into a first signal value and indicates over a first time range of a first process with a first defined start time and a defined end time, in which present time is signalized by a spatially extensible and uniformly highlighted portion of the first time range defined between the first start time and the present time. A second signal is converted into a second signal value and indicates over a second time range of a second process with a second defined start time and free of an end time, in which the present time is signalized by a spatially extensible portion of the second time range onto which a variably highlighted and superposed section is overlaid, the section being defined between the second start time and the present time.Type: GrantFiled: August 10, 2009Date of Patent: August 7, 2012Assignee: Siemens AktiengesellschaftInventors: Giorgio Corsini, Laurent Cloutot