Abstract: A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a sampling cycle to obtain a sampling result. When the sampling result indicates a non-compliant pattern, the phase of at least one of the first clock signal and the second clock signal is adjusted. Desirably, the core logic circuit keeps on working with the current first and second clock signals while continuing the sampling procedure of the second clock signal based on the first clock signal when the sampling result indicates a compliant pattern.

Abstract: A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.

Abstract: The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit.

Abstract: An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding to the ADC largely transparent to the end-user of the ADC. Therefore, multiple ADCs may be easily synchronized with each other, even if they have different group-delays, and they may further be synchronized with other types of ADCs that do not have group-delays. The data from the ADCs may also be synchronized with external events. The ADC timing engine (ATE) may be programmed with a number of parameters to set proper delays taking into account not only the group-delays corresponding to the various ADC, but delays stemming from a variety of other sources. Multiple ATEs may be synchronized with each other to ensure that data acquisition by the participating ADCs is started and/or stopped at the same point in time.

Abstract: The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design.

Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.

Abstract: A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.

Abstract: A receiving apparatus includes: a clock unit that outputs time information; a synchronizing (sync) packet receiving unit that receives a sync packet which contains transmitting time information and which is sent from a transmitting apparatus over an asynchronous network; a magnitude-of-jitter calculation unit that calculates as a magnitude of a jitter a difference between a first difference, which is a difference between the receiving times of two adjoining sync packets received by the sync packet receiving unit, and a second difference which is a difference between the transmitting times of the two sync packets; a delay time estimation unit that obtains the delay time of the sync packet on the basis of magnitudes of jitters calculated by the magnitude-of-jitter calculation unit; and a time correction unit that compensates the transmitting time of the sync packet, which is received by the sync packet receiving unit, on the basis of the delay time of the sync packet, which is obtained by the delay time estimat

Abstract: Exemplary systems and methods include a distribution device that maintains a dock rate and distributes a series of tasks to a group of execution devices. Each task has a plurality of samples per frame associated with a time stamp indicating when the task is to be executed. The execution devices execute the series of tasks at the times indicated and adjust the number of samples per frame in relation to the dock rate maintained by the distribution device.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.

Abstract: A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

Abstract: Methods and structures are provided for multi-lane data communication with measurable latency. In a particular embodiment, part of a parallel data set is transmitted from a first device to a second device on a plurality of slave lanes and another part of the data set is transmitted from the first device to the second device on a master lane. A known master delay is applied to data in the master lane that is greater than or equal to the known maximum skew between the lanes. The slave lanes are delayed as needed to align their data with the master lane. In one embodiment, part of the known master lane delay is applied on the first device and another part is applied on the second device. In another embodiment, all of the known master lane delay is applied on the first device and none of it is applied on the second device. In another embodiment, all of the known master lane delay is applied on the second device and none of it is applied on the first device.

Abstract: A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.

Abstract: A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

Abstract: According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.

Abstract: A method and apparatus for synchronizing time within a data protection system is described. In one embodiment, the method includes processing input/output activity information associated with at least one client computer, wherein the input/output activity information comprises at least one local client timestamp, determining at least one server timestamp for the at least one local client timestamp and modifying the input/output activity information with the at least one server timestamp.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase information provider and a feedback path. The calculator is clocked with a clock of the first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.

Abstract: A system may generate from a first value, based on rounding information, a first security key that matches a second security key whenever the first value and a second value from which the second security key is generated differ by less than a non-zero predetermined amount. The second security key may be generated from the second value rounded to a multiple of a rounding interval that is nearest to the second value. The rounding information may include a rounding direction indication. The rounding direction indication may indicate the direction in which the second value is rounded to the multiple of the rounding interval nearest to the second value.

Abstract: A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking periods. The skew adjusting circuit receives a pixel clock signal and adjusts a clock phase of the pixel clock signal by delaying the pixel clock signal with a controllable skew according to a feedback control signal so as to generate the processed pixel clock signal. The processing device stores a predetermined test pattern synchronized with the inserted test pattern, determines an optimum skew by comparing the sampled test patterns with the predetermined test pattern, and generates the feedback control signal including information indicating the optimum skew.

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: An interface apparatus and method are provided. The interface apparatus includes a level detecting unit detecting a level of an inputted control signal, a counter unit increasing or decreasing a count value according to the level detected in the level detecting unit, and a driving control unit outputting a driving control information mapped into a count value of the counter unit.

Abstract: When the synchronization information, transmitted from a synchronization information output unit of a clock master side device, is detected by a synchronization information detection unit, the clock slave side device associates the synchronization information with the timestamp information at the time of detection of the synchronization information. Based on the timestamp information associated with the currently received synchronization information, the timestamp information associated with at least one synchronization information up to the synchronization information received last time and transmission period information of the synchronization information, a calculation/decision unit decides whether or not a predetermined condition is met. When the condition is met, the calculation/decision unit supplies the currently received synchronization information to a clock synchronization technique function unit.

Abstract: Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.

Abstract: An interface device allows data communication between a controller and a plurality of circuit units. The interface device has a first interface for a connection to the controller, a second interface for a connection to a second circuit unit, and a third interface for a connection to a second circuit unit. An interface calibrating unit is coupled to the second and third interfaces and a non-volatile calibrating parameter memory is arranged in the interface calibrating unit or coupled to the calibrating unit. The memory is adapted to store calibrating parameters for the second and third interfaces.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbols in one or more clock cycles of a clock signal based on the data rate. The predetermined number of symbols is the same for each data rate selectable by the data aggregation module. The data aggregation module outputs the aggregated symbols to a deskew buffer of the deskew unit in a clock cycle of a clock signal. The deskew buffer deskews symbols received from the data aggregation module and outputs the deskewed symbols.

Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Abstract: A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than or equal to a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.

Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.

Abstract: There is provided a distributed control system including a plurality of field controllers which are connected through a control network. Each of the field controllers includes: a control clock that defines a control timing of the field controller; and an adjustment unit that adjusts a control time of the control clock depending on a network time obtained through the control network.

Abstract: A data processing circuitry for processing data is disclosed.

Abstract: A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit.

Abstract: Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.

Abstract: To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI1) outputs transfer data and a transfer synchronization clock signal to a slave (LSI2). For the edge of a clock signal used for data output at the master (LSI1), the slave (LSI2) latches input data by using a reverse edge. Moreover, upon data transfer from the slave (LSI2) to the master (LSI1), the master (LSI1) selects a latch timing of input data from a plurality of timings so that the transfer time to an internal circuit of the master (LSI1) side is identical regardless of which latch timing is selected.

Abstract: A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.

Abstract: A method, apparatus, and system for coordinated link power management. Some embodiments of a method include receiving an exit latency for each of a group of link states for a link, with a device being coupled to an interconnect via the first link. A latency tolerance value is determined and communicated, and a platform latency is received. The method further provides for determining a link budget for the device, the link budget indicating an amount of time available for an exit from a link state for the device; and selecting one of the link states based at least in part on the link budget.

Abstract: A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay circuit, wherein a delay range and a delay step size of the delay circuit is based on the control signal value. A delay select control signal is provided to the delay circuit to select a specific delay within the delay range.

Abstract: In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it.

Abstract: A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first measuring operating mode using a controllable integrated multiplexer to measure an asymmetrical signal lag of a measuring path, which includes the integrated signal path and the integrated multiplexer, and a measuring signal being able to be decoupled in a second measuring operating mode using the controllable integrated multiplexer to measure the asymmetrical signal lag of the integrated multiplexer.

Abstract: Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.