Abstract: Embodiments of the present invention relate to an approach for reusing information/knowledge. Specifically, embodiments of the present invention provide an approach for retrieving previously stored data to satisfy queries (e.g., jobs/tickets) for solutions to problems while maintaining privacy/security of the data as well as ensuring the quality of the results. In a typical embodiment, a query for a solution to a problem is received and details are extracted therefrom. Using the details, a search is performed on a set of data stored in at least one computer storage device. Based on the search, a set of results will be generated and classified into a set of categories. In any event, the quality of each of the set of results will be assessed based on the usefulness of the set of results.

Abstract: A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function.

Abstract: A computer-implemented method for providing software fault tolerance is provided. A multithreaded program is executed. The program execution includes a plurality of multithreaded processes. A set of inputs is provided to one of the multithreaded processes and the inputs set is copied to each of the other multithreaded processes. The executions of the multithreaded processes are divided into deterministic subsets of the execution that end at a checkpoint. An execution of the deterministic subset is speculatively executed continuously on one of the multithreaded processes. Upon completion of execution through the checkpoint, the successfully completed execution path through the deterministic subset is retired. Execution of the deterministic instructions subset on the other multithreaded process is continued along the completed execution path.

Abstract: The invention provides a control device for mutually monitoring two microcomputers at a low cost while reducing a parts number and doubly monitoring abnormality in each of the microcomputers. The control device transmits a reset signal to a main microcomputer and resets the main microcomputer when a frequency of a first pulse signal deviates from a normal frequency range determined by a frequency calculating means, in which the first pulse signal is output from the main microcomputer, and the frequency calculating means calculates a frequency of the first pulse signal by an input of the first pulse signal to a sub microcomputer. The control device transmits a reset signal to the sub microcomputer and resets the sub microcomputer when a frequency of a second pulse signal deflects from a normal frequency range, by an input of the second pulse signal to the main microcomputer from the sub microcomputer.

Abstract: A dual redundant process controller is provided. The controller comprises a first processor, memory, and instance of a process control application stored in the first memory. The controller further comprises a second processor, memory, and instance of the process control application stored in the second memory.

Abstract: An apparatus, system, and method are disclosed for non-interruptively updating firmware on a redundant hardware controller. The apparatus includes a routing module, a receiving module, and a forwarding module. The routing module routes communications between a redundant hardware controller and a service processor associated with a flash update. The receiving module receives a flash command for the flash update from the service processor via a shared serial connection. The forwarding module forwards the flash command via a dedicated point to point connection to the redundant hardware controller configured to receive the flash command over the point to point connection. The apparatus, system, and method provide a non-interruptive overlay of the firmware image on a redundant hardware controller, minimizing system downtime and user intervention.

Abstract: Exemplary embodiments are directed to a system and method for maintaining continuous operation applications in spite of hardware faults, maintenance, or replacement. The system having at least two physically redundant controllers, each controller being configured to achieve at least one of high availability and functional safety and having at least one control unit which actively participates in a control loop, and n redundant units that are kept synchronized in a stand-by mode. The at least two controllers are configured such that software code recorded on a first of the at least two controllers is replicated among others of the at least two controllers. Moreover, each of the at least two controllers include central processing units (CPUs) has a plurality of cores arranged within a single piece of silicon.

Abstract: An information processing apparatus includes a degeneration control unit and a re-synchronization processing instructing unit. The degeneration control unit degenerates, of a first controller group including a first controller and a second controller group including a second controller, the second control device group when the first and second controller performing a synchronization operation with each other detect occurrence of errors. The re-synchronization processing instructing unit instructs a controller included in the first controller group to execute re-synchronization processing. When another controller different from the first controller receives the instruction for the execution of the re-synchronization processing, the another controller performs interrupt mask setting.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, synchronizing records in peer devices. In one aspect, a method includes comparing, in a first peer device, a peer record received from a second peer device based on an IP address of the peer record from the second peer device and an IP address of a record stored in a host table of the first peer device. Unique agent identifiers, MAC addresses and time stamps are also compared to determine whether the peer record indicates a new host device, a new IP assignment to a known host device, or a new user logged into a known host device.

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.

Abstract: In a method and a device for securely checking the exclusivity of a binary active/passive state of redundant units, the device includes: at least one exclusive communication device of the state capable of transmitting an exclusive signal relating to the exclusivity of the state to at least one checking device integrated within each of the units. The checking device is capable of checking and confirming the exclusivity of the state. Each of said redundant units in the active state is capable of transmitting to the exclusive communication device the identity signal; the exclusive communication device is capable of receiving at least one of the identity signals from the redundant units; the exclusive communication signal is capable of producing the exclusive signal from at least one of the identity signals; and the checking device is capable of determining the exclusivity of the state of the unit by reading the exclusive signal.

Abstract: A failure diagnostic system (100) for a multicore CPU having installed therein a plurality of CPU cores (11) that is configured to be switched from a SMP mode to an AMP mode includes: load prediction means for predicting a processing load of the multicore CPU; mode switching means for switching at least one of the CPU cores (11) to the AMP mode when the processing load is less than a threshold; and failure diagnostic means for performing a failure diagnosis of the CPU core that has been switched to the AMP mode.

Abstract: Primary and secondary virtual machines each executing on a separate physical host and forming a fault-tolerant pair synchronize their execution with each other as closely as possible such that the secondary can take over execution of the primary with little or no disruption of service and no loss of data. To provide fast takeover, the execution latency between the two virtual machines is kept to a minimum by incrementally adjusting the CPU allocation to the primary virtual machine. The CPU allocation to the primary virtual machine decreases when the execution latency is large and increases when the execution latency is small. In order to maximize the performance of the primary virtual machine, the system seeks to maximize the CPU resource limit for the primary virtual machine for as long as possible while minimizing the execution latency.

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract: A data programming circuit is provided. The data programming circuit includes a one-time-programmable (OTP) memory and a control unit. The control unit stores a plurality of sections of a read-only memory (ROM) code into a free space of the OTP memory. In response to the sections of the plurality of sections that have the same content, the control unit stores a specific address into the OTP memory.

Abstract: A blade server is capable of being mounted with a plurality of operation blades, a plurality of switch blades, and I/O blades. The operation blades have CPUs that emit packets for the I/O blades. The switch blades include a crossbar that selects two or more of the plurality of operation blades, comparators that compare two or more packets emitted by CPUs that the two or more operation blades selected by the crossbar are provided with, and a further crossbar that transfers the compared packets to the I/O blades based on comparison results of the comparators.

Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: A method including requesting access to a resource governed by a spinlock; determining an allocation of the resource to a further requester; determining an expiration of a time limit for the spinlock, if the resource is allocated to the further requester; and initiating a fault recovery, if the time limit is expired.

Abstract: Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary and a secondary replica for an instance, with each capable of residing in a separate data zone or geographic location to provide a level of reliability and availability. A database running on the primary instance can have information synchronously replicated to the secondary replica at a block level, such that the primary and secondary replicas are in sync. In the event that the monitoring component is not able to communicate with one of the replicas, the monitoring component can attempt to determine whether those replicas can communicate with each other, as well as whether the replicas have the same data generation version. Depending on the state information, the monitoring component can automatically perform a recovery operation, such as to failover to the secondary replica or perform secondary replica recovery.

Abstract: The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.

Abstract: A safety output includes an output controller to make an instruction to output normal output data and first self-diagnosis pattern data synchronously with a control cycle, a normal output unit to output the normal output data synchronously with the control cycle, a test pattern generating unit to encode the self-diagnosis pattern data into a pulse train signal having a pulse width not larger than a preset value and output the pulse train signal in accordance with a baseband transmission system, a combination output unit to combine the pulse train signal with the normal output signal and output the resultant signal, a reconfiguration unit to decode the inputted operation-terminal-portion output signal to reconfigure the operation-terminal-portion output signal as second self-diagnosis pattern data, and a comparator to compare the first self-diagnosis pattern data with the second self-diagnosis pattern data to judge the presence or absence of a difference.

Abstract: A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads.

Abstract: An embodiment of a method for a high-assurance operation is disclosed. For this embodiment of the method, a first processor and a second processor are clocked for lockstep operation. A first physical address and a first transaction request are provided to a shared bus from the first processor. A second physical address and a second transaction request are provided to the shared bus from the second processor. The first physical address, the first transaction request, the second physical address, and the second transaction request are passed to a proxy device coupled to the shared bus. The first processor and the second processor are proxy served by the proxy device including generation of a third transaction request and a third physical address by the proxy device.

Abstract: Systems and methods for fine symbol timing estimation are disclosed herein. In one embodiment, a wireless receiver includes a differential detector, a correlator, a coarse symbol timing estimator, and a fine symbol timing estimator. The differential detector is configured to detect phase differences in a received preamble signal modulated using differential phase shift keying. The correlator is configured to correlate symbol values output by the differential detector against a reference sequence. The coarse symbol timing estimator is configured to generate a coarse symbol timing estimate, and to generate a coarse timing sample symbol index value corresponding to the coarse symbol timing estimate. The fine symbol timing estimator is configured to generate a fine symbol timing estimate that is more accurate than the coarse symbol timing estimate based on the coarse timing sample symbol index value and correlation samples at index values preceding and succeeding the coarse timing sample index value.

Abstract: A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.

Abstract: A node in a server cluster is designated as a quorum disk. The node stores a list of other nodes in the server cluster also designated as quorum disks. The node can replace the first list with a second and more recent list of quorum disks only if the second list is updated on at least a simple majority of quorum disks on the first list.

Abstract: Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.

Abstract: An aspect of the present invention mitigates reduction in availability level during maintenance of nodes in a cluster. In one embodiment, on receiving an indication that a maintenance activity is to be performed on the cluster, a scaling out of the cluster is first performed to add some nodes having the maintenance activity already performed, followed by a scaling in of the cluster to remove some of the nodes in the cluster which do not yet have the maintenance activity performed. The scaling out is performed before any scaling in of the cluster such that the number of nodes available in the cluster after the scaling in is not less than the number of nodes in the cluster at the time of receiving the indication. Accordingly, the reduction in availability level (which is based on the number of nodes available) is mitigated.

Abstract: Methods and apparatus to provide core sparing on multi-core platforms are described. In an embodiment, stored core state information of a target core (e.g., a core that has detected a fault condition (e.g., within its circuitry) or a request to offload operations from the target core (e.g., to enable run-time diagnostics without interfering with system software)) may be read by a spare core which is to operationally replace the target core. Other embodiments are also described.

Abstract: A high speed data processing system is described comprising first and second data processing modules and first and second data checking modules. The first and second data processing modules are each arranged to perform substantially the same processing steps on data received at said data input, with each providing an output. The first and second checking modules are arranged to compare the outputs of said first and second data processing modules and to output an error signal indicative of whether or not said first and second data processing modules have performed substantially the same processing steps. The first and second checking modules are located on physically separate devices. In some arrangements a third checking module is provided, which checking module may be physically separated from each of said first and second checking modules.

Abstract: A computer usable program product for accelerating recovery in an MPI environment is provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.

Abstract: The present invention relates generally to process control systems and devices and, more particularly, to an apparatus for and a method of implementing redundant controller synchronization for bump-less failover during normal and mismatch conditions at the redundant controllers. The redundant controllers are configured to transmit state information of the process control areas of the primary controller to the backup controller that is necessary for synchronizing the redundant controllers but is not typically transmitted to other devices during the performance of process control functions. Synchronization messages are transmitted from the primary controller to the backup controller each time one of the control areas executes to perform process control functions.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: Packet switch operating methods and packet switches, using primary control circuitry of the packet switch, receive a request to perform a transaction. In response to the receiving the request, the primary control circuitry forwards the request to backup control circuitry of the packet switch. Subsequent to forwarding the request, the primary control circuitry performs the transaction by modifying a plurality of first data objects stored in a memory of the primary control circuitry. The packet switch operating methods and packet switches, using the primary control circuitry, inform the backup control circuitry that the primary control circuitry has performed the transaction and, in response to the informing, the backup control circuitry performs the transaction by modifying a plurality of second data objects stored in a memory of the backup control circuitry. The first data objects correspond to the second data objects.

Abstract: There is provided a signal processing apparatus includes a sampling clock generator for generating a sampling clock by delaying, a phase of a driving clock having the same frequency as a carrier-wave; a logic data generator for generating logic data in synchronization with the driving clock, that the logic data are generated by using the driving clock generated to sample a modulation signal obtained by shifting a phase of the carrier-wave; a sampling bit-string generator for generating a sampling bit-string by shifting the logic data; a phase-error data generator for using a bit-string corresponding to one cycle of the carrier-wave extracted from the sampling bit-string to generate phase-error data between a phase of the bit-string and the phase of the carrier-wave; and an extraction position determination unit for determining, based on the phase-error data, an extraction position of the bit-string having a phase similar that of the carrier-wave.

Abstract: In a computer system in which a server has, in addition to a disk used for booting, an operation transfer destination disk that has the same content as the boot disk, a method for changing the disk used by the server or another server in the computer system for booting to the operation transfer destination disk is realized by changing the content of the operation transfer destination disk to enable the OS and applications installed in the operation transfer destination disk to be booted from the destination disk and by changing the setting of a boot program of the server to enable booting from the operation transfer destination disk.

Abstract: An application server system includes a main server and one or more clients controlled by the main server. The clients execute one or more applications in one or more virtual client environments. Each virtual client environment includes a lightweight server operable to instantiate one or more application objects in response to receiving configuration information from the main server. The application objects are each associated with an application being executed at the client. The application objects store operating information related to the associated application. The lightweight server is further operable to receive operating information from the application objects relating to the operation of the associated applications and to communicate the received information to the main server.

Abstract: “DECENTRALIZED SYSTEM AND ARCHITECTURE FOR REMOTE REAL TIME MONITORING OF POWER TRANSFORMERS, REACTORS, CIRCUIT BREAKERS, INSTRUMENT TRANSFORMERS, DISCONNECT SWITCHES AND SIMILAR HIGH VOLTAGE EQUIPMENT FOR POWER PLANTS AND ELECTRIC POWER SUBSTATIONS”, remarkably consisting of intelligent sensors of the IED type that make concerning measurements in the high voltage equipment, interconnected through a communication network to a monitoring central computer, allowing user's remote access to the measurements and diagnosis of the equipment condition as well as emitting automatic alarms should any abnormality appear in it.

Abstract: A method and apparatus is described for parallel debugging on the data nodes of a parallel computer system. A data template associated with the debugger can be used as a reference to the common data on the nodes. The application or data contained on the compute nodes diverges from the data template at the service node during the course of program execution, so that pieces of the data are different at each of the nodes at some time of interest. For debugging, the compute nodes search their own memory image for checksum matches with the template and produces new data blocks with checksums that didn't exist in the data template, and a template of references to the original data blocks in the template. Examples herein include an application of the rsync protocol, compression and network broadcast to improve debugging in a massively parallel computer environment.

Abstract: An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state.

Abstract: A system, method, and computer readable medium for reliable messaging between two or more servers. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. The reliable messaging ensures consistent ordered delivery of messages in the event that messages are lost; arrive out of order, or in duplicate. The messaging layer operates over TCP or UDP with our without multi-cast and broad-cast and requires no modification to applications, operating system or libraries.

Abstract: One embodiment described herein is directed to a method practiced in a computing environment. The method includes acts for determining test suite effectiveness for testing for concurrency problems and/or product faults. The method includes identifying a plurality of synchronization primitives in a section of implementation source code. One or more of the synchronization primitives are iteratively modified and a same test suite is run for each iteration. For each iteration, a determination is made whether or not the test suite returns an error as a result of modifying one or more synchronization primitives. When the test suite does not return an error, the method includes providing to a user an indication which indicates at least one of a test adequacy hole for the test suite; an implementation source code fault; or an equivalent mutant of the implementation source code.

Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal.

Abstract: A non-disruptive method for updating firmware in a first controller 210 of a redundant controller 200 in a storage subsystem 120 is disclosed. This updating occurs while the storage subsystem 120 presents data to a host system 130 in response to a host request 132. During the non-disruptive updating, the updating first controller 210 redirects the host request 132 for data, e.g., drive-A volume 252 normally owned by the first controller 210, to second controller 220 of the redundant controller 200. After the second controller 220 obtains data 134 identified in the host request 132, the operating second controller 220 transfers the data 134 to the updating first controller 210 via an inter-controller channel 202. Once the updating first controller 210 receives the data 134, the first controller 210 presents the data 134 to the host system 130. The host system 130 does not detect that the first controller 210 is updating because the updating process is invisible to the host system 130.

Abstract: A method and system for accelerating recovery in an MPI environment are provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.

Abstract: A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.