Abstract: A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for sending test signals to the input interface and receiving feedback signals from the output interface for facilitating locating and recording errors during testing of the computer. A testing method for testing the computer is also disclosed.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: According to some embodiments, a first bus may be monitored, via a first debug gate, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, via a second debug gate, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Abstract: Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the code address bus. The memory comprises a plurality of memory locations, each of the memory locations mapped to a particular one of a corresponding plurality of addresses associated with the firmware. The contents of the memory location associated with the address received from the code address bus being incremented responsive to receipt of the address.

Abstract: A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: A data processing apparatus having a memory for storing program code and a processor for processing the program code, the data processing apparatus comprising: a radio module to communicatively couple the data processing apparatus to a wireless network, the radio module generating a plurality of debug data in a plurality of signal classes; a set of debug data filtering rules specifying certain debug data within the plurality of signal classes to be collected from the radio module; and a debug application executed on the data processing apparatus, the debug application to apply the set of filtering rules, thereby causing only the specified set of debug data to be collected from the radio module.

Abstract: An apparatus for changing a connection between two serial components on the same circuit board. The apparatus comprises at least one column, and each column includes first, second, third and fourth pads. The first pad communicates with a first breakout connector disposed on the circuit board. The second pad communicates with a second breakout connector disposed on the circuit board. The third pad communicates with one of the serial components. The fourth pad communicates with the other of the serial components and with the third pad during normal operation.

Abstract: A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.

Abstract: A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.

Abstract: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

Abstract: An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output module. The BIOS is used for generating a POST code. The POST code is transmitted via a low pin count (LPC) interface. The conversion module receives the POST code and converts the POST code into a system management bus (SMBus) format. The output module is used for receiving and outputting the POST code transmitted by the conversion module. The output module is an SMBus interface.

Abstract: A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing block. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.

Abstract: Systems and methods for updating at least one field replaceable unit (FRU) are disclosed. In an exemplary embodiment the method may comprise generating a virtual image of a FRU ID for each FRU to be updated. The method may also comprise storing the virtual image separate from the FRU ID. The method may also comprise providing a handle to the virtual image so that updated information is retrieved from the virtual image when the FRU is accessed.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method is provided wherein a lithographic projection apparatus is used to print a series of test patterns on a test substrate to measure printed critical dimension as function of exposure dose setting and focus setting. A full-substrate analysis of measured critical dimension data is modeled by a response model of critical dimension. The response model includes an additive term which expresses a spatial variability of the response with respect to the surface of the test substrate. The method further includes fitting the model by fitting model parameters using measured critical dimension data, and controlling critical dimension using the fitted model.

Abstract: A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ignored, and activating a second defeature in the component to prevent messages from being sent over the communication bus by the component. Operations may then be performed on the component while the defeatures are activated.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: A computer-executable method for analyzing a condition of a computer system comprises executing an operating system on a processor according to an operating system image resident in a memory, and executing an analysis engine independently of the operating system on the processor in co-existence with the operating system. The analysis engine is enabled complete access to information relating to the processor and the operating system. The operating system is prevented access to the analysis engine.

Abstract: The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

Abstract: Systems and methods for testing a peripheral in accordance with a MIPI protocol are provided. A test system can test a peripheral by providing user-specified control over a test processor (which is substantially the same processor the peripheral will interface with when installed) to test, calibrate, or both test and calibrate the peripheral. The test processor can communicate with the peripheral according to the MIPI protocol, thereby effectively providing an actual “in-device” environment for testing and/or calibrating the peripheral.

Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.

Abstract: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Abstract: In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a predetermined program. Responsive to the mode judgment signal, a monitoring signal is generated indicative of an attempt by the CPU to execute the predetermined program during the debugging preparation. Furthermore, a transfer of an instruction code corresponding to the predetermined program is controlled so that the CPU is prevented from executing the predetermined program during the debugging preparation, responsive to the monitoring signal. Alternatively, in the debugging circuit and the method, instead of controlling the transfer of the instruction code responsive to the monitoring signal, another instruction code may be transferred to the CPU, responsive to the mode judgment signal. The another instruction code prevents the CPU from executing the predetermined program during the debugging preparation.

Abstract: In a mobile device having a primary baseband circuit and a secondary baseband circuit and an interface between the primary baseband circuit and a secondary baseband circuit, a method for testing the interface and primary and secondary baseband circuits comprising the steps of: setting the secondary baseband circuit into a loopback mode; sending a test signal from the primary baseband circuit to the secondary baseband circuit; receiving at the primary baseband circuit a second signal, the second signal being the first signal looped back from the secondary baseband circuit; and comparing the second signal with an expected result.

Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.

Abstract: A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.

Abstract: Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

Abstract: A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test.

Abstract: A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Abstract: A transmission apparatus has a main signal processing device, a monitor control part and an intermediating part to intermediate addresses and data between the monitor control part and the main signal processing device. The transmission apparatus further has a first switching part to selectively supply the address or the address and the data output from the intermediating part to the main signal processing device in the normal operation mode, and to selectively supply the address or the address and the data output from the monitor control part to the main signal processing device in the debug mode, and a second selecting part to selectively supply the data output from the intermediating part to the monitor control part in the normal operation mode, and to selectively supply the data output from the main signal processing device to the monitor control part in the debug mode.

Abstract: A debug network on a multiprocessor array includes communication channels, a master controller, and one or more individual debug units in communication with one or more of the processors. The master controller solicits information from the debug units by sending messages along the communication channels. The debug units can control some aspects of the processors, and can simply report on other aspects. By using commands to invoke processor action, then accessing the result, interactive debugging of a multiprocessor array is possible.

Abstract: In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is connected to the circuit subunits by means of a connecting unit, test signals are generated for the electric circuit and response signals generated by the electric circuit in response to the test signals are evaluated. The test signals and the response signals are interchanged between the circuit subunits by means of at least one compression/decompression unit associated with at least one of the circuit subunits.

Abstract: A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.

Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them. In practice, the BISD device may diagnose memory arrays and allow the identification of defects in the production process that affect a new technology during its learning phase, thus accelerating its maturation.

Abstract: A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.

Abstract: A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: Methods, apparatus, and products are disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

Abstract: An optical disc apparatus capable of performing self-diagnosis receives from a host computer a command to enable a self-diagnostic mode. Information indicating that the self-diagnosis mode is specified is written to a ROM in the optical disc apparatus. Product inspection is performed while the optical disc apparatus is not connected to the host PC. The optical disc apparatus checks whether the information has been written to the ROM. When the information is written to the ROM, the optical disc apparatus performs self-diagnosis mode inspection. When the optical disc apparatus is connected to the host PC to allow for the establishment of communications by use of an out-of-band signal, the information written to the ROM is erased on the assumption that the connection has been established. This eliminates an unnecessary command and prevents a malfunction caused by the self-diagnostic mode in a destination site.

Abstract: An integrated circuit device having a plurality of embedded processor/controllers and a parallel emulation trace port coupled thereto to provide trace data for debugging the integrated circuit device. A serializer macro is provided within the integrated circuit device to serialize the parallel data from the emulation trace port in order to provide trace data from the IC device in a serial data stream instead of a parallel data stream. A high speed differential serial driver is used to provide the bandwidth required to support the data speeds associated with embedded processors running at high clock rates. An external serial to parallel converter is also provided to convert the high speed serial trace data back to parallel trace data such that the trace data can be input into an emulator in the normal manner. In one embodiment, two serializers are provided within the integrated circuit device to meet data throughput requirements, such as when the IC device has more than one embedded processor/controller.

Abstract: An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and debugging on the IC, and generates testing results based on the at least one of the testing and the debugging. A serializer located on the IC receives the testing results from at least one of the embedded ICE and the embedded processor, serializes the testing results, and serially outputs the testing results from the IC.

Abstract: A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.