Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and configuration latches during reset state that links the logic elements and interconnect structure to form a complete path between the interface points of the programmable logic device to enable testing of the desired elements in the complete path.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Abstract: A method and system for quickly informing a backup unit that a primary unit has failed. Normally an exception handler is activated when a software failure occurs and network controller chips or the ASIC interface to a signal bus can operate even though there is a software failure. A software failure notification packet is programmed and stored in a location that is not affected by a software system failure. When a software failure occurs, control is shifted to the exception handler. The exception handler sends a pre-established and pre-addressed packet to the network controller card which transmits this packet to the backup unit. Upon receipt of the packet, the backup unit goes into operation. In some alternate embodiments that include multiple line cards in a single unit, the exception handler sends a signal to a backup unit via a signal bus or a data bus.

Abstract: A system performance profiling device is provided inside a system-on-chip (SoC). Selectors respectively select values of predetermined bit positions of counters and output the selected values to the outside of the system-on-chip, during a period of acquisition of profiling data. When the acquisition of the profiling data ends, the selectors respectively select values of all lower bit positions of the counters than the predetermined bit positions, and output the selected values to the outside of the system-on-chip.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: A data displacement bypass system is disclosed, wherein the data displacement bypass system comprises a CPU (Central Processing Unit), a first memory, a plurality of address lines, a plurality of data lines, an OE (Output Enable) line, a CS (Chip Select) line and a data displacement unit. The CPU could output a plurality of address characters, an OE signal and a CS signal, and receive a plurality of data characters. The first memory and the data displacement unit could output the plurality of data characters according to the plurality of address characters, the OE signal and the CS signal received by the first memory and the data displacement unit, wherein the data displacement unit could govern the plurality of data characters inputting to the CPU by outputting high or low voltage.

Abstract: The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the main memory and execute the debugging program. After execution, an execution result of the debugging program is stored into the main memory. The execution result is read and output via the debugging interface for further analysis. Because the architecture does not require a scan chain of ITR 104, the circuit requirement is reduced while performance is increased.

Abstract: A method, system, computer system and computer program product to remotely diagnose a problem with a computer system or related equipment using data provided by a user of the computer system via telephone. A signal including speech and/or DTMF tones is received via a telephone channel from a user of the computer system or equipment. The computer system and/or equipment associated with the signal is identified using information from the signal, such as a user name, caller ID, telephone number, or password. A source of diagnostic information about the computer system is identified, and diagnostic information is gathered from the source. The diagnostic information can be used to fix the problem or provided to a customer service agent for use in further problem diagnosis.

Abstract: A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing mode of the MCBIST command. Sequential addresses are generated and modified in response to the addressing mode being a stress test mode. The modifying includes swapping bits in a sequential address with other bits in the sequential address to target selected portions of a memory. The modified sequential addresses are output to the memory to be utilized in a MCBIST stress test of the memory.

Abstract: The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation.

Abstract: A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.

Abstract: Control commands are transmitted via an emulation interface holding a test clock signal at a constant value and switching a test mode select signal a number of times corresponding to the control command. A receiving system counts switches of the test mode select signal switches while the test clock is constant and interprets the number of switches as a corresponding control command.

Abstract: A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specific processor core to which control having a higher priority order than control to be allocated to processor cores other than the specific processor core is allocated. When the monitoring processor detects the abnormal operation in the specific processor core, the monitoring processor allocates the control having the higher priority order to one of the processor cores other than the specific processor core.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.

Abstract: A semiconductor integrated circuit is configured to test a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: Embodiments of the present invention include methods of one-key test function in a Control Console in a network device. In one embodiment, the present invention includes a console controller, a display module and an input module with a test-key on a network device so that a user can test status, operation or management at a network device with a single touch of a button. In another embodiment, the present invention includes remote activation of one key test function from a remote test module. In another embodiment, the present invention includes password authentication or user approval of remote activation of one key test function.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract: A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract: There is provided a method of communicating diagnostic information between a Universal Serial Bus (USB) host and a USB device, the USB host including a host USB controller, a main driver and a host main application. The method comprises establishing a data pipe in a data class interface between the USB host and the USB device for data communication; establishing a diagnostic information pipe in the data class interface between the USB host and the USB device for diagnostic information communication; monitoring the data class interface between the host USB controller and the main driver using a filter driver; intercepting the diagnostic information in the diagnostic information pipe of the data class interface using the filter driver; directing the diagnostic information intercepted by the filter driver to a host diagnostics application; and directing the data in the data pipe of the data class interface to the main driver.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.

Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

Abstract: A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.

Abstract: Methods and systems for memory monitoring. A triggering access is detected at one or more monitored memory regions. When a triggering access is detected, a function is accessed for determining a monitoring function, and a monitoring function associated with a particular triggered memory location address is automatically determined.

Abstract: A test circuit arrangement for testing latch units is provided which includes a) a voltage generator configured to adjust a voltage potential difference between a first ground line and a second ground line of the latch units and/or to adjust a voltage potential difference between a first supply voltage line and a second supply voltage line of the latch units; b) combiner configured to combine logical outputs of the latch units; and c) determiner configured to determine the voltage potential difference between the first ground line and the second ground line and/or the voltage potential difference between the first supply voltage line and the second supply voltage line in a state when all of the latch units have identical logical outputs.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: A method, apparatus and program storage device for protecting data write operations against write failures in a data storage device is provided. The data storage device includes a storage medium, a write cache including a copy of data written to the storage medium, and a controller configured for testing data write operations to the storage medium. The controller tests data write operations to the storage medium before the write cache is flushed to confirm that it is safe to flush the write cache. If the test fails, the data in the write cache can be recovered.

Abstract: A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells.

Abstract: A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board.

Abstract: A system on chip processor, that is, a semiconductor integrated circuit in which a processor, a cache memory and the like are integrated into one chip, includes a test controller, and a trace memory. The test controller generates test control signals in response to test flag signals generated from a processor. The trace memory stores a transmission data signal between the processor and a cache memory, a device under test, in response to the test control signals. Since the trace memory is provided within the integrated circuit, an operation of the device under test, which is configured in the integrated circuit, can be tested without disassembling the integrated circuit even after the integrated circuit is completely manufactured.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.

Abstract: A mechanism is provided for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is used that holds the programming information for each eFuse. This latch allows for programming only a portion of eFuses during each stage of testing. Moreover, the data programmed in the eFuses can be sensed and read as part of a scan chain. Thus, it can be easily determined what portions of the bank of eFuses have already been programmed by a previous stage of testing and where to start programming the next set of data into the bank of eFuses. As a result, the single bank of eFuses stores multiple sets of data from a plurality of test stages.

Abstract: A symbolic disjunctive image computation method for software models which exploits a number of characteristics unique to software models. More particularly, and according to our inventive method, the entire software model is decomposed into a disjunctive set of submodules and a separate set of transition relations are constructed. An image/reachability analysis is performed wherein an original image computation is divided into a set of image computation steps that may be performed on individual submodules, independently from any others. Advantageously, our inventive method exploits variable locality during the decomposition of the original model into the submodules. By formulating this decomposition as a multi-way hypergraph partition problem, we advantageously produce a small set of submodules while simultaneously minimizing the number of live variable in each individual submodule.

Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.

Abstract: A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

Abstract: A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a testing device is connectable to the terminal. The input/output cell has a switching part that is capable of switching between a first path that loops back at an output side of the output-stage buffer and a second path that loops back at an input side of the output-stage buffer. The first path is selected during normal operation and the second path is selected during the propagation delay testing.

Abstract: A boundary-scan circuit method and apparatus for asserting an internal reset signal connected to core logic circuits of an electronic device in order to assure that testing will begin and end in a safe, known logic state. A safe end state is assured even if the system reset signal on an input pin of the electronic device is logically disconnected from the internal reset connection to the core logic, as often occurs in boundary-scan and related testing.