Abstract: A scan element with self scan-mode toggle is described. In an example, the scan element is configured to automatically switch between a capture mode and a scan mode. In the capture mode, data is captured from logic under test. In the scan mode, the captured data is scanned out for testing. The scan elements each include a shift register that serves a dual purpose of providing control for determining when the scan element is to switch from the capture mode and the scan mode, as well as providing a location to store captured data.

Abstract: A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.

Abstract: A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.

Abstract: This invention relates to automatically establishing a connection between a testing and/or debugging interface to an integrated circuit and a connector of an apparatus, the connector being connectable to a testing and/or debugging apparatus configured to communicate with the testing and/or debugging interface via the connector in a testing and/or debugging mode of the apparatus and connectable to an accessory apparatus to be used in a normal operation mode of the apparatus, if the testing and/or debugging apparatus is connected to the connector, thereby establishing the testing and/or debugging mode of the apparatus.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

Abstract: A method is described that involves within a link based computing system, opportunistically transmitting, into a network utilized by components of the link based computing system, one or more packets that contain computing system state information. The computing system state information includes software state information created through execution of software by said link based computing system. The method also involves collecting the computing system state information at a monitoring and/or debugging system attached to the link based computing system in order to analyze the link based computing system's operation.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: A method and system are disclosed to quickly and inexpensively (in terms of computational overhead) detect when a data shift corruption event or a short read has occurred and to transparently retry the failed read operation. The method seeds the memory read buffer, into which read data will be written, by placing known values (a “seed pattern”) at the end of the buffer prior to initiating the read operation. If the seed pattern is still in the read buffer when the read operation completes, the read operation has encountered a data shift corruption event and should be retried. If the read operation completes correctly, the seed pattern will be overwritten by the data read from the disk. The particular seed pattern used and the size of the seed pattern are chosen to be discriminating (i.e., no false positives) and cheap to write and verify (i.e., no performance impact).

Abstract: It is possible to suppress a CPU showing signs of unstable operation before the OS starts. A micro program acquires error CPU information (which cannot be recognized directly by the micro program) from the service processor immediately before the termination of the micro program and making a request for suppression of the CPU showing signs of unstable operation according to the acquired error CPU information. The service processor suppresses the CPU showing signs of unstable operation before the OS starts.

Abstract: Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.

Abstract: This invention relates to a method, an apparatus, an electronic device, a system, and a computer program product for selecting at least one component out of at least one maintenance component and at least one non-maintenance component, wherein said at least one maintenance component and said at least one non-maintenance component represent electronic components arranged in an apparatus; and switching an external connector of said apparatus to said at least one selected component.

Abstract: Efficient performance monitoring for symmetric multi-threading systems is applicable to systems that have limited performance monitoring resources and enables efficient resource sharing on a per-execution unit basis. The performance monitoring unit being shared is programmed to reset its counter and to start performance monitoring operation if there is only one execution unit requesting this operation. In case there are several requests pending, an attempt is made to program the performance monitoring unit to collect performance data for a subset of execution units the hardware is capable to support. Upon a request to stop performance monitoring operation the previously allocated indicator may be removed, and the performance monitoring unit may be programmed to stop operating if there are no more active or pending requests. In case the performance monitoring was inactive for the current execution unit, this request may be discarded, and no performance data may be returned.

Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

Abstract: A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.

Abstract: A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a semiconductor substrate. Elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. Each SSA includes a local defect memory and a self-test mechanism. The self-test mechanism periodically tests the SSA and its interconnects, and stores resulting defect information into its local defect memory. The computer is configured to realize a user design and then is run. A defect is then detected. If the defect is determined to be in a part of the computer used in the realization of user design, then the computer is reconfigured not to use the defective part and running of the computer is resumed, otherwise the computer resumes running without reconfiguration.

Abstract: A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Abstract: A method for testing a circuit for a transponder, and transponder circuit, is provided, in which the circuit is operated in a passive mode in that the circuit is supplied with energy from a field, in which, during the passive mode, the circuit receives a command via the field to activate a test routine, in which memory content is stored by the test routine as test data in a memory area of a memory of the circuit predetermined by the test routine, in which, during the passive mode, the test data are transmitted via the field.

Abstract: A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.

Abstract: An electronic system comprises a processor, a diagnostic port, and a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port. A method for operating the electronic system is also included.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: Disclosed is a full error description for a technical system which is described by a system description which can be processed by a computer and stored. The system description contains information on elements available in system and information on the links therebetween. An element error description is determined for each element taken into consideration, using a stored error description which is respectively associated with a reference element. At least one part of the reference elements is grouped into a reference element group and a group error description is determined for the reference elements of a reference element group using a stored group error description which is respectively associated with a reference element group, enabling possible errors of the reference elements of the reference element group to be described. A full error description is determined from the element error descriptions and the group error descriptions, taking into account information on element links.

Abstract: In one embodiment, a debugger for a hardware-implemented operating system that supports one or more processors includes a host debug and a user interface. The host debug is operable to connect to a kernel processing unit of the hardware-implemented operating system via a test interface such as a Joint Test Access Group (JTAG) interface, to request information concerning internal objects of the kernel processing unit during the operation of the processors, and to receive the requested information without disturbing the operation of the processors. The user interface is then used to present the requested information to the user. In one embodiment, the debugger further includes a target resident debug server that is scheduled by the kernel processing unit to execute debugging commands issued by the host debug (e.g., a command to collect information resident in the processor's data space, a command to set a breakpoint, a command to respond to a breakpoint, etc.).

Abstract: Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

Abstract: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit.

Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. In one or more embodiments, the test module can include a linear-feedback shift register.

Abstract: A device includes a first test port coupled to a first test device, a second test port coupled to a second test device, a resource, and a security controller coupled to the first and second test ports. The security controller is operable to authenticate the first test device prior to authenticating the second test device, and, in response to authenticating the first test device, permit the first and second test devices to access the first resource.

Abstract: An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.

Abstract: A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active.

Abstract: An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.

Abstract: A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within the attached processor, which operate at the speed of the processor. A master controller solicits information from the information nodes by sending messages along the backbone. If a message requires interaction with a processor register, the node performs the action by synchronizing to the local processor clock.

Abstract: Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of serial ports needed for data transfer is significantly less than a complimentary parallel port configuration. Additional functional blocks on the chip process the data for high speed serial output. The functional blocks format information into subchannels, arbitrate data, append protocol, perform data integrity checks, and serialize the data. The additional blocks built on the chip to support the serial ports consume less chip space than the space consumed by the number of parallel ports required to provide equivalent data transfer rates. The process operates in near real time and may use time stamping to correlate and reconstruct data from different information sources.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: A booster circuit is incorporated in a one-chip microcomputer. In a test mode, a burn-in test is performed by switching power supply systems so that a power supply voltage of 5V is supplied to a 3.3V-type circuit section that normally operates on a power supply voltage of 3.3V in an ordinary state and a boosted voltage of a 5V booster circuit is supplied to a 5V-type circuit section that normally operates on a power supply voltage of 5V in the ordinary state.

Abstract: A testing device for testing a motherboard is provided to include a server, a client terminal computer, a debug card and a receiving device. The server is connected to the client terminal computer, for inquiring test results. The debug card is attached to the motherboard, for getting test data. The receiving device connecting with the debug card transmits the test data to the server via a network. A testing method for testing a motherboard is provided to include the following steps: a debug card getting the test data from the motherboard; sending the test data to a receiving device, the receiving device transmitting the test data to a server, the server collating and analyzing the test data; and a client terminal computer inquiring test results via the server.

Abstract: The present invention relates to a device and method for expediting feedback on changes of connection status of monitoring equipments, comprising a CPU, a switch module and at least an optical fiber connector, wherein the CPU contains multiple reserved pins and is connected with the switch module, while the switch module is connected with at least one optical fiber connector, which includes signal detect pins that are used to connect with the switch module. The CPU is connected through one of the reserved pins with the SD pin of the optical fiber connector, and controlled by a system software to read the bit value of the signal address of the SD pin. This allows the system software to analyze and determine if the address value of the signals received by the reserved pin is changed or not, and to take action to respond when the connection status is changed.

Abstract: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output terminal. The flip-flop unit has a second input terminal coupled to the first output terminal, a clock signal input terminal for receiving a reference clock signal, and a second output terminal outputting an output data. The first buffer is coupled to the flip-flop unit to convert the output data to a high voltage data, and outputs the high voltage data. The second buffer is coupled to the first buffer to convert high voltage data to low voltage data and transmit the low voltage data to the feedback input terminal.

Abstract: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans.

Abstract: A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Abstract: A method, system and apparatus for ensuring that only randomly generated numbers that have passed a test is used for cryptographic purposes are provided. When a random number is generated, it undergoes a built-in self-test (BIST). If the number passes the test, it is forwarded to a cryptographic device to be used for cryptographic purposes. If the number does not pass the test, a signal is instead forwarded to the cryptographic device to indicate the failure of the test. In a particular embodiment, only one data line is used to forward either the randomly generated number or the signal. A selector is used to facilitate the selection between the number and the signal.

Abstract: A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.

Abstract: A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system. The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active.

Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.