Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 8549368
    Abstract: A multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. The first and second sets of processor cores include first and second memory blocks and corresponding first and second built-in-self-testing (BIST) engines of different architectures. A control circuit configures the first and second TAP controllers and the connection between the first and second sets of processor cores and the first and second debug ports, for initiating the first and second BIST engines for testing the memory blocks using a predetermined test mode. A debug access module provides secure access to the first and second debug ports.
    Type: Grant
    Filed: May 19, 2012
    Date of Patent: October 1, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amar Nath Deogharia, Ankush Srivastava
  • Patent number: 8543950
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: September 24, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
  • Patent number: 8543863
    Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 24, 2013
    Assignee: Microsoft Corporation
    Inventors: Engin Ipek, Thomas Moscibroda, Douglas C. Burger, Edmund B. Nightingale, Jeremy P. Condit
  • Patent number: 8539295
    Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8539293
    Abstract: An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heon-Hee Lee, Hoi Jin Lee
  • Publication number: 20130238933
    Abstract: There present invention relates to a multi-core System On Chip (SoC) having a debugging function. The multi-core SoC having a debugging function includes one or more processors each configured to include an On Core Debug (OCD); a bus matrix configured to connect buses between the one or more processors and one or more peripheral devices; and a debug interface configured to include Processor Debug Interfaces (PDIs) for communicating with the respective OCDs and a Bus Debug Interface (BDI) for communicating with the bus matrix. In accordance with the present invention, the function of a multi-core SoC which has become complicated as compared with the existing singe core SoC may be efficiently verified.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 12, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Electronics and Telecommunications Research Institute
  • Patent number: 8533543
    Abstract: In accordance with an aspect of the application, there is provided a system for testing, including a first chip, a second chip, and first and second connections. The first connection is configured to couple a first pin of the first chip to a first pin of the second chip, and to transmit an initial signal from the first chip to the second chip. The second connection is configured to couple a second pin of the first chip to a second pin of the second chip to return the signal as a returned signal to the first chip. The first chip comprises comparison circuitry configured to compare the returned signal with the initial signal.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Harry Siebert
  • Patent number: 8527812
    Abstract: The invented device includes a central processing unit(s), each CPU including an execution unit coupled to an operand bus and a control unit that controls operation of the execution unit, based on fetched instructions, and a debugging circuit that obtains trace data about how a program is executed in each CPU. The control unit includes a debugging function unit that collects instruction execution analysis data in the CPU. The debugging circuit includes a trace acquisition circuit(s) that imports instruction execution analysis data collected by the debugging function unit and data received from the operand bus via logic circuits used for separate purposes and a trace output circuit(s) for delivering outside the output of the trace acquisition circuit. In the trace acquisition circuit, a sorting logic unit is provided that sorts instruction execution analysis data collected by the debugging function unit and data received from the operand bus.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Shiina
  • Publication number: 20130227344
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: January 29, 2013
    Publication date: August 29, 2013
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 8522096
    Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 27, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Nur A. Touba, Michael S. Hsiao, Zhigang Jiang, Shianling Wu
  • Patent number: 8522081
    Abstract: When a CPU executes a failure detection program, the CPU causes a program counter expected value register to store an expected value of an address which is stored in a program counter after a detection time passes from the start of execution of the failure detection program, and causes a detection time counter to start counting of the detection time. When the detection time counter finishes counting of the detection time, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toshiyuki Igarashi
  • Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8516304
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefore. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: August 20, 2013
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Christopher Wilson Case, James Patrick Sharpe
  • Patent number: 8516305
    Abstract: Dynamic power test slave (DPTS) modules are placed at selected locations of a data processing device to provide data to a logic module of the device at a high rate during testing of the device. The DPTS module intercepts data requests targeted to another logic module and the DPTS instead provides the requested data, thus simulating data transfer by the target logic module. The simulated data transfers can provide for transitions at the data processing device from a relatively high power state to a relatively low power state. Accordingly, the DPTS modules allow for simulation of expected normal operating conditions during testing of the data processing device.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 20, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sebastien Nussbaum, Guhan Krishnan
  • Patent number: 8504875
    Abstract: A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: August 6, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ryuji Orita, Barry A. Kritt, Charles D. Bauman, Sumeet Kochar, Jeremy K. Holland, Karen A. Taylor
  • Publication number: 20130198566
    Abstract: A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a triggering event. The debug controller reads data from memory device and provides the debug mode information external to the SoC device. The memory may include a first memory block and a second memory block, which store debug mode information. The first memory block may store debug mode information, and the second memory block may store normal mode information. A corresponding method and computer-readable medium are also disclosed.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: LSI CORPORATION
    Inventors: Sachin Shivanand Bastimane, Hemang Rajnikant Desai
  • Patent number: 8489943
    Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Anil K. Dwivedi, Akhilesh Chandra, Ajay Arun Kulkarni
  • Patent number: 8473793
    Abstract: A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: June 25, 2013
    Assignee: Global Unichip Corporation
    Inventor: Min-Hsiu Tsai
  • Publication number: 20130159771
    Abstract: An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion includes a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventor: Navin Patel
  • Patent number: 8468394
    Abstract: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: June 18, 2013
    Assignee: ARM Limited
    Inventors: Daryl Wayne Bradley, John Michael Horley, Sheldon James Woodhouse
  • Patent number: 8468408
    Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 18, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei-Yu Chen, Kevin Badgett, Kay Hessee
  • Publication number: 20130151902
    Abstract: A debug system includes a debug device and a computer. The debug device includes an IIC reading and writing module, a first control module; and a signal receiving and transmitting module. The computer includes a second control module. The IIC reading and writing module is connected to an IIC device. The second control module sends an inputted command to the first control module via the signal receiving and transmitting module.
    Type: Application
    Filed: July 26, 2012
    Publication date: June 13, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: KANG-BIN WANG
  • Publication number: 20130151903
    Abstract: An image forming apparatus has a plurality of device modules for executing predetermined functions; and a control module for controlling operation of the device modules. The control module comprises an initialization section for establishing a link; a master data transfer section for transferring data to a device module; and a link checking section for checking the state of the link. When a request for data transfer to a first device module out of the plurality of device modules is made, the link checking section checks the state of the link between the control module and the first device module. When the state of the link checked is determined to be abnormal, the initialization section establishes the link between the control module and the first device module, and then the master data transfer section transfers the data requested to be transferred to the first device module.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 13, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: SHARP KABUSHIKI KAISHA
  • Publication number: 20130151901
    Abstract: This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 13, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gary L. Swoboda
  • Publication number: 20130151904
    Abstract: A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit.
    Type: Application
    Filed: February 6, 2013
    Publication date: June 13, 2013
    Applicant: Kingston Technology Corp.
    Inventors: Jerry N. Le, Ngoc V. Le, Tat Leung Lai, Ramon S. Co
  • Patent number: 8464100
    Abstract: A system for checking a program memory) of a processing unit includes a check module, and the processing unit is made up of an instruction counter connected to the check module. The check module has a register connected to a first changeover switch that sets the register content. In a system that allows for the instruction addresses of the entire program memory to be checked, the instruction counter contains an ancillary counter, which runs through the instruction address space of the program memory independently of the program code during normal operation and which is connected to the register.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: June 11, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Jo Pletinckx, Hongyu Wang, Axel Wenzler, Markus Brockmann
  • Patent number: 8458539
    Abstract: An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Daniel Skaba, Michael Israeli, Itai Samoelov, Julius Mandelblat
  • Patent number: 8458540
    Abstract: A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryoichi Inagawa
  • Publication number: 20130139002
    Abstract: A debugging method for a plurality of processor cores is disclosed, which includes defining a debug data transmitting zone in a storage device, utilizing a first processor core for generating a debug data and transmitting the debug data to a second processor core via the debug data transmitting zone for debugging.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 30, 2013
    Inventor: Wen-Cheng Huang
  • Publication number: 20130124920
    Abstract: A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Allon Adir, Dimtry Krestyashyn, Charles Meissner, Amir Nahir
  • Patent number: 8443246
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: May 14, 2013
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Patent number: 8443175
    Abstract: A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: May 14, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Jui-Shuan Chen
  • Patent number: 8438442
    Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: May 7, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Gary R. Morrison
  • Patent number: 8438439
    Abstract: An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 7, 2013
    Assignee: Actions Semiconductor Co., Ltd.
    Inventor: Wuhong Xie
  • Patent number: 8432178
    Abstract: A testing device for testing a board managing controller (BMC) of a computer motherboard including a power supply, a BMC, and a warning unit, includes a storing module, a voltage adjusting module, and a voltage displaying module. The storing module stores a preset warning voltage and an upper limit voltage larger than the preset warning voltage. The voltage adjusting module is used for adjusting the voltage of the power supply. The voltage displaying module is used for displaying the output voltage of the voltage adjusting module. It indicates the BMC works properly if the warning unit provides warning when the output voltage of the voltage adjusting module is less than the preset warning voltage, or the warning unit is silent when the output voltage of the voltage adjusting module falls between the preset warning voltage and the upper limit voltage.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 30, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Xian-Kui Chen, Hai-Li Wang
  • Patent number: 8423832
    Abstract: A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 16, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reid J. Riedlinger, Douglas John Cutter, Rich McGowen, II
  • Patent number: 8423841
    Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 16, 2013
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 8423844
    Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pamela S. Gillis, David E. Lackey, Steven F. Oakland, Jeffery H. Oppold
  • Patent number: 8421275
    Abstract: An apparatus is provided that includes first and second switches in line between an appliance and terminals of the appliance that are connectable to a power source. The first switched is configured to open and close based on closing and opening of a door of the appliance, and the second switch is configured to open and close based on the mode of the appliance. Thus, the appliance may be connected to the power source when the first switch or the second switch is closed, and disconnected from the power source when both the first switch and the second switch are open. The apparatus further includes a third switch connected to the second switch and configured to control the second switch to close upon actuation of the third switch by a user, where actuation of the third switch may cause the appliance to enter an operational mode.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: April 16, 2013
    Assignee: Electrolux Home Products, Inc.
    Inventors: Ken E. Sauter, John DeFilippi, Kyle T. Perkinson
  • Patent number: 8412983
    Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Limited
    Inventor: Keigo Nakatani
  • Patent number: 8412991
    Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. A method for identifying a reference scan cell is provided, the method including, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The method further includes, in a shift mod, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 2, 2013
    Assignee: Teseda Corporation
    Inventors: Rich Ackerman, John Raykowski
  • Patent number: 8406122
    Abstract: Mesh access point fault reporting. In particular implementations, a method includes receiving a fault indication indicating one or more failures; collecting fault data related to the one or more failures or a state of the mesh access point; and passing the fault data to the RFID tag, which wirelessly transmits messages relating to the fault.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: March 26, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Allan Thomson
  • Patent number: 8407522
    Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; and a control section that controls the plurality of test modules. Each test module includes a test section that tests the device under test; and a self-diagnostic section that diagnoses operation of the test section based on diagnostic data supplied thereto. The control section supplies the diagnostic data in parallel to self-diagnostic sections for which the same type of diagnostic data is set, and supplies the diagnostic data sequentially to self-diagnostic sections for which a different type of diagnostic data is set.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: March 26, 2013
    Assignee: Advantest Corporation
    Inventor: Koji Takahashi
  • Publication number: 20130073906
    Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.
    Type: Application
    Filed: December 30, 2011
    Publication date: March 21, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-TSANG HSIEH, YUNG-PO CHANG
  • Patent number: 8402446
    Abstract: A probe (hereinafter also referred to as a breakpoint) can be added into source code of an application program. The probe can be exported to a file or any other form of storage. The probe is then associated with a unique test case for the application program thereby creating a direct mapping between the application program and the test case for the application program. In one embodiment, the probe can be added to at least one of a function or module of the application program.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventor: Saurabh Singh
  • Patent number: 8402313
    Abstract: One disclosed system and method enables dynamic reconfiguration of an electronic device in association with testing activities in a convenient and efficient manner. In one implementation, the electronic device includes a bus for communicating information, a microprocessor for processing data, a programmable functional component including a plurality of functional blocks programmable to provide a plurality of functions and configurations, and a memory for storing instructions including instructions for causing the programmable functional component to change functions and configurations. The components are programmably configurable to perform a variety of functions. In one example, the memory stores a plurality of configuration images that define the configuration and functionality of the circuit. The information stored in the memory facilitates dynamic reconfiguration of the circuit in accordance with the test harness instructions.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: March 19, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Matthew A. Pleis, Bert Sullam, Todd Lesher
  • Patent number: 8402331
    Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20130055023
    Abstract: Techniques are disclosed for verifying memory dump operations and scan dump operations. A memory specification is analyzed and parsed to generate a script for performing a memory dump operation. To verify the memory dump operation, first, a set of values are written to one or more memories of a SoC. Next, the script is executed to perform the memory dump operation, and then an output bitstream from the operation is compared to the set of values. The scan dump operation involves taking a snapshot of a model of a SoC in an emulator. A scan dump operation is performed, and an output bitstream from the operation is compared to the snapshot. The memory and scan dump operations are invoked using commands in a first language, and the commands are translated into a second language to perform the operations.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Andrew K. Chong, Heon Cheol Paul Kim
  • Publication number: 20130055024
    Abstract: A central processing unit (CPU) test system includes a CPU socket, a CPU core controller, and a CPU test device. The CPU core controller stores a start voltage message. The CPU test device includes a voltage detection pin, an analog to digital (A/D) converter, and a microcontroller. The voltage detection pin detects a voltage of an electronic device connected to the CPU socket. The A/D converter converts the detected voltage into a digital signal. The microcontroller controls the CPU core controller to output the start voltage to the CPU socket according to the digital signal. The microcontroller stores a predetermined start voltage message. The microcontroller reads the start voltage message after controlling the CPU core controller to output the start voltage, and determines whether the CPU core controller supplies the start voltage to the CPU socket by comparing the read start voltage message with the predetermined start voltage message.
    Type: Application
    Filed: September 22, 2011
    Publication date: February 28, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD LTD.
    Inventors: YING-BIN FU, TING GE, YA-JUN PAN
  • Patent number: 8381052
    Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes ā€œnā€ number of groups of the failing memory output data during ā€œnā€ cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette