Abstract: An integrated circuit or other type of digital system including multiple processors is tested using a control mechanism which dynamically defines a group of processors subject to common control. The control mechanism receives one or more commands for each of the processors in the group, and delays issuance of one or more of the commands for the group until a designated group scan command is received for each of the processors in the group. The control mechanism may be in the form of a software-implemented chain manager which provides the above-noted group definition, command receipt and issuance delay operations, and subsequently delivers one or more of the test commands as a single serial bit stream to an IEEE 1149.1 hardware scan chain associated with the processors. The control mechanism can provide synchronous control for a group of homogeneous processors of the digital system, or pseudo-synchronous control for a group of heterogeneous processors of the digital system.

Abstract: An apparatus for predicting life expectancy of a rotary machine includes: a load recipe input module acquiring loading conditions of a rotary machine; a characterizing feature input module obtaining characterizing feature data of a rotary machine; and a life expectancy prediction module calculating life expectancy of the rotary machine in conformity with the loading conditions and the characterizing feature data.

Abstract: The invention is the microcontroller, which comprises CPU, a bus controller, an instruction address bus of a first bit number and an instruction code bus of a second bit number, which connect between the CPU and bus controller, and, further, a debug support unit, which is connected to the instruction address bus and instruction code bus. This debug support unit is also connected to an external in-circuit emulator via a tool bus of a third bit number that is smaller than the first bit number and via a bus-status signal line that reports on the status of this tool bus. The debug support unit has a data output circuit, which, in response to the status information signal, when the branch information contains a branch, outputs the converted instruction address serially to the tool bus, and when the branch information contains no branch, outputs a branchless signal to the tool bus.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: In the microcomputer, the debug target circuit and the debugging circuit with an interface module to the in-circuit emulator are independently supplied with drive powers. Drive power is supplied to the debug target circuit and the debugging circuit, and various debug information is set by the in-circuit emulator. Thereafter, only supply of drive power to the debug target circuit is stopped. While the various debug information is held at the debugging circuit, supply of drive power to the debug target circuit is restarted. The debugging just after power throw-in is performed based on the debug information held in the debugging circuit.

Abstract: A method and system for tracking and processing errors in a distributed computer system. As an application encounters an error, a centralized system intercepts and assumes the processing of that error event. The central error processing may be used with a distributed network connecting the applications running on various user computers. Upon receipt of an error message from an application, the system creates an informative error package, propagates appropriate error alert to relevant subsystems, and attempts to resolve the error. The error may be resolved in various ways. For example, the system may select and dispatch appropriate help information to the user; or the system may locate an alternative resource to substitute for the failed resource. The system may prioritize errors when there is more than one error still unresolved at any given time.

Abstract: A clustered computer system, apparatus, program product and method utilize a group member-initiated shutdown process to terminate clustering on a node in an automated and orderly fashion, typically in the event of a failure detected by a group member residing on that node. As a component of such a process, node leave operations are initiated on the other nodes in a clustered computer system, thereby permitting any dependency failovers to occur in an automated fashion. Moreover, other group members on a node to be shutdown are preemptively terminated prior to local detection of the failure within those other group members, so that termination of clustering on the node may be initiated to complete a shutdown operation.

Abstract: A high reliability computer system includes a first processing engine (PE), a first memory and a third memory both accessible by the first PE, a second PE, and a second memory and a fourth memory both accessible by the second PE. The first memory contains initialization information for the first PE. The third memory has a location for storing an enable password or a surrogate therefor for the first PE. The second memory contains initialization information for the second PE. The computer system also includes circuitry for switching control of the system from the first PE to the second PE upon detection of a failure of the first PE, and a password passer writing the enable password or a surrogate therefor of the first PE to the fourth memory. Alternatively, a network system includes an authentication, authorization and accounting (AAA) or any other password server having a database for maintaining an enable password for a high reliability computer system.

Abstract: A semiconductor integrated circuit having: an internal main bus; first microprocessor and second microprocessor sharing the internal main bus; a first debug serial bus with one end thereof connected to said first microprocessor; a second debug serial bus with one end thereof connected to the second microprocessor; and a debugging module connected to the other ends of the first debug serial bus and second debug serial bus and transferring at least a debugging program and debugging data to the first microprocessor via said first debug serial bus and to the second microprocessor via the second debug serial bus.

Abstract: Test tool logic and testing methods are provided for facilitating testing a duplexed computer function, such as a duplexed coupling facility. The test tool allows a testcase written for a first environment to be automatically driven in a second environment, thereby facilitating testing of a function of the second environment. Other aspects include logic for intercepting a system event by a test tool to facilitate testing of system-managed event processing, and for adjusting a display characteristic of one or more messages to be displayed by the test tool based on message type. Further, logic for propagating an environmental error indication and for facilitating processing a wait state are also provided, as are several new test tool verbs and macros.

Abstract: A semiconductor manufacturing apparatus allows the user to accurately determine the state of the apparatus and the cause of an abnormal condition for a short time. The apparatus includes a main unit for processing raw materials and forming a semiconductor, recording means for recording information of an operation to be executed by the main unit as predetermined data, operating means for operating the operation of said main unit and simulating the operation by using the predetermined data, and display means located remotely from the main unit and for displaying the simulated result.

Abstract: A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

Abstract: Smooth release of resources on a switch node adapter to a diagnostics program is provided without requiring rebooting of the system. The release technique includes: setting a first flag at a device driver associated with the adapter to block new open system calls from opening the device driver; broadcasting an adapter down event to instruct internet protocol (IP), fault service daemon (FSD) and application program interface (API) components of the node to release resources on the adapter; and setting a second flag at the device driver to block input/output control calls other than from the diagnostics program. When the device driver supports multiple adapters, only the adapter undergoing diagnostics is suspended, the remaining adapters remain up to components of the switch node. Upon completion of diagnostics, components remaining in open state are restarted on their communication windows at the adapter.

Abstract: A computer-implemented method for diagnosing the performance of a computer system using a diagnostic application. The method includes providing a diagnostic application and providing an operating system (OS) kernel, the diagnostic application being configured to execute under the OS kernel in the computer system, the OS kernel having a kernel trap arrangement. The method also includes providing a diagnostic monitor, the diagnostic monitor being configured to execute cooperatively with the OS kernel, the diagnostic monitor having a monitor trap arrangement. The method additionally includes ascertaining, using the diagnostic monitor, whether a trap encountered during execution of the diagnostic application is to be handled by the OS kernel or the diagnostic monitor. Furthermore, the method includes passing, if the trap is to be handled by the OS kernel, the trap to the OS kernel for handling.

Abstract: The present invention provides a system and method for analyzing hardware alarms in a telecommunications digital cross-connect system. The present invention also relates to a system and method for automating the process of analyzing hardware failures that cause path and parity alarms in a telecommunications digital cross-connect system used in a long distance network.

Abstract: A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.

Abstract: A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

Abstract: A hierarchical failure management technique uses an integrated equipment hierarchy to automatically pass failure information from control modules to unit modules. Each control module collects failure information and generates a composite failure code by mathematically combining the failure information collected by that module. Modules which are currently needed by a phase of the unit module to carry out a process automatically send respective failure codes to the unit module. The unit module selects the worst failure code from a list of failure codes within the unit module and compares the selected worst failure code to a predetermined threshold value to determine whether the process should continue.

Abstract: An apparatus for predicting life expectancy of a rotary machine includes: a load recipe input module acquiring loading conditions of a rotary machine; a characterizing feature input module obtaining characterizing feature data of a rotary machine; and a life expectancy prediction module calculating life expectancy of the rotary machine in conformity with the loading conditions and the characterizing feature datap.

Abstract: An enduser diagnostic system or “system” (10) for computer-based error interpretation includes a network addressable device (33), a computer-based system (20), and an inspector (40). The network addressable device (33) provides solutions for error problems associated with the computer-based system (20). The computer-based system (20) includes a system registry (26) for storing information required for configuring software and hardware components that define the computer-based system (20). The inspector (40) is a software component linked with the system registry (26) and the network addressable device (33). The inspector (40) compiles examination data by accessing the computer-based system (20) including the system registry (26). By generating examination data, the inspector (40) quickly and accurately provides information, including real-time information, required for assisting the network addressable device (33) with supplying a solution to the error.

Abstract: An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract: Disclosed is a method of testing memory, comprising providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip comprising one or more memory cells, providing a programmable testing apparatus comprising at least one test pattern generators and a test bed adapted to receive said one or more wafers in communicative contact so as to address individual memory cells, chips, and wafers and transmit information thereto and receive information therefrom, receiving one or more test commands, constructing a test sequence of one or more commanded tests from said test commands, constructing at least one header comprising location information for each said wafer, chip and memory cell, testing said memory cells with a test pattern generated by said test pattern generator, collecting the results of said testing and passing them to a display device, passing said location information to said display device, constructing and displaying a graphical representation of said test result

Abstract: Methods and apparatus for obtaining consistency of redundant data after a failover event. In one aspect, a redundant data storage system has a first data storage facility that initially acts as a primary facility for storage requests and a second data storage facility that initially acts as a secondary facility for the storage requests. The second data storage facility is conditioned to assume the role of the primary facility in response to a failover event. The first data storage facility is conditioned to assume the role of the secondary facility, which includes sending a copy of data committed at the second data storage facility to the first data storage facility. The copy of data includes a version of data committed at the second storage facility.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmatic support for multiple disparate display types, multi-mode programmable hardware blinking, programmable multiple color depth digital display interface, and programmable matrix controlled grayscale generation.

Abstract: In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups and a master TAP in another group, the master TAP having an instruction register with bits for storing a group selection code; a Test Data Output (TDO) circuit responsive to the group selection code connects the group TDO of one of the groups to the circuit TDO; and, for each secondary TAP group, a group Test Data Input (TDI) circuit responsive to a shift state signal for selectively connecting the group TDI to the circuit TDI or to the output of a padding register having its input connected to the circuit TDI, and its output connected to an input of the group TDI circuit; and a group TMS circuit responsive to a predetermined TAP selection code associated with the group for producing a group TMS signal for each TAP in the group.

Abstract: An in-circuit emulation system consisting of an emulation base and a slightly modified, flash-based COP8 architecture microcontroller. In addition to the flash memory where the User's program resides, the COP8 device includes a small ROM area with a monitor program that is used to communicate commands and data with the emulation base. Two new instructions are added, one for entering the ROM area and one for exiting it. A small set of the COP8 device's digital pins are modified to allow data, status and control to be exchanged between the COP8's CPU and the emulation base. These modified COP8 pins are recreated by the emulation base so that emulation occurs with the COP8's full complement of I/O. The content of the signals shared between the COP8 and the emulation base allows for a full range of emulation capabilities. The COP8 device is emulated in situ on the printed circuit board providing accurate operation of precision peripherals and environmental variables.

Abstract: The present invention provides a system and method of detecting a process failure and a network failure in a distributed system. The distributed system includes a plurality of processes, each executing on a host, operable to transmit messages (i.e., heartbeats) to each other on a network. A process in the system is operable to execute a process failure algorithm for detecting failure of a process in the system. The process failure algorithm includes calculating a difference in the period of time to receive a heartbeat from a first processes and a period of time to receive a heartbeat from a second process in the system. If the difference exceeds a process failure threshold, the second process is suspected of failing. A process in the system is also operable to execute a network failure algorithm for detecting failure of a network connecting a plurality of hosts in the system.

Abstract: The present invention provides a system and method for effective troubleshooting of a network. In one embodiment, the present invention provides a system for troubleshooting a network having a plurality of network elements. A management station may be coupled to one of the network elements for signaling a distributed network operating system to transmit alarm information from each network element to the management station for display to a user. The system also includes a plurality of network element subsystems in each network element, wherein at least one of the plurality of network element subsystems generates a subsystem alarm in response to a subsystem fault condition. The distributed network operating system includes a plurality of subsystem applications on each network element, wherein at least one of the subsystem applications on each network element generates an application alarm in response to receiving the subsystem alarm.

Abstract: A programmable logic controller having a data holding unit for storing operation data for instructing operations and condition data for the operations in accordance with a predetermined sequence, having a variable control unit for generating operation instruction signals from the operation data in accordance with a predetermined sequence, and controlling a system for successive operation when conditions defined by the condition data and conditions input from sensors of the control system match.

Abstract: This invention relates to an automated test system for the remote testing of applications and devices especially in dynamic environments. It provides for the automation of the testing process and for functional independence at every level of the process. The invention is particularly suited for remote testing over a network such as the internet. To achieve its purpose, the invention provides a test generation means for generating the tests and executing the testing, which is connected to a data storage means contains information about testable items and test scenarios for the testable items, as well as the results of testing. The image builder means provides a centralized image building facility for converting the tests into an executable form.

Abstract: A method, system, and product in a computer system are described for reporting error events which occur within the computer system. The computer system includes multiple logical partitions. Each of the logical partitions includes a different one of multiple, different operating systems. A format is specified for reporting error events. An error event occurring within one of the logical partitions is detected. Information about the error event is formatted according to the specified format. Each operating system utilizes this format to report error events.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A method and mechanism for configuring a node in a computing system to route data to a predetermined observation point. A node in a computing device or system is configured to identify and convey an observation data stream via a non-critical path. A non-critical path is configured within the computer system for the transmission of the generated stream of data to a convenient client location where the data may be observed. This stream of data is routed through the computer system via disabled, replicated, monitor or other links which correspond to a non-critical path. The observation data stream conveyed by the node may be generated by the node and correspond to an internal state of the node. Additionally, the node may be configured to duplicate and convey received data streams or extract debug data from a received data stream for conveyance to a predetermined observation point.

Abstract: A system for monitoring and managing devices on network comprising one or more managed devices connected to the network and storage means for storing a device management application program associated with each of the managed devices. The system further includes a management station which is in communication with each of the managed devices across the network, and the management station is in communication with the storage means. When a user wishes to monitor, configure, or manage one of the managed devices on the network, the user preferably selects the managed device to be managed and the management station retrieves from the storage means the device management application program associated with the selected managed device. By the management station processing the management application program for the selected managed device, the management station allows the user to monitor the status of the managed device, as well as change the configuration of and fix errors with the managed device.

Abstract: A distributed-processing equipment has a first storage means in which identifiers of first processors that reconfigures respective devices are registered in advance. When a second processor has detected an event for which one of the devices is reconfigured, the second processor notifies, of the event, a first processor indicated by an identifier that is registered in the first storage means as corresponding to the device. This distributed processing equipment can flexibly adapt to a variety of configurations at a low cost without changing the configuration greatly, whereby the performance and the reliability of an information processing system and a facility to which the invention is applied can be kept high in a stable manner.

Abstract: A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Abstract: An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

Abstract: One embodiment of the present invention provides a system that facilitates recovering from failure in a distributed event notification system. During operation, the system detects a failure of an event forwarder, which notifies subscribers of events generated by distributed components in the distributed computing system. In response to detecting the failure, the system restarts the event forwarder, typically on another node in the distributed computing system. Next, the system requests a snapshot of current state from the distributed components. In response to this request, the system subsequently receives events from the distributed components that specify current state of the distributed components, and then forwards the events to subscribers that are registered to be notified of the events.

Abstract: A vehicle maintenance system predicts potential failure of a component or system using statistical data and methods. The maintenance system preferably includes a communications apparatus for communicating component or system performance data to an offboard network or data collection device. Methods for advantageously using the collected performance data are also provided.

Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

Abstract: A memory test system of the present invention comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. The common memory unit has an interrupt controller (INT CNT) 22. In each of the memory test units 90, a slave processor (MCPU) 40 and a memory for the slave processor (MEM) 14 are provided. MCPU 40 reads memory test results and responses of local processors (RCPU) 42 to 46 which are stored in RMEMs 32 and transfers read data to SMEM 16. MCPU 40 generates an interrupt signal. When all MCPUs 40 generate interrupt signals, INT CNT 22 generates an interrupt signal INT to the EWS 10. The EWS 10 may perform several functions based on the interrupt signal INT.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: An internal bus testing device for a semiconductor integrated circuit in which an internal bus control circuit and a plurality of modules are linked by a plurality of internal buses. The internal bus testing device includes an area selector which causes the internal bus control circuit to select an address area corresponding to one of the plurality of internal buses. An area address setting unit sets the internal bus control circuit in an internal bus test mode in response to an internal bus test start signal, the area address setting unit storing a state setting signal and a predetermined address value indicating the address area. A control unit supplies, at a start of an internal bus test, the address value from the area address setting unit to the area selector by transmitting the state setting signal from the area address setting unit to the area selector.

Abstract: An apparatus and method for performing a diagnostic problem determination methodology for complex systems is provided. With the apparatus and method, a diagnostic application for a system may automatically invoke additional diagnostics for child devices and/or siblings of the child devices based on status of the child devices after testing the parent device. This allows for complete testing of a subsystem in a single diagnostic execution resulting in a more complete, accurate analysis of subsystems with complex configurations such as seen with redundant arrays of independent disk drive (RAID) systems.

Abstract: A system and method are disclosed for aiding a field engineer in the field such as at a remote service facility in analyzing a fault log of a malfunctioning machine such as a locomotive. The method includes obtaining data associated with operation of the malfunctioning machine from a user at a second computing unit coupled via a communications network such as the Internet to a first computing unit such as a centrally located server operable to provide data associated with analysis of the malfunctioning machine, and providing at the second computing unit at least one of a diagnosis of and a repair for the malfunctioning machine based on the data associated with the operation of the malfunctioning machine and the data associated with analysis of the malfunctioning machine.

Abstract: An interconnect system connects two drawer management cards (DMCs) of a drawer. The drawer contains a plurality of independent nodes. The nodes are managed by at least two DMCs. Thus, if one of the DMCs fails, the other DMC can take over and manage the drawer. In one embodiment of the invention, the nodes within the drawer are managed through an Intelligent Platform Management Bus (IPMB). The other field replaceble units (FRUs) or hardware components in the drawer, such as fans, power supplies, etc., may be managed using an Inter Integrated Circuit bus (I2C). The first and second DMCs are interconnected with each other within a chassis of the drawer. The two DMCs are also interconnected with the management channels (e.g., buses) of the drawer. During power up, the first DMC and the second DMC on the drawer may determine, whether the DMC's are interconnected (or not). The DMCs then decide each of their roles (i.e., determining which DMC should be in an active state and which DMC should be in a standby state).

Abstract: A cPCI server system includes a plurality of printed circuit assemblies. A server management card coupled to the plurality of printed circuit assemblies monitors and manages operation of the server system. The server management card receives and stores status information from the plurality of printed circuit assemblies. A first LCD panel is mounted on the server system and is coupled to the server management card. The first LCD panel provides a user interface for configuring the server management card and accessing the stored status information from the server management card.

Abstract: A processor includes instruction sequencing logic, execution circuitry, data storage coupled to the execution circuitry, and test circuitry. The test circuitry detects for a hardware error in one of the instruction sequencing logic, execution circuitry, and data storage during functional operation of the processor in response to an instruction within an instruction stream provided by the instruction sequencing logic. In one embodiment, a hardware error can be detected by comparing values output in response to a test instruction by redundant circuitry that performs the same function. Alternatively or in addition, a hardware error can be detected by performing an arithmetic or logical operation having a known result (e.g., multiplication by 1, addition of 0, etc.) in response to the test instruction.

Abstract: A semiconductor module that comprises a plurality of semiconductor chips mounted on a single substrate and which readily diagnoses all the semiconductor chips. A plurality of semiconductor chips are mounted on a single substrate. The semiconductor module is provided with a mode signal pin for receiving a mode signal for requesting performance of a diagnostic operation, as well as with a result output pin for outputting diagnostic results. Further, each of the semiconductor chips is provided with a diagnostic circuit for diagnosing the status of the corresponding semiconductor chip. The semiconductor module is also provided with a diagnosis controller for controlling the diagnostic circuits such that all the semiconductor chips are diagnosed in parallel or serially after a mode signal for requesting a diagnostic operation has been supplied to the mode signal pin.