Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: A functional unit for carrying out logical test cases on a test system interconnected to a unit that is to be tested, the functional unit being suitable for being interconnected between the logical test cases and the test system in such a way that the logical test cases are decoupled from the test system, and, in this context, for supporting an execution of the logical test cases on the test system as mediator.

Abstract: Method and system for repairing memory failure in a computer system in one aspect determines one or more test patterns and time duration for testing the new memory unit that replaced a failed memory unit. The test pattern is written to the new memory unit and read from the new memory unit. The read pattern is compared to the test pattern that was used to write. If the read test pattern and the written test pattern doe not match, a further repair action is taken. If they match, writing and reading of the test pattern repeats until the time duration for testing expires. The new memory unit may be configured as available for use when the write and read test completes successfully for the testing time duration.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

Abstract: An actuator (10) includes sensors (12) which are used to detect variables representing the operating state of the actuator (10) and are connected to an evaluation unit (16) associated with the actuator (10). The evaluation unit (16) is connected to sensors (12) and/or control actuating elements (13) by means of a first data bus (15). The sensors (12) are used to detect measurable variables representing the operating state of the actuator (10), and to transmit the same to the evaluation unit (16).

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: To enable measurement of a suspension position and a suspension period of the reference clock of a microcomputer to be inspected, based on the information stored into a clock information register section, by acquiring output data output from the microcomputer; preserving the acquired output data into a data bank section by use of the reference clock being output from the microcomputer together with the output data; discriminating the suspension of the reference clock by a clock operation discrimination section at sampling intervals of the output data; and writing and preserving the discrimination result into the clock information register section by a register control section.

Abstract: A system for updating management entities or devices in a computer system network with configuration change information from the devices being managed. The management entities are configured to discover, monitor and configure managed devices, such as storage systems, connected to the network. Preferably, the managed devices include a comparator which can track changes made to the managed device configuration or properties and report that change back to the various management entities. In this way, the management entities can keep track of the configurations of the various devices that they manage, even though they might not be responsible for issuing the configuration change. This can be accomplished even when managed devices developed by different manufacturers according to different standards or protocols are involved.

Abstract: An apparatus, program product and method provide a generic error reporting and diagnosis framework that is readily suited for use in a wide variety of distributed computing environments, and that supports the autonomic reporting, diagnosis, and potentially the remediation of errors. The framework supports the encapsulation of symptomatic data associated with an error in a component of a distributed computing environment such that the encapsulated symptomatic data may be routed to an error processing facility, typically irrespective of the underlying nature of the error and the hardware and/or software platform of the component that generated the error. The error processing facility is in turn capable of routing the encapsulated symptomatic data to one or more diagnostic agents that are capable of processing the symptomatic data to prescribe a treatment for the error.

Abstract: Methods and apparatus are provided for implementing a semiconductor device with a debug core separate from a processor core. The user configurable debug core can be customized to include one or more debug core submodules. Each debug core submodule is generally associated with a particular debug feature such as trace generation, performance counters, or hardware triggers. The debug core can be driven through a variety of interfaces to allow debugging, monitoring, and control of processor operations.

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.

Abstract: Stationary power equipment including a sensing device configured to collect data associated with an operation of the equipment, and a data storage device configured for storing the collected data. Information derived from the collected data may be transmitted to a remote system via a data transmission network, or be downloaded to a data storage medium or a diagnostic device. An operation condition of the stationary power equipment is determined based on the information. Responsive to the operation condition, the power equipment receives data that is selected based on the operation condition, and modifies an operation of the power equipment based on the received data.

Abstract: A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger.

Abstract: A method is provided wherein a lithographic projection apparatus is used to print a series of test patterns on a test substrate to measure printed critical dimension as function of exposure dose setting and focus setting. A full-substrate analysis of measured critical dimension data is modeled by a response model of critical dimension. The response model includes an additive term which expresses a spatial variability of the response with respect to the surface of the test substrate. The method further includes fitting the model by fitting model parameters using measured critical dimension data, and controlling critical dimension using the fitted model.

Abstract: In general, in one aspect, the invention relates to a method for monitoring a computing device, that includes receiving, by a data collector, a plurality of system messages from a system controller, wherein the data collector is wired to a serial port component of the system controller, wherein the system controller is factory preconfigured to automatically send the plurality of system messages via the serial port when the data collector is connected to the serial port, wherein the computing device comprises the system controller, and wherein the data collector is independent of the computing device. The method further includes storing data from the plurality of system messages on the data collector, receiving, by the data collector, a data transmit request, and wirelessly transmitting, by the data collector, the data to a field receiver.

Abstract: The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: Systems, methods, apparatus and software can implement a flexible I/O fence mechanism framework allowing clustered computer systems to conveniently use one or more I/O fencing techniques. Various different fencing techniques can be used, and fencing mechanism can be customized.

Abstract: A method for running a computer program on computing hardware, in particular on a microprocessor. The computer program includes multiple program objects designed as tasks, for example. Transient and permanent errors are detected during the running of the computer program on the computing hardware. To be able to handle these transient errors constructively when they occur in a computer system in such a way that the functionality and function reliability of the computer system are restored within the shortest possible error tolerance time, at least one program object that has already been sent for execution is set into a defined state on detection of an error and is restarted from this state. The program object is a runtime object of the computer program, for example, also known as a task. One or more tasks that are still being executed or have already been executed on occurrence of an error are restarted and run again.

Abstract: A mechanism for isolating failures in a digital system is provided. In one embodiment, a fault table is defined for each unit in the system. Related faults are ordered within the table to reflect the time-order in which the faults would be activated during operation of the associated unit. When multiple related faults are reported for a given unit in the system, the fault that is first located when a linear search of the corresponding fault table is conducted is considered the source of the failure within the unit. If faults are reported for multiple units, the source of the failure for the system is identified using at least one of primary and second priority values assigned to the faults, timestamps obtained when the faults are reported, and an order in which the faults are logged.

Abstract: A debug network on a multiprocessor array includes communication channels, a master controller, and one or more individual debug units in communication with one or more of the processors. The master controller solicits information from the debug units by sending messages along the communication channels. The debug units can control some aspects of the processors, and can simply report on other aspects. By using commands to invoke processor action, then accessing the result, interactive debugging of a multiprocessor array is possible.

Abstract: A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.

Abstract: A system and method is disclosed for increasing the efficiency of a cellular communication network, reduce ongoing operating costs and increase revenue. According to one aspect, a method is disclosed for increasing the efficiency of a cellular communication network whereby network capacity in the radio access network (RAN) and baseband processing for wireless connections are dynamically adjusted to automatically provision sufficient bandwidth and baseband processing capacity in response to changes in the network. The method is further extended by implementing policy management which allows wireless carriers to develop and implement network based policies to automatically increase or decrease the amount of processing resources and network bandwidth required from any cell site, hub or mobile switching office. According to another aspect, network efficiency is enhanced by utilizing a novel cellular network infrastructure.

Abstract: Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using a descriptive language including setting at least one default value associated with the device. The method also includes defining a scan path associated with the device, defining a netlist of the circuit, and configuring a test control program for the circuit. Additionally, the method includes changing the default value associated with the device. Testing the circuit after changing the value and using the test control program is also included wherein a portion of the test control program associated with the value remains substantially unmodified.

Abstract: An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

Abstract: The invention provides for facilitating e-commerce transactions between a client and a server over a network. In particular, a client, such as a client computing device, can perform a diagnostic test, such as a power-on self-test, and determine during the test any goods requiring replacement (e.g., acquiring a substitute good, repair, or upgrade). The client may then contact a server, such as a vendor or a technical support department, for procuring such replacement. In one embodiment, the server sends the client diagnostic commands so as to allow remote diagnosis of operability of the client.

Abstract: Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.

Abstract: An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.

Abstract: A trace and debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core executes non-successive instruction in accordance with an address data of the program counter; (C) producing a trace break event in order to set the processor core to enter a debug mode if the processor core executes a non-successive instruction; (D) fetching a value of the program counter and a state of the processor core; and (E) sending the value and the state to a host to accordingly form a trace and debug message with respect to the processor core.

Abstract: To log errors of a plurality of subsystems, a master reporting tool provides a table identifying the subsystems and their interface protocol addresses with respect to a network. A subsystem reports errors, via the network, to the master reporting tool, and the reporting subsystem identifies and reports other subsystems associated with the errors, if any, to the master reporting tool. The master reporting tool employs the interface addresses of the table to request reportable data from the other subsystems identified by the originally reporting subsystem as associated with the reported error. The network may be separate from a data handling network of the data handling system.

Abstract: Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus for the Internet phone, which can develop and verify the system-on-chip simultaneously by integrating an Advanced RISC Machine(ARM) core module, a field programmable gate array (FPGA), a peripheral interface and the system-on-chip. The apparatus includes an ARM core module performing a core processor function, a peripheral interface including a memory and many external input/output devices, a FPGA controlling the ARM core module and performing a control function for connecting the ARM core module and the peripheral interface, and a system-on-chip integrating the functions of the ARM core module and the FPGA.

Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Abstract: An automated testing system is provided that includes a computer system, a handset, script and scripting interface, a test module, and a data comparison component. The handset has at least one application resident thereon to be tested. The handset is coupled to communicate with the computer system. The script executes on the computer system and is operable to generate an input to the application on the handset to test the application. The test module is embedded in a source code of the application. The test module is operable to monitor a response by the application to the input by the script. The data comparison component compares the response by the application monitored by the test module to an expected response.

Abstract: A method for analyzing the root cause of system failures on one or more computers. An event is generated when a computer system detects a system failure. The cause of the failure is determined. The event, including the cause is transmitted from the computer system to a central repository. And the system failure is analyzed in the central repository.

Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Abstract: A method for using an operating system device for non-operating system uses. A false event signal is generated to indicate that a device should be shut down. After this is accomplished, the device is used for a different purpose while the operating system thinks it is inoperative. Once the other use is completed, another false event signal is generated so that the device is activated again and returned to use in the operating system in normal fashion.

Abstract: A method and device for recording call failure information in a data transmission system is provided. The failure logs generated in response to a failure event include a failure type and a first timestamp. A log record is created for a first failure log based on the failure type, and storied in a log record storage. Whenever a further failure log is generated in response to the same failure event, the further failure log includes said failure type and a current timestamp, so that it will receive the same identifier. The log record is updated to document the current timestamp.

Abstract: An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

Abstract: A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset.

Abstract: A maintenance management system according to the present invention has an electronic device and a database server. In one embodiment of the invention, the electronic device further includes: (1) a log generating unit for collecting states of components and generating a log when a failure is detected during execution of a process; (2) a DB inquiry unit for transmitting the log to the database server and making an inquiry about whether firmware capable of solving the failure exists; and (3) an updating process unit for obtaining firmware capable of solving the failure from the database server and updating firmware in the electronic device with the obtained firmware. In addition, the database server further includes: a storing unit for storing a database having version information of firmware and failure correction information; and an inquiry responding unit for identifying when firmware for solving the failure exists.

Abstract: A method and a system for implementing the method are disclosed relating to archival storage of information in large numbers of disk units. The reliability of the stored information is checked periodically using data verification operations whose results are saved. These results establish the veracity of the data and enable compliance with various regulatory requirements. The techniques described enable the use of low cost disk drive technology, yet provide high assurance of data veracity. In a typical system, management information storage is provided in which data entries are associated with each of the disk drives to provide information with respect to the condition of the data on that drive and its last verification. The data verification operations are performed on the data during time periods when I/O accesses are not required.

Abstract: Controlling the timing of execution of test instructions by a target computing device is disclosed. A method initiates a test process at each target computing device. The method receives a process handle of the test process from each target computing device, as generated at the target computing device. The method repeats sending to each target computing device the process handle of the test process, and a test instruction to be executed at the target computing device, until the target computing device has finished executing all the test instructions. A test instruction may be a test script made up of a number of test commands that are to be executed as a group, or a test instruction may be a single test command. Timing of execution of each test instruction can be controlled by deciding when to send the test instruction to a target computing device.

Abstract: A Micro Telecommunications Computing Architecture, MicroTCA, test system comprises an interconnect for communication between modules of the MicroTCA test system. A test controller module, such as a JTAG, Switch Module, is coupled to the interconnect and comprises an interface for coupling to at least one unit under test. An interface module, such as a MicroTCA Carrier Hub module, receives test instruction messages from an external connection and forwards these to the test controller module via the interconnect. The test instruction messages comprise test input data for at least a first unit under test. The test controller module furthermore comprises an extraction processor for extracting the test input data from the test instruction messages; and a test controller for performing a test of the first unit under test in response to the test input data.

Abstract: The present invention provides a system verification system that automatically generates a behavior model modeling the system under test in terms of actions of a test case and a range of expected reactions corresponding to those actions. In this regard, the system verification system obtains a set of actions and individual reactions corresponding to the actions from a plurality of runs of a test case for the system under test, and automatically generates the behavior model representing the system under test in terms of the set of actions and a range of expected reactions each range corresponding one of the actions. The range of expected reactions generalizes and includes all or most of the individual reactions corresponding to said one of the actions.

Abstract: Functional testing of an embedded system is performed by a test control system that implements a peripheral emulation module to interface with an externally accessible port of the embedded system. The test control system implements a test generation processor that operates to autonomously resolve abstracted component templates and embedded system description data, specific to the embedded system, to produce a corresponding specific test program. The test control system executes the test program to drive operation of the embedded processor unit to cause transfer of test data through the external interface, which is then autonomously compared to reference data derived through the execution of the test program and specific to the embedded system, whereby the comparison results reflect the correct operation of the embedded system.

Abstract: This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.

Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.

Abstract: An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.