Abstract: An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

Abstract: A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block events or “tags” are created from a slice of a graphical stimulation view, which slice is converted into a coded stimulus written in a high-level language code that represents the condition(s) that created the graphical simulation view. These coded stimuli (representing the tags) are stored in a library. To create a corner case scenario or sequence in the DUT, a user utilizes a graphical interface to select the different extracted tags from the library and combines them together.

Abstract: A complex user-facing computer application often has run-time dependencies on other computer applications. The other computer applications may, in turn, have run-time dependencies on still other applications. A supporting application might run on multiple hosts and a particular host might be chosen by a higher-level application in order to meet requirements such load balancing or reliability. In order to facilitate intelligent choices by higher-level applications in the system, each server in the system is responsible for generating a performance capability or health score that reflects the health of local components and the health of all servers on which the given server has a direct run-time dependency. A particular server's generated health score is advertised to any other server that has a direct run-time dependency on the particular server. Decisions about which of alternative lower-level servers to use in a servicing a client request are made using a routing or hop-at-a-time approach.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract: Upon detecting existence of characteristic information of a failure, of which search is requested, a mobile terminal device 102 notifies a failure management server 104 of the detected location information and time information together with the characteristic information of the failure, and the failure management server 104 notifies a terminal device 1022 of the location information of the failure to be estimated on the basis of the detected location information, time information, and the characteristic information of articles and allows the terminal device 1022 to output this location information. Thereby, even in the case that no communication apparatus is provided to a target apparatus, a failure can be detected and a probability of notification can be improved.

Abstract: A network monitoring method and system reduces a load to a monitoring network without deteriorating accuracy of detecting a malfunction. A plurality of network constituent elements that constitute a communication network are connected to an operation system through a monitoring network. A health check for detecting a malfunction is periodically performed between a group of the network constituent elements positioned closed to each other within the communication network at a short monitoring period. A health check of malfunction detection on all of the network constituent elements is performed by the operation system at a long monitoring period longer than the short monitoring period.

Abstract: A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in which its output is not used in system control. A meta-controller is activated to drive the primary controller to the same states at which the secondary or redundant controllers operate. A voting mechanism is used to determine a fault in an output to a controlled device. Control of the device using the secondary outputs is effected. The primary controller recalculates the primary output, based upon the primary output; a feedback signal; and, the secondary outputs. Control using the primary output is permitted when the primary output is within an allowable range of the secondary outputs.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A program-controlled unit has debug resources for monitoring the operations proceeding within the program-controlled unit. The program-controlled unit described is distinguished by the fact that the debug resources contain a CPU, and/or that a portion of the debug resources is provided for monitoring the operations proceeding within the remainder of the debug resources. Debug resources constructed in this way make it possible for errors occurring in program-controlled units to be localized and eliminated rapidly and simply under all circumstances.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: An apparatus, system, and method are disclosed for performing a storage device maintenance operation. A management module receives a command through an interconnection module configured as a non-blocking switch. The management module performs a maintenance operation on a storage device through the interconnection module in response to the command. In addition, the management module may receive queries on the status of the maintenance operation through the interconnection module and report the status of the maintenance operation through the interconnection module.

Abstract: A system and method may emulate scenarios for testing a distributed system. The distributed system may include a plurality of nodes, each having one or more resources. The system may include a resource driver for each type of the one or more resources in the distributed system, as well as one or more agents configured to access each resource through the corresponding resource driver. At least one node in the distributed system may be configured to run on a different platform than another node in the distributed system. The system may further include a central controller configured to communicate with each agent. The central controller may further execute a test scenario script containing one or more test scenarios for the distributed system.

Abstract: A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for generating a defect value when a defect in a predetermined region of an optical disc is detected; a weighting circuit, electrically connected to the defect detecting unit, to generate a weighted defect value according to the defect value and a weighting factor corresponding to a location of the defect on the optical disc; and a computing module, electrically connected to the weighting circuit, for computing the defect estimation value according to a plurality of weighted defect values corresponding to the predetermined region.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.

Abstract: A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic application is provided with access to the file system of the failed O/S image. The diagnostic software application collects relevant configuration information from the file system of the failed O/S image, and transports this information to a proxy system running the same operating system as the computing device being diagnosed. The proxy system utilizes the collected data to diagnose the subject failed O/S system. Once the proxy makes a determination it synthesizes repair information comprising new or modified files and instructions to be transported back to the diagnostic software system to apply. A network connection is provided between the computer running the diagnostic application and the proxy system that enables data to be easily transported between the two systems without human intervention.

Abstract: A method and data processing system for isolating a faulty component in a computer. A first microcontroller detects a fault in a component of a computer. Responsive to detecting the fault, the first microcontroller sets a first fault record for the component to pending fault, sets a second fault record for the first microcontroller to pending fault, and fails over to a second microcontroller. If the second microcontroller detects the fault in the component of the computer, then the first fault record for the component is set to permanent fault, and the second fault record for the first microcontroller is cleared. If the second microcontroller determines the component of the computer does not have the fault, then the first fault record for the component is cleared, and the second fault record for the first microcontroller is set to permanent fault.

Abstract: An improved testing assessment tool and methodology maps the Testing Maturity Model (TMM) structure to individual test areas, thereby enabling comprehensive and targeted improvement. In this way, the present invention uses the five TMM maturity levels to assess individual areas, rather than merely assigning a single maturity level to the entire organization. Embodiments of the present invention include a quick assessment that includes a relatively small number of questions to be subjectively answered using the TMM hierarchy. Embodiments of the present invention further include a full assessment that includes a relatively large number of questions to be discretely answered, with these results being use to evaluate various testing areas using the TMM hierarchy.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for testing a data service on a computing cluster having several computing nodes. A test package is installed on a test administration machine and on one or more of the computing nodes in the computing cluster. Data service configuration information is collected for the data service to be tested. Computing cluster configuration information is collected. The data service configuration information and the computing cluster configuration information are distributed to one or more of the computing nodes in the computing cluster. The data service is tested on the computing cluster by applying one or more data service test suites in the test package to the data service. A report containing results of the application of one or more of the data service test suites to the data service is generated.

Abstract: A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.

Abstract: A communication state storing unit stores the communication error states of the field bus communication. A connecting state updating unit updates a connecting state of the field bus communication of two systems. A diagnosing unit sequentially and periodically obtains the communication error states stored in the communication state storing unit to diagnose the communication state of the field bus communication in accordance with the obtained communication error state, and sequentially and periodically obtains the connecting states updated by the connecting state updating unit to diagnose the communication state of the field bus communication in accordance with the obtained connecting state.

Abstract: A preferred embodiment of the present invention provides a method and system for managing a distributed medical diagnostic imaging system. The system includes a system manager for managing the medical diagnostic imaging system, a subsystem that includes a subsystem manager for managing the subsystem and an actor, or task operator, capable of executing certain functions. The subsystem manager reports to the system manager. The system also includes a communication channel for transmitting data between the system manager and the subsystem. The system may include a plurality of subsystems with a plurality of actors or task operators. The components of the system may be configured and adjusted.

Abstract: Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative storage locations to facilitate run-time detection and, in some cases, mitigation of soft errors. In general, a compiler emits a program sequence of primary instructions that correspond to source code. However, in addition, for those primary instructions that target storage susceptible to soft errors, the compiler may emit corresponding additional instructions that target additional storage. In some implementations the additional storage is not itself susceptible to soft errors. However, more generally, implementations may tolerate soft errors affecting the additional storage, as long as such soft errors are generally uncorrelated with those affecting the storage targeted by the primary instructions.

Abstract: An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

Abstract: Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.

Abstract: A SAS expander includes SAS PHYs for transceiving signals with SAS devices on corresponding SAS links coupled to the SAS PHYs. The SAS expander includes status registers that provide fault detection parameters concerning communications on the SAS links. A microprocessor of the SAS expander identifies faulty communications on one of the SAS links, based on the fault detection parameters, and disables a corresponding one of the SAS PHYs coupled to the SAS link on which the microprocessor identified the faulty communications. The microprocessor may also report the PHY disabling to a SAS initiator. The microprocessor may also re-enable the PHY after corrective action is taken, such as in response to user input, an indication from a SAS device, or automatically detecting the corrective action. The expander may also automatically take the corrective action. The fault detection parameters may include error counters and corresponding thresholds, interrupt indicators, and state values.

Abstract: The present invention relates to a motor shock prevention structure, which is a shock prevention structure disposed between a metal tube and a fixing hole of the bottom plate in a motor such that the metal tube and the bottom plate are not directly contacted. Moreover, the shock prevention structure includes integrating at least a shock prevention element and a gasket. As the shock prevention element is made of a flexible material being shock-absorbent and damping, the vibration amplitude during motor rotation won't be transmitted to the bottom plate and the electronic system due to the damping function of the shock prevention element, and the resonant effect and noise out of vibration occurring in an electronic system is avoided.

Abstract: An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTAG-compatible bitstream that can be used by the processor's test circuitry to access and/or control the processor's resources at any time, thereby allowing the embedded processor's resources to be accessed and controlled during FPGA configuration operations before the processor has been initialized to an operational state without using an external configuration tool. For some embodiments, the formatting circuit is a state machine that formats soft data such as firmware code, software programs, processor commands, and the like received from the external storage device into a JTAG-compatible bitstream that can be loaded into and/or used to access the resources of the embedded processor via the processors' test circuitry.

Abstract: A method is provided for transmitting messages between bus users that are each linked with a communication bus for the purpose of exchanging messages and with a diagnostic device for detecting the failure of the communication bus. In a diagnostic operation mode that is different from the normal operation mode, the bus user receiving the message is requested by the diagnostic device to output the message to the communication bus, thereby diagnosing a message transmission between two bus users.

Abstract: The present invention provides an apparatus, system and method for use in remotely diagnosing electronic devices and/or providing content. The method for use in remotely diagnosing includes the initiating a diagnostic analysis of an electronic device, identifying the electronic device, receiving scripts communicated over a distributed network for diagnosing, remotely initiating diagnostic instructions with the scripts and receiving a response based on the instruction. The method can further determine further diagnostic instructions based on responses, and remotely initiate further instructions with the scripts. Additionally, a system for use in remotely diagnosing electronic devices includes a script generator coupled with a distributed network, and a remote diagnostic controller coupled with the distributed network and with an electronic device. The script generator compiles scripts and forwards them over the distributed network.

Abstract: The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC core, constructs a core kernel section using a device integrating additional FPGAs available to support additional functions, and provides a plurality of interfaces necessary to an Internet telephone function centering around the core kernel section. With this, the number of necessary component parts can be minimized to facilitate design and simplify the configuration thereof.

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract: A hardware debug device is usable to debug a target such as a microcontroller or microprocessor. A host instructs the hardware debug device what tests to perform on the target by sending a non-compiled script of text across a standardized script-based interface. The hardware debug device receives and interprets the script and sends appropriate microcommands to the on-chip debugger of the target to carry out actions specified by the script. The syntax of the interpreted script language is rich and allows scripts to define complex looping and testing actions. New scripts can be written to accommodate different target processors without changing the hardware debug device. Because complex testing operations are performed by the hardware debug device, network traffic at the host is reduced. The use of the interpreter and scripts also allows the cost of the hardware debug device to be reduced and reliability of the device to be increased.

Abstract: A computer peripheral connecting interface system configuration debugging method and system is proposed, which is designed for use in conjunction with a computer platform that is equipped with a particular type of peripheral connecting interface, such as a PCI (Peripheral Component Interconnect) interface, for automatically finding errors in the PCI system configurations of a group of peripheral devices connected to the PCI peripheral connecting interface, and if errors are found, capable of automatically generating an electronic error report. This fully-automatic debugging capability can help software engineers to more conveniently and efficiently correct the errors in the PCI system configurations on a computer platform.

Abstract: A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory built in self test sequencer module and providing satellite engine module coupled to the memory built in self test sequencer module, to the plurality of embedded memories and applying read and write protocols to the plurality of embedded memories based upon the particular read and write protocols of each of the embedded memories. The satellite engine module includes an instruction buffer and a sequence generation engine.

Abstract: A process plant includes a process control system having a safety system embedded therein. The integrated process control and safety system includes a host computer arranged to send and receive process level messages and safety level messages, a controller operatively connected to the host computer by a first communication network, at least one first input/output device adapted for operative communication with at least one process control field device, and at least one second input/output device adapted for operative communication with at least one safety-related field device. The first and second input/output devices are operatively connected to the controller via a second communication bus.

Abstract: An automated software re-testing system for efficiently validating proper operation according to a specification. Regression tests are automatically created in an object-oriented system. The inheritance hierarchy of the system is used to determine which system classes should be tested. Regression test class destructors are used to test dependent classes. Unchanged system classes, and those dependent entirely on unchanged system classes need not be tested and time and effort are saved by skipping their re-testing.

Abstract: In at least some embodiments, a computer system may comprise a CPU and a system memory coupled to the CPU. The computer system may further comprise a management device coupled to the CPU and the system memory. The management device is operable to permit remote control of the computer system by other computer systems. The management device is configured to receive a signal when the computer system malfunctions and, in response to receiving the signal, perform a data dump of at least some of the data in the system memory without involvement of the CPU.

Abstract: A program-controlled unit (e.g., a microcontroller) in which trace information (e.g., selected addresses, data and/or control signals) that is processed by a core and which can be used to trace the profile of the processes occurring within the program-controlled unit, are stored and/or output from the program-controlled unit along with corresponding identification codes that are used by an external debugging system to identify the trace information.

Abstract: In one embodiment, the invention may include a logic structure integrated in an integrated circuit (IC), that has a set of bus inputs to generate events, a mask register to select inputs from among the set of bus inputs, a logic register to select logic to apply to the selected inputs and an event output to supply the result of the applied logic. The embodiment may further include a bus interface integrated in the IC and coupled to the logic structure to transmit settable parameters to the mask register and the logic register of the logic structure from an external agent.

Abstract: A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.

Abstract: An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.

Abstract: An apparatus having: an agent; and a first test session servlet running on the agent, receiving a test description in a predetermined format from a caller, threading a first test session that invokes the agent to run the at least one subtest. The test description has at least one predefined subtest, dynamic data, and predefined test parameters. The first test session servlet receives test results from the first test session, and sends the subtest results from the at least one subtest and the dynamic data back to the caller.

Abstract: A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality of registers (26) is sourcing the debug information. A user-determinable enable and disable mechanism that is correlated to some or all of the registers sourcing the debug information specifies whether to enable or disable the providing of the debug information. In one form a single bit functions as the mechanism for each correlated register. Debug operations including breakpoints, tracing, watchpoints, halting, event counting and others are qualified to enhance system debug. The registers may be included in a programmer's model and can be compliant with one or more industry debug related standards.

Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: An SDIO card development supporting system for development of SDIO cards, an SDIO controller reference board, and a method for running the system are disclosed. The SDIO card development supporting system includes: (a) a hardware component comprising: (i) a platform equipped with an operating system and a memory operably connected to the operating system; (ii) an SD host board including an SDIO host device; and (iii) an SD bus operably connecting the operating system of the platform to the SD host board; and (b) a software component stored in the memory of the platform, wherein the software component comprises an SDIO test program that runs on the operating system of the platform.

Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.

Abstract: A system and method are described for remotely debugging an application server. In one embodiment, a plurality of application servers are organized into groups referred to as “instances.” Each instance may include a group of redundant application servers, one or more debug nodes, and a dispatcher. The dispatcher distributes service requests to each of the application servers in accordance with a load-balancing mechanism. In addition, a central message passing architecture is defined which allows the various instances to communicate with one another. In one embodiment, a debug node is isolated from the load-balancing mechanism. The debug node may also be isolated from the central message passing architecture. A remote node may then debug an application on the debug node, without disrupting processes executing on other application servers in the instance.