Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A safety controller may execute both standard and safety programs using shared architecture in which two processors symmetrically execute the safety program and check each other for errors, and one processor only executes the standard program to minimize undetected symmetrical corruption of the safety programs.

Abstract: The described program controlled unit has first supply voltage connections for applying a first supply voltage to the program controlled unit and second supply voltage connections for applying a second supply voltage to the program controlled unit. The full OCDS module or a part of the OCDS module is supplied with power by the second supply voltage. The remaining components of the program controlled unit are supplied with power by the first supply voltage. This means that the entire OCDS module or part of the OCDS module can actually be supplied with power, before the time at which the remaining parts of the program controlled unit are supplied with power. A debugger supplies the OCDS module with control information that prescribes a particular state of the OCDS module.

Abstract: The invention may relate to a method of programming a programmable non-volatile device. The programmable non-volatile device may be programmed while coupled to a circuit in which the programmable non-volatile device is to be used. The method may include establishing a connection and communicating information. The connection may be established from an external device to a test interface of the circuit. The information may be communicated from the external device through the test interface, for programming the programmable non-volatile device.

Abstract: A method for identifying service critical faults in a communications network and a network management system employing the method are provided. A service provisioning tool associated with the network management system and operating in accordance with the method, performs operations on a multitude of managed entity instances stored in a containment hierarchy associated with the network management system, the managed entity instances corresponding to managed field installed equipment. Received alarm information is used to ascribe operational states to corresponding managed entities in the containment hierarchy. Operating in accordance with the presented method, the service provisioning tool inspects low-level managed entities in the containment hierarchy and, if each managed entity of a group of low-level managed entities which provide a unitary function is “unavailable”, then the operational state of a corresponding high-level managed entity is set to the “unavailable” state.

Abstract: A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Abstract: The error-free function of modules in a bus system with a central unit is tested. First, all (error-free) modules are set into a silent operating mode in response to an agreed silence-command, and then in this silent operating mode it is tested whether all modules still remain silent, i.e. do not transmit data, in response to an agreed data request allocated to these modules. A module that nonetheless transmits data is recognized as faulty and is deactivated. Subsequently, all modules except for a module to be tested are set into the silent operating mode, and then it is tested whether this test module transmits its data in response to the agreed data requests allocated to it and remains silent in response to the data requests not allocated to it. Additionally, the position of the return-transmitted data can be determined and compared with a nominal position.

Abstract: Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.

Abstract: A data correlation technique is provided for a computing environment having multiple independent operating environments. The technique includes associating by a first operating environment a first key to a set of data to be obtained responsive to an identified event within the computing environment; obtaining by a second operating environment the set of data with the associated first key, and associating a second key therewith; and using the set of data with the associated first key and second key to match to the set of data at least one other set of data obtained by the first operating environment or the second operating environment responsive to the event. The at least one other set of data has only the first key or the second key associated therewith. In one implementation, the event is a fatal event at a network interface adapter.

Abstract: A network identification system for use in a process control system creates and stores a unique network identification tag for input/output networks in the process control system. During the configuration process, each process controller is assigned a unique controller identification tag. In addition, each input/output device installed on each process controller is assigned a device identification tag. The network identification system creates a network identification tag for an input/output network by concatenating and combining the unique controller identification tag and the device identification tag. The network identification system may be configured to periodically transmit the network identification tag or to provide the network identification tag is response to a request for identification.

Abstract: A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for testing a computing cluster having several computing nodes. Configuration information regarding a test system is received and used to generate a configuration file that profiles the test system. The configuration file may be passed to each computing machine in the test system whereupon an appropriate test suite is launched on each computing machine in the test system to perform the tests contemplated by the test suite.

Abstract: A method for executing processing tasks in a distributed processing framework system is provided. The method includes identifying a main task of a tasklist and identifying a subtask of the main task. Also included is allocating computing resources for each of the main task and the subtask. The method further includes deploying the main task to a first computing system that is part of the distributed processing framework system. A code of the main task is executed on the first computing system. The code of the main task has program instructions for requesting loading of code for the subtask to a second computing system. The second computing system is part of the allocated computing resources. The code for the subtask is in client-server communication with the code for the main task, such that the code for the main task receives processing results directly from the code for the subtask.

Abstract: A method and mechanism for detecting interconnect and bridge defects. Contact points in a chip are assigned placement designation such that no two adjacent points have the same designation. A transmitter, receiver, and optional transmitter/receiver test are then run. During the transmitter test, transmitters with a given designation drive a particular test pattern while other transmitters drive a different test pattern. Receivers compare received test patterns against expected patterns. During a receiver test, transmitters drive a test pattern corresponding to the placement designation of the receivers to which they are coupled. During a particular receiver test, transmitters coupled to receivers of a given designation drive a particular stream, while other transmitters drive a different stream. Receivers then compare received streams against an expected stream.

Abstract: A method for checking a microprocessor for correct operation, the microprocessor having a plurality of gates, each having a plurality of transistors, in which during the intended running of a computer program on the microprocessor a self-test is cyclically executed, and as part of the self-test, gates in the microprocessor are checked for correct operation. In order to check the microprocessor for correct operation in such a way that the functional check is able to detect at an early stage such errors which occur only during the intended operation of the microprocessor, and to the extent possible not to make use of models of the open-loop or closed-loop control algorithms, at least those gates of the microprocessor whose state has an impact on the intended running of the computer program on the microprocessor are checked during one run of the self-test.

Abstract: A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

Abstract: A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating system are coupled together by a network (220) to form the local network groups. The independent processing systems may have more than one CPU (202). One or more of the independent processing systems may share power, cooling and a housing, thereby forming a common fault processor group (200). An application is written to execute across multiple independent processing systems and common fault processor groups. That is, the application runs in many instances that each run on independent processing systems. The multiple instances of the application provide some measure of high availability by using N+K sparing or the like. The application is for example, call processing or radio control. A processor notification list (304) keeps track of the independent processing systems that cooperatively provide an application.

Abstract: An emulator is provided on an electronic assembly that permits external logic to communicate with test logic on the electronic assembly over an electrical interface that has fewer signals than the electrical interface associated with the test logic itself. In this way, external logic can communicate with test logic on the electronic assembly over an interface that uses fewer signal lines thereby permitting the electronic assembly's electrical connector to be smaller than it otherwise would be. In accordance with one embodiment, the test logic's interface comprises a JTAG interface having four signals (with an optional fifth signal) and the interface between the emulator and the external logic comprises a two wire SMBus communication link. In fact, the SMBus interface may already be provided to the electronic assembly for other reasons such as to provide control to and obtain status information from another component on said electronic assembly.

Abstract: A disc array device receives a hardware diagnosis after shipment of the disc array device at short times during an operation of the device and a diagnostic rate is enhanced and an internal failure of a LSI can be detected at a device level. By at least one MP of a redundant-constitution channel interface control adaptor, a hardware diagnosis of a part in a channel interface control adaptor is made, and hardware diagnoses of a part in a CACHE and a part in a cache path switch are made through a diagnostic interface. By at least one MP of the redundant-constitutional disc drive interface control adaptor, a hardware diagnosis of a part in the disc drive interface control adaptor is made, and hardware diagnoses of a part in the CACHE and a part in the cache path switch are made through a diagnostic interface.

Abstract: A method and system that enables a service processor to program a system resource. The service processor uses a JTAG Bus to request a system processor to enter into probe mode. Once in probe mode, the service processor sends a signal with instructions to the system processor. Upon execution of the instructions by the system processor, the executed instructions are forwarded to the appropriate address through a host bus and a controller. The service processor may forward instructions to any system resource through the system processor.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

Abstract: The present invention relates a system adapted to localize and remove software type errors comprising a microcontroller (10) and storing means (11), said microcontroller (10) being connected to said storing means (11) by a serial type bus (12), characterized in that said system comprises a first (20) and a second (14) converter, said first converter (20) being inside said microcontroller (10) and said second converter (14) being inside said storing means (11), said first (20) and second (14) converter being connected by means of said serial type bus (12), said storing means (11) being outside said microcontroller (10), said microcontroller (10) adapted to transmit and to receive data with said storing means (11) by means of said first (20) and second (14) converter.

Abstract: A method, system, and apparatus are provided for performing a diagnostic test on one or more managed system elements. The system includes a managed system element upon which the diagnostic test may be performed, a diagnostic setting object, and a diagnostics control module. The diagnostic setting object is derived from an industry-standard diagnostic setting object prototype and includes one or more properties specified by the prototype and a device-specific settings property identifying one or more settings for the diagnostic test specific to the managed system element. The diagnostics control module performs the diagnostic test on the managed system element and customizes the test according to the device-specific settings property in the diagnostic setting object.

Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.

Abstract: A method and system for testing a microprocessor. The method includes executing debug application software on an external device, downloading diagnostic program instructions from the external device to a cache memory within the microprocessor via a serial test interface. Once the diagnostic program instructions are loaded into the cache memory, the method includes executing the diagnostic program instructions from within the cache memory.

Abstract: A computer system compnses a processor (2), memory (4) and a plurality of devices (6, 8, 12), the processor (2) and the memory (4) being operable to effect the operation of a fault response processor (AFR), and a device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices. The fault response processor (AFR) is operable to generate a model which represents the processor (2), the memory (4) and the devices (6, 8, 12) of the computer system and the inter-connection of the processor (2), memory (4) and the devices (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL). The device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices (6, 8, 12) is arranged, consequent upon a change of operational status of the device, to generate fault report data indicating whether the change of status was caused internally within the device or externally by another connected device. The devices of the computer system may be formed as a plurality of Field Replaceable Units (FRU).

Abstract: A computer management system attains, through one line, the uniform and steady system management through an agent such as monitoring of fault and power control in a computer connected by LAN as well as a public line, and system management for an off-state of the computer or abnormal operation state of the computer such as remote power control and notice and diagnosis of critical fault by the direct connection with a service processor through the line.

Abstract: A circuit for testing a chip. The chip has an intellectual product circuit module, and the circuit has a multiplexer controller, several registers and a MUX finite state machine controller to configure these registers in different states according to the test patterns. In the next state, a test activating signal is provided to the intellectual product circuit module. The intellectual product circuit module is then operated and tested according to the output of the registers.

Abstract: A computer server architecture and diagnostic framework for testing same is described. The diagnostic infrastructure consists of various logical modules present on both service processor-side and platform-side regions of a server. These modules work together to present a modular, extensible yet unitary diagnostic framework. The invention permits dynamic operation of information resources, and extensibility when/if expansion is needed. The server architecture includes an OS independent, custom ASIC and processors configured in a 4-way geometry which permits scalable expansion up to a 16-way configuration geometry within a SMP programming model. The server architecture is capable of integration with third party management frameworks, for example, SNMP and CIM, and is modularly scalable, i.e., offers a “one to many” management capability.

Abstract: A system for providing simultaneous, real-time trace and debug of a multiple processing core system on a chip (SoC) is described. Coupled to each processing core is a debug output bus. Each debug output bus passes a processing core's operation to trace capture nodes connected together in daisy-chains. Trace capture node daisy-chains terminate at the trace control module. The trace control module receives and filters processing core trace data and decides whether to store processing core trace data into trace memory. The trace control module also contains a shadow register for capturing the internal state of a traced processing core just prior its tracing. Stored trace data, along with the corresponding shadow register contents, are transferred out of the trace control module and off the SoC into a host agent and system running debugger hardware and software via a JTAG interface.

Abstract: A distributed computer-implemented diagnostic system for determining a diagnostic state of a component. The component exhibits measurable characteristics. The system includes a database that stores reference component characteristic data. A computer server is connected to the database, and a computer client is connected to the computer server via a network. The client computer provides data requests to the server computer in order to retrieve the component characteristic data from the database. A portable computer is connected to the computer client in order to have data access to the retrieved component characteristic data and to provide the component characteristic data for performing diagnosis. The diagnostic state of the component is determined based upon the retrieved component characteristic data as provided by the portable computer and upon at least one of the measurable characteristics of the component.

Abstract: Disclosed are novel methods and apparatus for efficiently providing concurrently programmable dynamic memory built-in self-testing (BIST). In an embodiment of the present invention, a method of utilizing a BIST system is disclosed. The method includes: loading setup data into a configuration register; loading a first instruction into a shift register; loading the first instruction into an update register; executing the loaded first instruction to perform a memory test; upon receiving a first update command, loading a second instruction into the shift register; and upon receiving a second update command, loading the second instruction into the update register.

Abstract: A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one instruction by a processor. The first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked when the processor is operating in a debugging mode.

Abstract: At the time of a backup process of the sharing disk in a disk shared file system, the write cache of each computer is reflected on a sharing disk, and data of the sharing disk is copied in a backup medium as a batch. Further, blocks to be backed up are listed to be copied in the backup medium as a batch. Then, the log of each computer is stored in a log medium, and the data at the start point of a backup process is formed using the log.

Abstract: An apparatus and method is provided for auditing the configuration of an enterprise comprising the steps of: collecting information relating to the configuration of the enterprise, analyzing the configuration information based on expert knowledge; and providing the result of the analysis in the form of reports, and other results of the analyses.

Abstract: A system and method for debugging a program which is intended to execute on a reconfigurable device. A computer system stores a program that specifies a function, and which is convertible into a hardware configuration program (HCP) and deployable onto a programmable hardware element comprised on the device. The HCP is generated based on the program, specifies a configuration for the programmable hardware element that implements the function, and further specifies usage of one or more fixed hardware resources by the programmable hardware element in performing the function. A test configuration is deployable on the programmable hardware element by a deployment program, where, after deployment, the programmable hardware element provides for communication between the fixed hardware resources and the program. The program is executable by a processor in the computer system, where during execution the program communicates with the one or more fixed hardware resources through the programmable hardware element.

Abstract: A semiconductor device, such as a multiprocessor chip for a computer system, includes a total number of on-board components which is greater than the number of that component required by the system. The chip may be provided with multiple I/O controllers, e.g. more than one controller per I/O interface, and the I/O controllers can act as backups to one another, with failover logic controlling the backup process. In addition, the number of processors formed on the chip may be greater than the number required by the system, allowing multiple levels of redundancy and greater successful manufacturing yields.

Abstract: A method, apparatus, and computer implemented instructions for saving data in a logically partitioned data processing system. An error is detected in the logically partitioned data processing system. Data needed for error analysis of the error is saved in a power independent memory associated with a service processor.

Abstract: An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be configured to (i) couple the trace circuit to the selected processor in response to a select signal and (ii) transfer the information from the selected processor to the trace circuit while the selected processor is executing the software.

Abstract: Debug information is delivered over a general purpose interface. The debug information is delivered in packet format. These packets are referred to as Debug Event Packets (DEP). The debug event packets include a number of debug event bits that if set denote the occurrence of run-time programmable (selectable) debug events. The debug information packet also may include a debug parameter byte that allows one device to pass extra debug information to another device. The debug parameter byte may be associated with one of the debug event bits. The transfer of the debug event packets occurs in-band.

Abstract: A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

Abstract: The present invention, in various embodiments, provides techniques for testing devices. In one embodiment, the device under test is a chip including a plurality of processors and a memory structure that stores test programs. One or more processors executes the test programs and generates test results based on which the chip may be determined good or bad. In one embodiment, the processors execute the test programs independent of each other, and no external hardware and/or test controller is required during the test phase. Various embodiments include a first processor that controls the scan chain of a second processor; the test results of the first processor are used as inputs for testing the second processor, etc.

Abstract: When a built-in nonvolatile memory in a microcomputer is tested, a control program prestored in a boot ROM is run upon entering a test command from an external communication device; a test program is transferred from the external communication device to a built-in RAM through a communication circuit; a control of a CPU is switched to the built-in RAM after the test program has been transferred and a test is conducted on the nonvolatile memory; and a test result and a fail log are transferred to the external communication device through the communication circuit. Consequently, the built-in nonvolatile memory in the microcomputer can be checked without leaving the test program on the chip.

Abstract: A system analyzer for a data storage system has a control module and a memory module. The system analyzer includes a logic analyzer, an input port that couples to the data storage system, an output port that couples to the logic analyzer, and a pre-processor which is interconnected between the input port and the output port. The pre-processor is configured to receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal. The pre-processor is further configured to generate a pre-processed signal based on the second point-to-point signal, and to provide the pre-processed signal to the logic analyzer.

Abstract: A system and method for monitoring a host computer using a service processor is provided. A shared nonvolatile random access memory (NVRAM) area is used to store progress information from the host computer system. The host computer system writes progress information corresponding to the initialization step being performed to the shared NVRAM and also updates a host pointer in the NVRAM. The service processor reads the shared NVRAM and compares its pointer with the host pointer to determine whether new host initialization activity has been reported. The service processor sets a timer so that if host activity is not reported during a set amount of time an error condition occurs causing the service processor to handle the host computer error. An optional service processor routine determines whether the host computer is stuck in an initialization loop whereupon the service processor once again handles the host computer error.

Abstract: A computer-implemented method for monitoring a computer system when the computer system executes a user application using a production operating system (OS) is disclosed. The method includes providing a diagnostic monitor, the diagnostic monitor being configured to be capable of executing even if the OS kernel fails to execute, the diagnostic monitor having a monitor trap arrangement. If a trap is encountered during execution of the user application, the method includes ascertaining using the diagnostic monitor whether the trap is to be handled by the OS kernel or the diagnostic monitor. If the trap is to be handled by the OS kernel, the method includes passing the trap to the OS kernel for handling.

Abstract: A system where a production microcontroller is partially copied in a FPGA of an ICE to form a virtual microcontroller. The virtual microcontroller and the production microcontroller simultaneously and independently run a microcontroller code to be debugged at a high frequency. The debugging logic can substantially reside in the ICE and the ICE can perform all debugging functions. The debug interface, residing in the production microcontroller, can enable the production microcontroller to communicate with the ICE in low frequencies. The production microcontroller may request the ICE to lower its frequency when the production microcontroller encounters a halt due to outside events. A user may command resumption of the operation of both the production microcontroller and the virtual microcontroller when debugging of the codes is completed.

Abstract: A method for using an operating system device for non-operating system uses. A false event signal is generated to indicate that a device should be shut down. After this is accomplished, the device is used for a different purpose while the operating system thinks it is inoperative. Once the other use is completed, another false event signal is generated so that the device is activated again and returned to use in the operating system in normal fashion.

Abstract: Techniques for managing data objects in conjunction with a computer system are provided. In a technique for clustering data objects on a disk storage device, the invention comprises maintaining a log of at least a portion of accesses (e.g., read and for write operations) to the data objects; determining from the maintained log a cluster comprised of data objects accessed at substantially similar times; and storing the data objects comprising the cluster in close proximity to one another on the disk storage device. In a technique for prefetching data objects on a disk storage device, the invention comprises receiving a request for a data object in a cluster, determining from the log a probability that at least one other data object in the cluster may be subsequently requested; and, in response to the probability being not less than a predetermined value, retrieving both the requested data object and the at least one other data object.