Abstract: A system recovery method and an apparatus supporting the same are disclosed. A software image is downloaded, and a system is loaded with the downloaded software image, and the system is recovered by a software image used before the updating, if the system loading fails.

Abstract: A pilot process method for system boot and an associated are provided. An environment variable is read from a NAND flash memory. When an irrevocable error exists in an environment variable, the environment variable is read successively for a predetermined threshold number of times. A backup variable of the environment variable is read when the irrevocable error is still present in the environment variable that is read for a predetermined threshold number of times, and the environment variable is restored according to the backup variable. Therefore, when it is confirmed that the environment variable is damaged, a backup variable is utilized and the damaged environment variable is restored according to the backup variable, so as to ensure a normal boot-up process of the system to significantly enhance system reliability as well as user experience.

Abstract: A booting method and an apparatus thereof for debugging in a portable terminal are provided. The method includes, when a booting event occurs, stacking a boot loader in a preset boot loader region of a Random Access Memory (RAM), and executing, and stacking an Operating System (OS) in a preset OS region of the RAM, wherein the boot loader region and the OS region of the RAM are set such that they do not overlap each other.

Abstract: Systems and methods for testing non-volatile storage devices are disclosed that provide functionality to control when testing of the non-volatile storage device is performed. In one embodiment, information stored in persistent memory indicates whether testing is enabled or disabled. For example, the testing information may indicate that testing is to be performed upon a first initialization of a non-volatile storage device, but not in connection with subsequent power-up events. Furthermore, functionality is disclosed for re-running and/or bypassing testing of the non-volatile storage device.

Abstract: A connector can be activated or deactivated by providing power and data signals to the connector at different times. In some embodiments, the power signals are provided to a connector, and then the data signals are provided to the connector after a delay. Providing power and data signals at different times can, in at least some cases, better mimic the timing of signals provided by a connector as the connector is attached to an electronic device. This can aid automated testing of the electronic device. It can also be used to control access of the device through the connector.

Abstract: A method for resetting a system to factory default settings is provided. The method includes: disconnecting-connecting a power source repeatedly; detecting whether a count value of disconnecting-connecting the power source has exceeded a predetermined value; and triggering a procedure of resetting the system to factory default settings when the count value has exceeded the predetermined value.

Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

Abstract: One processor core of a plurality of processor cores that are included in a multi-core processor that processes a request from an external device detects a prescribed event, specifies a sub resource that is assigned to the one processor core based on the resource management information that indicates a sub resource of a plurality of sub resources that are included in a physical resource and a processor core that is assigned to the sub resource, and executes a reboot based on the specified sub resource.

Abstract: A method for diagnosing an apparatus in a computer system, which includes: determining to enter a diagnostic mode after the computer system is started; initializing a cache in the computer system; after initializing the cache, performing a diagnosis of the apparatus by executing a diagnostic program; and after the diagnosis of the apparatus is completed, executing a Basic Input Output System (BIOS) or Extensible Firmware Interface (EFI) program and loading an operating system.

Abstract: An information handling system includes a memory, a processor, and a management controller. The memory includes code to implement a power on self test (POST). The management controller operates to receive an indication that the POST has halted execution in response to a POST error, to log the indication and the POST error, and to send an input to the POST. The POST operates to receive the input and to continue execution based upon the input.

Abstract: A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.

Abstract: A method for performing a set of diagnostics on a host system using a service processor. The method includes recognizing a power-on event, and in response checking a diagnostic flag, where the diagnostic flag indicates the set of diagnostics to be performed. Retrieving, from internal storage of the service processor, a disk image including the set of diagnostics to be performed. Mounting, using a disk image reader, the disk image to obtain a mounted disk image. Making the mounted disk image accessible as a device using a virtual device driver. Mounting, using a connection between the service processor and the host system, the device within the host system, and performing the set of diagnostics on the host system.

Abstract: A BIOS circuit for a computer includes a baseboard management controller (BMC), a central processing unit (CPU), a main basic input-output system (BIOS) storage, and a subsidiary BIOS storage. Both the main BIOS storage and the subsidiary BIOS storage store programs for controlling the computer. The CPU executes the programs stored in the main BIOS storage to control the computer. When data of the programs stored in the main BIOS storage is missing or corrupted, the BMC copies data of the programs stored in the subsidiary BIOS storage to the main BIOS storage to recover the missing or corrupted data in the main BIOS storage.

Abstract: Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies.

Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Abstract: A method for preheating an electronic system when booting in an environment with low temperature and an apparatus using the same are provided. The electronic system includes at least a processor, at least a first controller, and at least a second controller. The method includes: the first controller checking whether the initialization of the second controller is successful or not after the electronic system boots, wherein the first controller include a basic input/output system; entering a preheating mode when the initialization of second controller has failed, wherein in the preheating mode, the processor is powered continuously and a turbo function is enabled, so as to provide a heat energy for heating the electronic system; and stopping the preheating mode and rebooting the electronic system.

Abstract: A debug device is presented, which is applicable to a server having a control chip. The debug device includes a receiving unit, a retrieving unit, an analyzing unit, and a processing unit. The receiving unit is coupled to the control chip and is used for receiving a boot detection signal (BDS). The retrieving unit is coupled to the receiving unit and is used for receiving the BDS through the receiving unit and retrieving an information code of the BDS. The analyzing unit has a lookup table, is coupled to the retrieving unit, and is used for receiving the information code, using the lookup table to analyze the information code and generating an analysis result. The processing unit is coupled to the analyzing unit and is used for receiving the analysis result and generating a processing signal according to the analysis result.

Abstract: A system and method is disclosed for recovering a boot image from a secure location. Hardware instructions initiate a sequence of boot cycles to launch a computer operating system on a computer-enabled device. During the boot cycles, multiple levels of boot code are verified and a determination is made whether each level is usable by the device. If a level of boot code is determined to be unusable, a secure copy of the boot code is loaded from a secure read-only location to repair the unusable code to launch the computer operating system.

Abstract: A debugging method for a computer system is disclosed, which includes defining a debug reference data area in a storage device for a BIOS and a control device, periodically transmitting a reply request including an identification information to the BIOS, transmitting reply information corresponding to the identification information according to the reply request, checking the reply information and storing an execution log data into the debug reference data area when the identification information does not conform to the original identification information, determining whether the computer system is in normal operation, and performing a debugging process according to the execution log data when the computer system is in abnormal operation.

Abstract: A system and method for correcting a boot error is disclosed. The system comprises a solid-state nonvolatile memory device, the solid-state nonvolatile memory device storing a boot loader at a predetermined block having a first address on the solid-state nonvolatile memory device. The system further comprises a main controller that retrieves the boot loader from the predetermined block upon powering up. The system also includes a monitoring module configured to monitor an initial boot sequence of the main controller and to determine when the predetermined block has a read inability error. The main controller obtains a backup boot loader from a backup block when the monitoring module determines that the predetermined block is corrupted.

Abstract: A method for processing booting errors for a computer having multiple voltage regulator downs (VRDs) includes reading a boot sequence including multiple power-on stages, and each power-on stage corresponds to a boot voltage and one of the VRDs; performing the power-on stages according to the boot sequence, and determining whether an output voltage of the VRD corresponding to each power-on stage is equal to the corresponding boot voltage; and when the output voltage of any one of the VRDs is not equal to the corresponding boot voltage, performing a debugging procedure.

Abstract: Test coverage is enhanced by measuring various types of coupling between coverage tasks. The coupling measurements may be implicit coupling measurements, explicit coupling measurements, coding coupling measurements, performance coupling measurements, resource coupling measurements or the like. Coupling scores are calculated for coverage tasks and based thereon ranking of the coverage tasks or groups of coverage tasks may be determined The ranking may be utilized in selecting for which uncovered coverage task a test should be designed. The ranking may be utilized in computing a coverage measurement of a test suite. The ranking may be utilized to rank tests, based on the coverage tasks each test covers. Ranking of tests may be utilized for various purposes such as performing test selection.

Abstract: Test coverage is enhanced by measuring various types of coupling between coverage tasks. The coupling measurements may be implicit coupling measurements, explicit coupling measurements, coding coupling measurements, performance coupling measurements, resource coupling measurements or the like. Based on the coupling measurements, different coverage tasks may be grouped together. For example, closely coupled coverage tasks may be grouped together. The groups may also be determined based on an initial distribution of groups, by combining groups having closely coupled member coverage tasks. The groups may be ordered and prioritized, such as based on the size of the groups and the number of uncovered tasks in each group. The groups may also be ordered, such as based on coupling score which aggregate the coupling measurements of the member coverage tasks.

Abstract: A system is used for acquiring Basic Input/Output System (BIOS) debug codes. The system includes a platform controller hub (PCH), a storage chip, and a baseboard management controller (BMC). The PCH reads power-on self tests (POST) codes from an address port of a bus, and converts the POST codes to binary data and stores the binary data in the storage chip. The BMC reads the binary data stored in the storage chip and defines the binary data as virtual sensor data, which conform with threshold type data, and decodes the virtual sensor data to POST codes and controls a display unit to display the POST codes.

Abstract: The present invention relates to a debugging apparatus for a computer system and a method thereof. A detecting unit detects if a debugging unit connects to the computer system. When a debugging unit connects to the computer system, the detecting unit produces a detecting signal, which contains information of a bus in the computer system electrically connected with the debugging unit. Then a selection unit selects the bus electrically connected with the debugging unit according to the detecting signal. Besides, a testing unit tests the computer system and produces a power-on self-test (POST) code, so that the selected bus can be used for outputting the POST code to the debugging unit. Thereby, the present invention can choose to use the bus reserved in the computer system for outputting the POST code to the debugging unit, and hence facilitating inspection personnel to debug the computer system.

Abstract: A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes receiving a first test data, which identifies a state of a state machine, wherein the state machine performs reset and initialization operations for a processor. The method also includes halting the state machine in the state identified by the first test data upon reaching the state.

Abstract: According to an embodiment, a management apparatus includes a management table, a control unit, a module timer, and a judgment unit. The control unit controls an order of executing modules based on an execution order described in a management table. The module timer measures the execution time of each running module. The judgment unit writes real execution time in the management table when the real execution time at the end of the exertion is equal to or shorter than the expected execution time. Otherwise, the judgment unit writes a flag for defective condition in the management table when the real execution time is longer than the expected execution time. When a flag for defective condition is written in the management table, the control unit stops the execution of the running module and starts the execution of the next module.

Abstract: A disc stores therein a computer program and encrypted information. A BIOS is executed at the time of start-up and starts the computer program. A TPM is connected to the BIOS by a low-speed bus. The TPM includes a register for storing data. A blob stores therein true hash values of the computer program and the BIOS in advance. The BIOS includes a hash value calculating unit that calculates hash values of the computer program and the BIOS and stores those hash values in the register. The TPM compares the hash values stored in the register with the hash values stored in the blob and decrypts information in the blob if the hash values agree with each other.

Abstract: A system for testing a network switching apparatus includes one or more port connections external to the network switching apparatus. The one or more port connections are configured to interconnect selected ports of the network switching apparatus to transfer packets between the selected ports. Further, the system includes a test manager configured to automatically generate a plurality of test scenarios for testing a processing operation to be performed by the network switching apparatus on packets. The test scenarios define paths for forwarding packets multiple times among the ports of the network switching apparatus. The system also includes a packet generator configured to transmit packets to at least a first port of the network switching apparatus to test a processing operation performed by the network switching apparatus.

Abstract: A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address.

Abstract: An information processing apparatus includes a process monitor configured to monitor the status of processes executed in accordance with respective monitored driver programs which are to be monitored among driver programs associated with respective devices, an error processor configured to operate when a processing error is detected by the process monitor, to register, in a nonvolatile memory, driver information indicating the driver program with respect to which the error has been detected, and an execution controller configured to call and execute the driver programs, wherein when the information processing apparatus is started, the execution controller skips execution of the driver program indicated by the driver information registered in the nonvolatile memory.

Abstract: An apparatus and method for determining an abnormal ROM update in a portable terminal. The apparatus includes a ROM update unit for increasing a value of an update start counter when a ROM update process is performed, and increasing a value of an update finish counter when the ROM update process is finished. The ROM update unit loads the values of the update start counter and the update finish counter, and compares the values of the two counters to determine that the ROM update process has been normally performed before the portable terminal abnormally operates.

Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.

Abstract: A server testing system is used for testing servers of a server system and includes a power source, switches, a connection device, a controlling device, and a display device. Each switch is connected to the power source and the controlling device. The controlling device is connected to the connection device and the display device. The controlling device controls each switch to connect a corresponding server to the power source. When receiving a feedback signal from a server, the connection device sends a status signal to the controlling device. The status signal triggers the controlling device to control a corresponding switch to disconnect and then connect the server to the power source. The controlling module controls the switches to turn each server on and off for a predetermined number of times and controls the display device to display a warning when a server is not working normally.

Abstract: A computer turning on/off testing apparatus for turning on a computer automatically includes a control module, a switch module, and a power supply module. The control module outputs control signals and receives a turn on signal from the computer to determine whether the computer turns on successfully. The switch module receives the control signals and turns on/off the computer according to the control signals. The power supply module provides power to the control module and the switch module. The control module stores a predetermined test time. The control module records abnormal information and test times when the computer turns on/off, and outputs the control signals to turn on the computer again when the computer cannot restart. The computer is turned on and off until a turning on/off time of the computer is equal to the predetermined test time.

Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.

Abstract: The present invention is aimed to provide means and methods for recovery of an IP Multimedia Subsystem ‘IMS’ where a Home Subscriber Server ‘HSS’ holding subscriber data for subscribers of the IMS has suffered a restart. A first method of recovery is applied after detecting a HSS restart, and as receiving a registration from a given subscriber or an invitation to communicate with a given subscriber from another subscriber. A second method of recovery is applied after detecting a HSS restart, and as receiving a request from a given subscriber at a S-CSCF previously assigned for serving the given subscriber in the IMS.

Abstract: A mobile terminal for reporting an exception or error and a method thereof, by which an exception of the mobile terminal can be transmitted to a server in a transmission mode appropriate for a status of a network. Exception information, such as information of a register of the mobile terminal if the exception is generated, information of a task performed by the mobile terminal before the generation of the exception, and history information before the generation of exception, are stored in a memory. The exception information is transmitted to the server.

Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.

Abstract: A display device is coupled to a computer, and the computer accommodates a motherboard. The display device includes an interface unit connected to the motherboard, a display panel, and a processor electrically coupled to the interface unit. The processor is used to: receive a power-on self test (POST) code from the motherboard via the interface unit, convert the POST code into a debug code, and control the display panel to display the debug code.

Abstract: A way for securely protecting secret information—for example, a secret key—in a programmed electronic device is provided. A technique is disclosed for protecting secret information in a programmed electronic device that includes a non-trusted memory containing software, a data memory containing the secret information, and an access restriction logic unit that is adapted to allow or block access to the secret information wherein the secret information is adapted to be used for verifying the integrity of the software. In one embodiment, when starting up the programmed electronic device, the access restriction logic unit allows access to the secret information. Then the secret information is accessed for use in verifying the integrity of the software, and subsequently the access restriction logic unit blocks further access to the secret information. Embodiments of a semiconductor device and a programmed electronic device comprising similar features are also disclosed.

Abstract: A method, system, and computer usable program product for identifying a defective adapter are provided in the illustrative embodiments. A configuration process of the adapter is initiated, the adapter being coupled with a slot in a data processing system. An indication of the configuration process is activated. A determination is made whether the configuration has completed successfully. The indication is allowed to remain activated responsive to the configuration not completing successfully. The activated indication identifies the defective adapter.

Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.

Abstract: A computer startup test apparatus for turning on a computer automatically, includes a control module, a switch module, and a startup module. The control module is configured to output control signals, data signals and clock signals. The switch module is configured to receive the control signals, and turn on the computer according to the received control signals. The startup module is configured to receive the data signals and clock signals, and restarts the computer according to the received data signals and clock signals. The control module stores a predetermined test time. The control module records abnormal information and test times when the computer restarts, and outputs the control signals to turn on the computer using the switch module when the computer cannot restart.

Abstract: A system and method provide for integrating a Basic Input/Output System (BIOS) Read-Only-Memory (ROM) image. A method includes but is not limited to opening a BIOS modification application; opening a target BIOS binary image within the BIOS modification application; and adding an electronic security and tracking system and method (ESTSM) ROM image to the target BIOS binary image.

Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Abstract: Administering computer processor execution of BIOS code that includes a primary BIOS code and a recovery BIOS code stored in ROM, the ROM operatively coupled to a control module and the processor, where administering processor execution of the BIOS code includes determining, by the control module, a size of the ROM; generating, by the control module in dependence upon the size of the ROM, an address for the primary BIOS code and an address for the recovery BIOS code; starting, by the control module, operation of the processor for execution of the primary BIOS code including providing, to the processor, the address for the primary BIOS code; and if executing the primary BIOS code fails, restarting, by the control module, operation of the processor for execution of the recovery BIOS code including providing, to the processor, the address for the recovery BIOS code to the processor.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.