Abstract: Techniques for recovering data from cold images are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer implemented method for recovering data from cold images comprising searching storage associated with a target recovery device, identifying one or more data structures on the storage, parsing the one or more identified data structures, and recovering one or more portions of the one or more parsed data structures.

Abstract: A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S105, S106) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S109) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S106, S103) and determines once again that the block is faulty or not faulty.

Abstract: The routines to be called by the dispatching function are identified based on the contents of description files associated with the child modules containing the routines to be called. Once the routines to be called by the dispatching function have been identified, an initialization source file is generated that includes source program code for calling each of the identified routines. Once the initialization source file has been generated, the parent program module is built by compiling the individual routines to generate object code and then linking the compiled files to generate the parent program module. The resulting executable parent program module includes the proper calls to execute the identified routines.

Abstract: Operating system (‘OS’)-firmware interface update recovery including determining, for each of a plurality of available OS-firmware interface images for booting a computer, whether each available OS-firmware interface image is corrupted or uncorrupted; setting, for each corrupted OS-firmware interface image, a predictive failure analysis (‘PFA’) bit in nonvolatile memory available to the OS-firmware interface update recovery module; selecting an uncorrupted OS-firmware interface image; initiating a boot for the computer with the selected OS-firmware interface image; determining whether a previous update to one of the available OS-firmware interface images was interrupted; and notifying a user that the previous update was interrupted if the previous update to one of the available OS-firmware interface images interrupted.

Abstract: The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.

Abstract: Provided is a file server providing a file service to a host computer, including an interface coupled to the host computer; a processor; a memory; and an interface coupled to a disk drive. The file server is configured to calculate a capacity of storage areas in the memory, which is required to provide the file service; execute a first memory check in which the storage areas having the calculated capacity are tested; execute, after the first memory check is completed, a second memory check in which remaining storage areas in the memory are tested; and start, in a period after the first memory check is completed and before the second memory check is completed, providing the file service.

Abstract: A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.

Abstract: A method for automatically simulating manual testing of a computer after the computer is powered on includes the steps of: (a) connecting the computer to an external storage device having a script recorded thereon that corresponds to a manual testing operation; and (b) after the computer is powered on, enabling the computer to access the script of the external storage device for performing the manual testing operation. By providing automatic simulation of manual testing of a computer after the computer is powered on, time and labor costs incurred in a conventional method of manually inputting instructions required for the manual testing operation in the computer are saved.

Abstract: A method for controlling a boot sequence of a server includes the following steps. A boot image is created, and a first proxy server program is placed into the boot image. The first proxy server program communicates with a management server. The boot image is restored on a rewritable removable storage device, so as to enable the rewritable removable storage device to boot a managed target server. A second proxy server program is installed and executed in the management server. A basic input/output system (BIOS) of the target server is set to enable the rewritable removable storage device to act as a first boot device. Boot files in the rewritable removable storage device are modified through the first proxy server program or the second proxy server program according to a boot instruction received from the management server, thereby controlling a boot sequence of the target server.

Abstract: A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repair locations to be stored within one or more storages. In response to initiation of a power-down state of a given processor core, the given processor core may execute microcode instructions that cause the information from the one or more storages to be saved to a memory unit. During a recovery of the given processor core from the power-down state, the processor core may execute additional microcode instructions that cause the information to be retrieved from the memory unit, and saved to the one or more storages. The repair unit may restore repairs to the locations in the cache memories using the information.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: In the information process device 1, the fault inspection program is stored in the fault inspection program area 13b of the ROM 13 provided on the mother board 11 which is independently arranged from the hard disk 24, thereby even if a fault occurs in the hard disk 24 which is inspected by the fault inspection program, it can be guaranteed that the fault inspection program properly operates.

Abstract: A triggered restart mechanism for failure recovery in power over Ethernet (PoE). Powered devices (PDs) that fail can be remotely recycled by a power sourcing equipment (PSE). After detection of a failure of a PD, such as by the failure to receive a status message, a PSE can generate a reset signal (e.g., power cycle, reset pulse, etc.) on the port. This reset signal can cause the PD to perform a full power cycle or quick restart.

Abstract: Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error.

Abstract: A memory controller, a method of testing memory power management modes in an integrated circuit and an integrated circuit. In one embodiment, the memory controller includes a power management mode test controller couplable to a test access port and at least one memory core and configured to respond to a signal provided via the test access port by providing an ordered signal-setting sequence to the at least one memory core to cause the at least one memory core to enter into and exit from at least one memory power management mode.

Abstract: A timer circuit and a timer method are provided for a BIOS of an electronic device. The timer circuit includes a processing module, a setting module, and a display module. The processing module includes a microprocessor unit (MCU), a clock circuit 20, and a reset circuit. The timer circuit electronically connects with a debug card to measure a running time of a procedure of the BIOS of the electronic device. A timer result of the measurement is displayed on the display module.

Abstract: According to one embodiment of the present disclosure, a method for testing a boot image is disclosed. The method comprises creating a test boot image for a first logical partition, creating a second logical partition wherein the second logical partition is a duplicate of the first logical partition, initiating a boot sequence for the second logical partition using the test boot image, and returning a result of the boot sequence to a requestor.

Abstract: A BIOS switching system applicable to a computer system is provided. The BIOS switching system includes an input module and a memory module, and the memory module further includes a plurality of BIOS's, an option recording block, and a boot-up management block. The input module produces a switching signal according to a user input. The boot-up management block determines whether replacing an execution option block's data in the option recording block is necessary or not based on the switching signal. The data of the execution option block is identification data of one of the BIOS's. The boot-up management block executes the BIOS indicated by the data of the execution option block while the computer system boots up.

Abstract: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time.

Abstract: A system and method for encoding and decoding data. A method includes selecting a subgroup of bits from one or more bytes of binary encrypted information, wherein the binary encrypted information is for tracking, locating, and disabling an electronic device; passing the subgroup of bits to an encoding function that performs binary mapping operations on the subgroup of bits to generate an encoded byte; and encoding the next one or more bytes of binary encrypted information if the end of the binary encrypted information has not been reached.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A bootable restoration computer includes: at least one mass storage device; at least two mass storage device partitions in the at least one mass storage device, including first and second partitions; a partition image restoration program; at least one partition image; at least one human interface device; a primary operating system with graphical user interface; a secondary operating system; and, a boot loader responsive to the human interface device that provides for selecting between the primary secondary operating systems. The primary operating system resides on the first partition and is configured so that its standard locations for storing user-created files are folders rooted on at least one of any partition other than the first partition. The at least one partition image is an image of the first partition, and resides on at least one of any partition other than the first partition.

Abstract: A booting system includes: a non-XIP memory, for storing a plurality of booting images, wherein the booting images comprise a source image and a plurality of duplicates of the source image; an XIP memory, coupled to the non-XIP memory; and a code shadowing module, coupled to the non-XIP memory and the XIP memory, for shadowing a specific booting image to the XIP memory if no errors are detected when carrying out error detection (EDC) checking on the specific booting image; wherein if at least a specific part of a booting image does not pass EDC checking, the code shadowing module shadows error-free parts of the booting image to the XIP memory, carries out EDC checking on at least a duplicate of the specific part, and then shadows an error-free part corresponding to the specific part to the XIP memory.

Abstract: A system and method for electronic device communication. A system includes a client device application including an encryption/decryption module, wherein the module directly transmits and receives data to and from the client device application; and a server device application including an encryption/decryption module coupled to the client device application through a communication medium, wherein the module directly transmits and receives data to and from the server device application.

Abstract: In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.

Abstract: A method for recovering a basic input output system (BIOS) and a computer device thereof are disclosed. The computer device includes a motherboard, a power button, a BIOS storage unit, and an embedded controller. The BIOS storage unit is disposed on the motherboard, and it stores a first boot block code and a second boot block code. When the computer device is connected with a power supply to supply standby power to the motherboard, and the power button is not pressed, the embedded controller detects whether the first boot block code is damaged. If the first boot block code is damaged, the embedded controller recovers the first boot block code via the second boot block code.

Abstract: A method for tuning memory parameter values and a computer system using the same are disclosed. In the invention, the computer system provides an embedded controller which may accumulate a counting value and send a reset signal to reboot the computer system. Firstly, the embedded controller reloads a memory parameter value corresponding to the counting value. Then, the computer system executes a memory test procedure. When the memory test procedure successes, a BIOS stores the memory parameter value. On the contrary, when the memory test procedure fails, the embedded controller accumulates the counting value and sends the reset signal to reboot the computer system. The BIOS reloading another memory parameter value corresponding to the accumulated counting value and re-executes the memory test procedure.

Abstract: An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output module. The BIOS is used for generating a POST code. The POST code is transmitted via a low pin count (LPC) interface. The conversion module receives the POST code and converts the POST code into a system management bus (SMBus) format. The output module is used for receiving and outputting the POST code transmitted by the conversion module. The output module is an SMBus interface.

Abstract: Method and computer program product for identifying a primary disk storage medium that is higher in a boot order than a secondary disk storage medium in a software RAID, and testing for a hardware failure of the primary disk storage medium during the BIOS power-on self test. The boot order of the disk storage mediums in the software RAID is automatically changed to position the secondary disk storage medium in the RAID higher in the boot order than the primary disk storage medium in response to detecting a hardware failure in the primary disk storage medium. The operating system is then booted from the disk storage medium that is highest in the boot order. A hardware failure may be detected by reading and verifying a predetermined portion of the boot partition of the disk storage medium.

Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Abstract: Method and system for executing instructions out of a non-volatile memory that may have defective blocks is provided. During an initialization process, a processor reads operating system instructions from the non-volatile memory that may have defective blocks. While reading the operating system instructions, the processor expects a valid signature at a known offset. If the processor does not receive a valid signature at the expected offset, the processor continues to search for a valid signature for X more blocks after the offset. The X blocks are the number of defective blocks in a memory partition where the operating system instructions are stored.

Abstract: A method for automatically restoring a system configuration with a single key in a computer having a power button is provided. The method includes detecting a press mode of the power button; determining a relevant restoring item according to the press mode; performing a process for restoring the system configuration corresponding to the restoring item, which aims at updating/recovering the system configuration, or clearing the system configuration setting stored in a CMOS memory; and performing a normal boot process.

Abstract: A semiconductor device is designed to provide an access control for a memory that includes a plurality of storage regions storing the same boot programs comprised of a set of program data. The semiconductor device is provided with a memory controller for reading out the program data from the storage regions, and an error detection circuit performing error detection on the program data read out. When the error detection circuit detects an error in one of the program data read out from one of the storage regions, the memory controller reads out the corresponding one of the program data from another of the storage regions.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: Detection of a reset failure in a multinode data processing system is provided by a diagnostic circuit in each of a plurality of the server nodes of the system. Each diagnostic circuit is coupled to a code fetch chain of its corresponding node. At reset, prior to a node processor retrieving startup code from the code fetch chain, the diagnostic circuit provides diagnostic signals to the code fetch chain. A problem in the code fetch chain is detected from a response to the diagnostic signals. When a problem is detected, a node failure status for the problem node may be signaled to the other nodes. The multinode system may be configured in response to signaled node failure status, such as by dropping failed nodes and replacing a failed primary node with a secondary node if necessary.

Abstract: An information handling system includes a lock, a switch, and a south bridge. The lock is configured to receive a key and to alternate between a locked position and an unlocked position. The switch is in communication with the lock. The switch is configured to receive a signal from the lock, to close if the lock is in the locked position, and to open if the lock is in the unlocked position. The south bridge is in communication with the switch. The south bridge is configured to disable a plurality of communication ports of the information handling system when the switch is closed, and configured to enable the communication ports when the switch is opened.

Abstract: A computer system firmware stores an operating system boot loader along with accompanying firmware boot driver and a service option ROM. A firmware boot enables the computer system to initiate an operating system boot without necessarily utilizing a hard drive or other peripheral. The service option ROM is installed, indicating to the firmware that a firmware boot is available. When selected the firmware boot copies the operating system boot loader from firmware to main memory and then initiates the operating system boot loader.

Abstract: A power lock-up setting method and an electronic apparatus using the same are provided. The power lock-up setting method includes following steps. A trigger signal generated by a pressed power switch is received by a pin of a GPIO interface and transmitted to a control unit, such that the control unit starts the electronic apparatus, and a power-on-self-test of a logic processing unit is performed by a processing module. Whether the GPIO interface is set to a power lock-up state is determined by the logic processing unit. If so, a level of the pin is set to a disable level. An operating system is loaded by the processing module to perform an operating system booting process. Accordingly, when the electronic apparatus is under an operating environment of the operating system, the trigger signal is forbidden to be transmitted to the control unit when being generated again.

Abstract: A bus fault detecting unit 21 detects a closed PCI bus, and outputs to an OS 1, a PCI card disconnection instructing signal that requires the OS 1 to disconnect PCI cards connected to the closed PCI bus and PCI buses downstream of this PCI bus. The OS 1 disconnects the designated PCI cards from its control, and outputs to a BIOS 2, a power-off instructing signal that instructs to turn off the power of the disconnected PCI cards. In response to this, a PCI card disconnection handling unit 23 activates a bus diagnosing unit 24, and the bus diagnosing unit 24 diagnoses whether the closed PCI bus functions normally or not. In a case where the closed PCI bus functions normally, a bus opening unit 25 opens the closed PCI bus.

Abstract: Under the present invention, a configurable dictionary is provided. The configurable dictionary includes a set of objects that identify: (1) attribute conditions of the computer system to be checked; (2) associated locations within the computer system for checking the attribute conditions; and (3) actions to be taken based on results of the checks for the computer system. The health of the computer system is checked by processing the set of objects in the configurable dictionary. Specifically, the attribute conditions identified in the configurable dictionary are checked at their associated locations, and any necessary action are implemented.

Abstract: A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the detecting unit for controlling the detecting unit to check a status of a bus signal on the bus after a predetermined delay time. Accordingly, the detecting unit may enable the first BIOS unit or the second BIOS unit to boot the computer system according to the state of the bus signal.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: A computer debug method includes following steps: a Power-On Self Test (POST) is started; several function tests of the POST are executed respectively, wherein at least one set of codes corresponding to each following executing function test is stored in a memory before executing each of the function tests; when the POST is interrupted, wait for a user to input a guess signal through an input device; compare the set of stored codes in the memory with the guess signal; a signal representing that the set of stored codes in the memory equals to the guess signal is output if the set of stored codes in the memory equals to the guess signal.

Abstract: A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.

Abstract: The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.

Abstract: Disclosed is an apparatus and method of mirroring firmware and data of an embedded system. The embedded system mirrors a boot loader image, a kernel image, a RAM disk image and data that are stored on a main flash memory to be operated onto a secondary flash memory. Therefore, when a main flash memory does not normally work, the firmware and data that are stored on the main flash memory to be operated is mirrored onto the secondary flash memory, which prevents the loss of data and maintains the operation of the embedded system. As a result, it is possible to secure the reliability and operability of the system.

Abstract: Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.

Abstract: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.