Abstract: A method for detecting a power failure type of an electronic device sets a shutdown flag as a first value when the electronic device is turned on, modifies the shutdown flag to a second value if a shutdown status of the electronic device is detected, and modifies the shutdown flag to a third value when the electronic device keeps the shutdown status for a predetermined time. The method further determines the power failure type of the electronic device according to a value of the shutdown flag when the electronic device is turned on the next time.

Abstract: The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.

Abstract: A diagnostic card includes a circuit board, a connector, a controller, and a first display. The connector is coupled to a low pin count (LPC) to receive a reset signal outputted by a basic input output system as a server reboots. The controller is configured to record the total number of reboot times of the server and displays the total number of reboot times on the first display area.

Abstract: A state restoration unit tracks opening and closing of programs within a computer operating system. Responsive to detecting opening and closing of programs, a state restoration structure is updated. After the computer operating system restarts from a failure, the state restoration structure is accessed. The state restoration unit restores those of the programs indicated as open in the state restoration structure.

Abstract: A firmware recovery system includes a baseboard management controller (BMC) module, a south bridge, a basic input and output system (BIOS) module, a multiplexer and a storage module. The BIOS module is connected to the BMC module by the south bridge and determines whether a firmware file of the BMC module is corrupt. The multiplexer selectively connects the BIOS module or the BMC module to the south bridge. The storage module stores a new firmware file. When the firmware file of the BMC module is corrupt, the BIOS module controls the multiplexer to select the BMC module to connect to the south bridge. The BIOS module reads the new firmware file from the storage module to recover the corrupt firmware file from the BMC module.

Abstract: A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.

Abstract: The present disclosure provides a method for outputting power-on self test information, a virtual machine manager, and a processor. The method includes: receiving trigger information generated by a BIOS program when the BIOS program runs a predefined virtual mode trigger instruction, starting, by a virtual machine manager, the virtual machine manager and monitoring a processor, where the processor is a processor that enters a virtual mode after receiving the trigger information of the BIOS program; when detecting that the processor generates an exit instruction, obtaining power-on self test information after the BIOS program performs a power-on self test operation, and outputting the power-on self test information to a serial port. Power-on self test information may be output without using a motherboard diagnostic card, so that device resources are saved. In addition, the operation is simple, and no human control operation is required.

Abstract: A BIOS refresh device includes a first socket, a second socket, and a jumper. The first socket includes a first elastic contact, a first voltage contact, and a first ground contact. The second socket includes a second elastic contact, a second voltage contact, and a second ground contact. The jumper includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is electronically connected with the second elastic contact. The second pin is electronically connected with the first voltage contact or the second voltage contact. The third pin is electronically connected with the first elastic contact. The fourth pin is electronically connected with the second ground contact or the second ground contact.

Abstract: During starting of a field device for pressure measurement, flow measurement and/or fill level measurement, which field device including a memory that includes a boot memory region in which a boot function is stored, and an operating memory region in which an operating function is stored, the following steps are carried out: carrying out the boot function; determining whether a memory check of the operating memory region is to be carried out; carrying out a memory check of the operating memory region when it has been determined that a memory check is to be carried out; and carrying out the operating function.

Abstract: Technologies are described herein for allowing a computer system to recover from an invalid configuration, without requiring any modifications to the hardware of the computer system by the user. The computer determines whether a boot-fail counter exceeds a threshold value. If the boot-fail counter exceeds the threshold value, the computer executes an exception processing routine. In one aspect, the exception processing routine causes the computer to reset configuration settings stored in a memory area of the computer to default configuration settings. If the boot-fail counter does not exceed the threshold value, the computer increments the boot-fail counter and executes system initialization routines for booting the computer. Upon successfully completing the system initialization routines, the computer resets the boot-fail counter.

Abstract: A value of a configuration setting contained within a selected content unit of an application may be used as input for a configuration check algorithm to calculate a control parameter output. The algorithm may include logical operators, conditional statements, mathematical logic, and mathematical functions. The algorithm may be used to verify the correctness of the value. Different control parameter output values may be associated with different options in the automated configuration verification program. The options may include, but are not limited to, modifying an unsupported configuration setting value to a supported value, updating configuration setting values in non-selected content units, exiting the automated program and switching to a manual configuration setting change mode, and automatically updating a configuration setting value to a supported value without further intervention.

Abstract: A method for performing a quick boot and a general boot at a basic input output system (BIOS) stage is described. A computer is powered on. An embedded controller firmware or a BIOS determines whether a quick boot key is pressed. If the quick boot key is not pressed, a boot flag is changed from Quick Boot to General Boot. If the quick boot key is pressed, the BIOS determines whether the boot flag is set to Quick Boot. If it is determined that the boot flag is set to Quick Boot, an initialization of drivers preset by the quick boot is performed, and uninitialized drivers are initialized at a stage when an operating system is started. If it is determined that the boot flag is set to General Boot, an initialization of all drivers is performed.

Abstract: A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.

Abstract: An information processing apparatus including an apparatus body and a system control apparatus. The apparatus body includes a first processing unit that executes an arithmetic operation; a first storage unit that stores configuration information of the first processing unit; and a first control unit that controls a readout of the configuration information. The system control apparatus includes a second storage unit that stores a program for controlling the system control apparatus and diagnosis procedures of the information processing apparatus; a second processing unit that reads the program and executes the program; and a second control unit that detects the first processing unit by reading the configuration information via the first control unit on the basis of the diagnosis procedures stored in the second storage unit simultaneously with the execution of the program by the second processing unit.

Abstract: A computer-implemented method for focusing product testing based on areas of change within the product is described. A link between resource files of a product and test cases associated with the product is created. The resource files of a first build of the product are compared with the resource files of a second build of the product. A report that comprises which resource files changed between the first build of the product and the second build of the product is generated. The resource files that have changed and the test cases linked to the changed resource files are displayed. The test cases linked to the changed resource files are executed.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: A non-volatile memory device comprises an application code sector of sufficient size to store a first copy of an application code and a second copy of the application code; and a boot sector having a boot loader code embodied therein. The boot loader code is configured to cause a processor to check the integrity of both the first and second copies of the application code; if the first copy is corrupted, overwrite the first copy of the application code with the second copy; and if the second copy is corrupted, overwrite the second copy of the application code with the first copy.

Abstract: A testing method for a server supporting an intelligent platform management interface (IPMI) is applied to test a server before an operating system (OS) of the server operates. The test method includes the following steps. A baseboard management controller (BMC) of the server is activated. The server is activated, and a monitoring module is operated. Real-time status data of the server stored in the BMC of the server is obtained. The monitoring module executes a pre-test procedure according to the real-time status data of the server before the OS operates. A test result of the pre-test procedure is stored.

Abstract: Embodiments of the present invention provide a method, devices and a system for automatic device failure recovery. The method mainly includes: sending a recovery request message to a management device or a server; obtaining a program file used for failure recovery from the management device or the server; and performing the failure recovery by using the program file. With the implemention of the present invention, a device may recover from a failure fully automatically. No intervention of a local user is needed in the whole failure recovery process. Therefore, the implementation of the recovery is more convenient and more flexible. Meanwhile, the failure emergency recovery of the device may be implemented automatically, which makes the failure recovery processing safer and more reliable, and effectively reduces the cost of the local maintenance of a device.

Abstract: A computer system firmware stores an operating system boot loader along with accompanying firmware boot driver and a service option ROM. A firmware boot enables the computer system to initiate an operating system boot without necessarily utilizing a hard drive or other peripheral. The service option ROM is installed, indicating to the firmware that a firmware boot is available. When selected the firmware boot copies the operating system boot loader from firmware to main memory and then initiates the operating system boot loader.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: Disclosed are techniques for recovering system configuration settings, such as remote management, of an information handling system following a disorderly shutdown. A restart controller detects a disorderly shutdown of an information handling system and, in response, sets a disorderly shutdown flag and restarts the information handling system. During the restart, the basic input/output system (BIOS) checks the disorderly shutdown flag as part of its power-on housekeeping. In response to determining the disorderly shutdown flag has been set, the BIOS reconfigures the system configuration settings, such as the power management scheme, of the information handling system so as to enable one or more remote wake mechanisms, such as wake-on-LAN or wake-on-ring. The BIOS then performs an orderly shutdown of the information handling system to place the information handling system in a low-power state, from which the information handling system can be awoken via the remote wake mechanism.

Abstract: According to example embodiments, a solid state drive system includes at least one semiconductor memory, a control circuit including first connection terminals, and second connection terminals. The first connection terminals may be configured to supply one or more operational voltages to the at least one semiconductor memory. The second connection terminals may be configured to supply one or more test voltages to the at least one semiconductor memory.

Abstract: A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises a plurality of bays, a screen, and control circuitry operable to detect when a first DSD has been inserted into a first bay. Independent of operator input, a graphical user interface (GUI) displayed on the screen is automatically updated to reflect the first DSD has been inserted into the first bay. Independent of operator input, a DSD test is automatically executed on the first DSD. When the first DSD is removed from the first bay, independent of operator input, the GUI is automatically updated to reflect the first DSD has been removed from the first bay.

Abstract: A method for troubleshooting a set top box is disclosed and can include receiving a trouble ticket from a set top box and initiating a self test at the set top box. The method can also include receiving test results from the set top box and analyzing the test results to isolate a problem.

Abstract: A control server is electronically connected with a number of test servers via a number network interfaces. The control server records a network interface number and an IP address of a baseboard management controller (BMC) of each test server, sets an IP address of a network card of the control server, and generates a test command. The test command comprises information in relation to a number of times for powering on a test server, a number of times for powering off the test server, and a time interval between a power-on operation and a power-off operation. The test command is sent to each test server by the control server according to the network interface number and the IP address of the test server. After receiving the test command, the BMC of the test server performs power-on/power-off operations of the test server according to the test command.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: Example embodiments relate to a machine-readable storage medium encoded with instructions executable by a processor of a computing device including a display device. The machine-readable storage medium may include instructions that access a stored indication upon boot-up of the computing device using a Basic Input Output System (BIOS). In addition, the machine-readable storage medium may include instructions that determine, using the stored indication, whether an operating system (OS) of the computing device exited properly, and instructions that display a BIOS productivity display using the display device when it is determined that the computing device exited properly. Still further, the machine-readable storage medium may include instructions that permit the OS to display a recovery display when it is determined that the OS did not exit properly.

Abstract: A storage system includes first and second expanders for connecting storage units, each of the first and second expanders being connected cascade each other, a first controller connected one of the first and one of the second expanders and a host, a second controller connected the one of the second expanders, the one of the first expanders and the host, the second controller detecting a failure of at least one of the first controller, the first expanders and the second expanders, the second controller selectively controlling a first boot sequence which boots the first controller after the first expanders have been booted and a second boot sequence which boots the first controller before the first expanders have been booted, determining one of the first boot sequence and the second boot sequence on the basis of a place where a failure has occurred in a recovery process.

Abstract: A method for processing booting failure of a computer system is adapted for being performed at a computer. The method includes the following steps. First, a parameter selecting signal is generated according to a triggering signal by a control module. Second, a driving parameter is chosen from a look-up table according to the parameter selecting signal by a basic input output system (BIOS), and the driving parameter is loaded into the BIOS and provided to a driving module. Third, a memory is driven according to the driving parameter by the driving module. Fourth, the driving parameter is stored by BIOS.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: Aspects for monitoring audible tones indicative of operational status of each planar in a multiple planar chassis are described. Included in the aspects is the monitoring of a speaker channel of each planar of a plurality of planars in a common chassis for state changes of beep tones. An operational status of a specific planar emitting the beep tones is identified based on the state changes.

Abstract: A user of a user computer whose hard disk drive (HDD) is “fried” can press a special key to cause BIOS to automatically gather location information about the computer from its GPS receiver and gather information about the HDD, activate a WWAN transceiver, and automatically send the location and HDD information over the WWAN to a service computer, which may return a location of a nearest service center to the user computer and any other advice including recovery advice for the HDD that the service center might be able to divine from the information sent to it by the user computer.

Abstract: A boot test apparatus and method can repeatedly execute actions of power-on and power-off for a cold boot test of a computer to test whether the computer is operable. The boot test apparatus includes a microprocessor, a controller, and a power switch. The microprocessor generates a control signal according to a period voltage provided by an internal power supply. The control signal includes a pulse signal and a voltage signal. The controller controls a power switch to send the pulse signal to the computer through a power button of the computer, and controls the power switch to send the voltage signal to the computer through a power input port of the computer. The microprocessor further obtains test information from the computer when the computer executes a cold boot process according to the control signal, and displays the test information on an LED when the cold boot process is abnormal.

Abstract: A method capable of executing programs for a computer system operating in a shut down state includes generating a control instruction while a key of the computer system is pressed down; storing the control instruction; and performing actions according to the control instruction when the computer system is booted up.

Abstract: Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed.

Abstract: Firmware is interactively recoverable prior to loading an operating system on a computer. Rather than proceeding through a recovery without user input, user input about a recovery is solicited after determining that an update is needed. Prior to recovering the firmware, users may be able to, for example, specify configuration options about the recovery, cancel the update altogether, and specify a firmware image location. Once input is received, the firmware recovery proceeds.

Abstract: A method and system for performing parallel tasks in a computer system includes invoking a single-threaded operating environment in a computer, invoking under the single-threaded operating environment a first task to be performed by a first processor, invoking under the single-threaded operating environment a second task to be performed by a second processor, while the first task is still being performed, and receiving results from the first and second tasks.

Abstract: A storage medium to manage a master boot record and a method of booting a computer system using the storage medium. The storage medium includes a master boot record sector area having a master boot record related to a booting operation being currently performed stored therein, a data storage area having a master boot record that is previously changed stored therein, and a firmware to communicate with a host device and to manage the master boot record sector area and the data storage area, wherein, when an error occurs in the master boot record stored in the master boot record sector area, the firmware selects a specific master boot record from the data storage area and stores the selected master boot record in the master boot record sector area.

Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Abstract: The present invention relates to a debugging apparatus for a computer system and a method thereof. A detecting unit detects if a debugging unit connects to the computer system. When a debugging unit connects to the computer system, the detecting unit produces a detecting signal, which contains information of a bus in the computer system electrically connected with the debugging unit. Then a selection unit selects the bus electrically connected with the debugging unit according to the detecting signal. Besides, a testing unit tests the computer system and produces a power-on self-test (POST) code, so that the selected bus can be used for outputting the POST code to the debugging unit. Thereby, the present invention can choose to use the bus reserved in the computer system for outputting the POST code to the debugging unit, and hence facilitating inspection personnel to debug the computer system.

Abstract: A processing system for monitoring the power-on self-test information is used for monitoring an operating state of a complex programmable logic device (CPLD) of a main board. The processing system includes a basic input/output system (BIOS) device, a CPLD and a monitoring device. The BIOS device sends power-on self-test information at a first frequency. The CPLD is electrically connected to the BIOS device. The CPLD further includes a first in first out (FIFO) register, and the FIFO register is used for storing the received power-on self-test information. The CPLD sends the power-on self-test information stored in the FIFO register at a second frequency. The monitoring device is electrically connected to the CPLD. The monitoring device is used for receiving the power-on self-test information sent from the CPLD.

Abstract: A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies a defective area in the main memory. The diagnostic-program loading unit loads a processor-diagnostic program for diagnosing a plurality of functions of the first processor into an area of the main memory other than the defective area identified by the memory-diagnostic unit. The defective-function identifying unit causes the second processor to execute the processor-diagnostic program loaded by the diagnostic-program loading unit, and identifies a defective function that is disabled from the functions of the first processor.

Abstract: A device and method for outputting BIOS POST code, applied to a computer system. The device includes a basic input output system (BIOS), a transfer module and a video graphics array (VGA) connector. The BIOS generates a power-on self-test (POST) code using a low pin count (LPC) interface format. The transfer module receives the POST code and transfers the format of the POST code to a system management bus (SMBus) format. The VGA connector receives and outputs the POST code transmitted from the transfer module.

Abstract: A power-on test system is used to test a number of blades of a blade server. The power-on test system supplies power to the number of blades. The power-on test system times for the blades after supplying power, and determines whether the blades are powered on after supplying power. If one of the blades is not powered on, the power-on test system determining whether an accumulated time is less than a set power-on time. If the accumulated time is equal to or greater than a power-on setting time, the power-on test system sends internet protocol address of the blade being not powered on to be displayed.

Abstract: Embodiments disclosed herein related to a system used for disaster recovery backup. The system converts the operating system in the system preparing for disaster recovery into a virtualized system which will be disaster-recovery-ready. The system includes: a device to be converted on which a physical operating system is installed; a USB converting device which is coupled to the device to be converted, which includes a USB disc operating system, a converting unit and a virtual system, and which is used to convert the physical operating system in the device to be converted into a virtual system for making backup of the virtual system. Embodiments disclosed herein are further related to a method for disaster recovery backup and a method for installing the disaster recovery system. The disaster recovery system based on the virtualization technology may be deployed rapidly without making any changes to the physical operating system itself.

Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

Abstract: The invention provides a boot method capable of reducing boot time even in the case of a change in the configuration of boot files. A boot file is booted from a hard disk drive in a computer equipped with a multitasking operating system. A plurality of tasks are observed, the tasks being created and sequentially executed in order to read out boot files. This observation is carried out at the corresponding boot and a log in the past boot is not used. On the basis of the observed boot files, a prefetch boot file is selected. The entire selected prefetch boot file is filled into a boot cache. The boot file is loaded from the boot cache to a main memory.

Abstract: A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Abstract: A system and method for providing an electronic device security and tracking system and method (ESTSM). A method includes but is not limited to accepting a selection of an opt-in to use the ESTSM service; and making available the ESTSM service.