Abstract: A method for synchronizing time in an Ethernet-based network having a master network subscriber, a first segment and a second segment. Each segment has at least one network subscriber. The second segment is connected to the first segment by a first network distributor, arranged in the second segment. The method comprises steps for sending out a synchronization telegram addressed to the second segment by the master network subscriber, the synchronization telegram being of the first type; receiving the synchronization telegram by the first network distributor, for conversion into a second type; forwarding the synchronization telegram to a network distributor of the second segment, by the first network distributor; reading out a synchronization value stored in the synchronization telegram by the first network distributor of the second segment; and adjusting a speed of a local system time of the network distributor of the second segment, using the synchronization value.

Abstract: In some implementations, a vehicle device may receive, from a controller area network (CAN) bus of a vehicle and for a time period, messages received by the CAN bus after an engine of the vehicle is turned on. The vehicle device may combine identifiers provided in unique addresses, of the messages received by the CAN bus, to generate a unique identifier, and may utilize the unique identifier to determine data identifying a year, a make, and a model of the vehicle. The vehicle device may utilize the data identifying the year, the make, and the model of the vehicle to determine non-standard parameter identifiers associated with an engine control module of the vehicle.

Abstract: Implementing a firmware watchdog timer. A system presents a data structure over a bus which exposes, to software executing at a central processing unit (CPU), a hardware resource that is associated with a watchdog timer, attribute(s) of the watchdog timer, and (iii) commands available to the software executing at the CPU for managing the watchdog timer via one or more native CPU instructions that target the hardware resource. The system listens on the bus for a data value written to the hardware resource (i.e., by a native CPU operation issued by the software executing at the CPU), and identifies a particular command for managing the watchdog timer based on the data value written. Based on identifying the particular command, the system performs at least one of: initializing the watchdog timer, starting the watchdog timer, resetting the watchdog timer, or stopping the watchdog timer.

Abstract: A method includes receiving a request to process a set of data using a data processing application. The method includes, based on a feature associated with the set of data, selecting between (i) a first mode in which one or more running processes of the data processing application are used to process the set of data and (2) a second mode in which one or more new processes of the data processing application are started up. The method includes causing the data processing application to be executed according to the selected mode to process the set of data.

Abstract: Fault detection devices, systems, and methods are provided which implement identical processors. A first processor is configured to receive a first measurement, execute a first firmware based on the first measurement, and output a first result of the executed first firmware. A second processor is configured to receive a second measurement, execute a second firmware based on the second measurement, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin.

Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

Abstract: In response to determining that an application programming interface call made in response to a first request for the call has failed and that no fail entry has been set for the call, aspects increment a fail count value and set a fail entry for the call that includes a fail response generated by the failure of the call; in response to determining that the call has failed in response to a subsequent, second request for the call, determine whether the incremented fail count value meets a limit value, and if so, set a paused timestamp value for the fail entry; and in response to additional requests for the call occurring within a pause period of time from the paused timestamp value, pause making the call and return the fail entry set for the call in satisfaction of said additional requests.

Abstract: A diagnostic Electrochemical Impedance Spectroscopy (EIS) procedure is applied to measure values of impedance-related parameters for one or more sensing electrodes. The parameters may include real impedance, imaginary impedance, impedance magnitude, and/or phase angle. The measured values of the impedance-related parameters are then used in performing sensor diagnostics, calculating a highly-reliable fused sensor glucose value based on signals from a plurality of redundant sensing electrodes, calibrating sensors, detecting interferents within close proximity of one or more sensing electrodes, and testing surface area characteristics of electroplated electrodes. Advantageously, impedance-related parameters can be defined that are substantially glucose-independent over specific ranges of frequencies. An Application Specific Integrated Circuit (ASIC) enables implementation of the EIS-based diagnostics, fusion algorithms, and other processes based on measurement of EIS-based parameters.

Abstract: A diagnostic Electrochemical Impedance Spectroscopy (EIS) procedure is applied to measure values of impedance-related parameters for one or more sensing electrodes. The parameters may include real impedance, imaginary impedance, impedance magnitude, and/or phase angle. The measured values of the impedance-related parameters are then used in performing sensor diagnostics, calculating a highly-reliable fused sensor glucose value based on signals from a plurality of redundant sensing electrodes, calibrating sensors, detecting interferents within close proximity of one or more sensing electrodes, and testing surface area characteristics of electroplated electrodes. Advantageously, impedance-related parameters can be defined that are substantially glucose-independent over specific ranges of frequencies. An Application Specific Integrated Circuit (ASIC) enables implementation of the EIS-based diagnostics, fusion algorithms, and other processes based on measurement of EIS-based parameters.

Abstract: A diagnostic Electrochemical Impedance Spectroscopy (EIS) procedure is applied to measure values of impedance-related parameters for one or more sensing electrodes. The parameters may include real impedance, imaginary impedance, impedance magnitude, and/or phase angle. The measured values of the impedance-related parameters are then used in performing sensor diagnostics, calculating a highly-reliable fused sensor glucose value based on signals from a plurality of redundant sensing electrodes, calibrating sensors, detecting interferents within close proximity of one or more sensing electrodes, and testing surface area characteristics of electroplated electrodes. Advantageously, impedance-related parameters can be defined that are substantially glucose-independent over specific ranges of frequencies. An Application Specific Integrated Circuit (ASIC) enables implementation of the EIS-based diagnostics, fusion algorithms, and other processes based on measurement of EIS-based parameters.

Abstract: The present disclosure relates to an apparatus and a method for collecting failure/error history lists to identify and categorize erring memory locations in randomly accessible memory of a computer system. Method and apparatus consistent with the present disclosure may identify whether particular memory cells, rows of memory cells, or columns of memory cells within a memory device are associated with transient or persistent errors. These methods and apparatus may also avoid using portions of memory that have been associated with persistent errors or failures.

Abstract: A memory appliance system is described and includes a processor coupled to one or more communication channels with a command interface, wherein the processor is configured for communicating commands over the communication channels. A plurality of Smart Memory Cubes (SMCs) is coupled to the processor through the communication channels. Each of the SMCs includes a controller that is programmable, and a plurality of memory devices. The controller is configured to respond to commands from the command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices.

Abstract: A controller analyzes a tuple in an operator graph. The controller determines that the tuple includes one or more selected characteristics. These characteristics signify preferred data. The controller determines operations of the operator graph which can be suppressed. The controller suppresses the one or more operations. The controller suppresses those operations in response to the tuple including one or more of the selected characteristics.

Abstract: A method for monitoring changes in an inventory of media cartridges in a media library includes the steps of determining with a controller that the inventory of media cartridges in the media library has changed, and asynchronously reporting with the controller the specific change in inventory of media cartridges that has occurred in the media library. The method can also include the step of determining whether the change in inventory included an increase or a decrease in the quantity of media cartridges within the media library, or whether the change in inventory did not include an increase or decrease in the quantity of media cartridges within the media library. Further, the method can also include the step of determining whether the change in inventory of media cartridges is required to be reported. A media library system includes a media library having a plurality of media cartridges, and a controller that determines a change in an inventory of media cartridges in the media library.

Abstract: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

Abstract: A method and a device for creating a product stream of product units in a predefined sequence. The device includes a first conveying device with a grouping stretch for creating a cycled product stream of product units from fed products, in a predefined sequence. The device also includes a conveying-away device for conveying away the product units in the predefined sequence in a cycled product stream. The device further includes a bridging device that is designed such that product units amid the bridging of a conveying stretch section of the conveying-away device can be fed to the conveying-away device in a temporally successive manner and thus be sorted into the predefined sequence of product units.

Abstract: Disclosed here is a fault tolerant architecture suitable for use with any distributed computing system. A fault tolerant architecture may include any suitable number of supervisors, dependency managers, node managers, and other modules distributed across any suitable number of nodes. In one or more embodiments, supervisors may monitor the system using any suitable number of heartbeats from any suitable number of node managers and other modules. In one or more embodiments, supervisors may automatically recover failed modules in a distributed system by moving the modules and their dependencies to other nodes in the system. In one or more embodiments, supervisors may request a configuration package from one or more dependency managers installing one or more modules on a node. In one or more embodiments, one or more modules may have any suitable number of redundant copies in the system, where redundant copies of modules in the system may be stored in separate nodes.

Abstract: Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Abstract: An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device.

Abstract: The invention sets forth a New Network Model for building and managing distributed computing networks based on a fundamental network building block referred to as a DIME; an acronym for Distributed Intelligent, Managed, Entity, and a Signaling Infrastructure. The network model enables dynamic management of the programs comprising the DIME. Five of these programs are used for implementing the functional management services commonly referred to as Fault, Configuration, Accounting, Performance and Security, or FCAPS, at the DIME level. A combination of FCAPS management and Signaling Infrastructure enables DIME based Workflows, which are groups of connected DIMEs programmed to execute in coordination with each other to produce desired results. The network model further enables basic Workflow requirements, including those of task specialization; priority based mediation; fault tolerance; reliability; and resiliency.

Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

Abstract: A server system includes at least one server and a server cabinet. The at least one server includes a first connection port and a baseboard management controller which detects a connection state of the first connection port and according to the connection state, outputs a data signal or a warning signal. The server cabinet includes chambers for containing the at least one server, and the chamber includes a second connection port and a storage unit. The storage unit stores data. When the connection state specifies that the first connection port couples to the second connection port, the baseboard management controller reads the data stored in the storage unit, to output the data signal. When the connection state specifies that the first connection port does not couple to the second connection port, the baseboard management controller outputs the warning signal.

Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.

Abstract: Methods and apparatus to provide failure detection are disclosed herein. An example method includes executing, via a plurality of computing nodes, first fenced computing operations; storing a count of issued data operations resulting from the first fenced computing operations; and determining whether a failure condition exists in the plurality of computing nodes by comparing the count of issued data operations to the count of performed data operations resulting from the first fenced computing operations.

Abstract: The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by the sending to the microcontroller of an instruction to verify a user code by submitting a correct code, and the value of the counter is decremented by the sending to the microcontroller of the instruction to verify the user code with an erroneous code value.

Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and directing transmission of the group of data units to the host in accordance with the first sequence.

Abstract: A method for event management in asynchronous work processing including timing at least one step in an asynchronous work process, wherein the at least one step is performed by an application and the at least one step has an expected time of completion; determining an error preventing step completion in response to the expected time of completion expiring; correcting the error; and re-performing the at least one step.

Abstract: A dynamic cue signal generator and method for processing one or more input and output signals to synchronize the operation of one or more associated machines and includes processes for creating a signal delay between receiving an input signal and issuing an output signal, for conditioning an input signal to produce an output signal with required parameters, for producing a plurality of outputs signals, for filling in undetected cues in an input signal to create a filled-in output signal, for filtering noise from an input signal to generate a noiseless output signal, and for generating an error output signal to indicate that an unusual event occurs in an input signal.

Abstract: In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO buffers data coming from the L1 FIFO, reducing the polling time for received data. Status is always checked for errors before processing the data and updating the state variables. Implementing a state machine to perform some of the checks results in a PRU utilization that is not a function of the bytes that need to be processed.

Abstract: A method and a system have been disclosed for the preemptive detection of occurrence of one or more faulty conditions based on the usage of one or more resources. The faulty conditions are detected during an execution of a program; the program includes at least one function. The method includes initializing Application Program Interfaces (APIs) across the at least one function. After this, calls to the APIs used within a namespace of the program are intercepted. The interception is performed by the at least one function through extended method classes. Thereafter, the usage of the resources for the at least function intercepting the APIs is checked against a corresponding predetermined threshold limit. Once the usage of the resources is checked, context of the usage of the resources is identified based on a predefined knowledge. Subsequently, the occurrence of the faulty conditions is determined based on the identification.

Abstract: A CPU (1) of an information processing apparatus (8) executes software stored in a DRAM (7). A watchdog timer (2) monitors the operation of the software. A hardware monitoring device (4) monitors the state of hardware provided in the information processing apparatus (8). Results of the monitoring are managed by a management LSI chip (3). A non-volatile memory (6) is where failure information is saved. If no watchdog toggles are received for a given period of time, the watchdog timer (2) notifies the CPU (1) with an NMI signal and starts the second round of time counting. The CPU (1) collects failure information from the management LSI (3). The CPU (1) is rebooted through cold reset when failure information collection is completed, and through hot reset when failure information collection is incomplete. In the case of hot reset, the CPU (1) collects failure information after rebooted.

Abstract: Server management data describes observed operating condition of a pool of spare servers. Based on a demand forecast of a specific target system, a dynamic allocation period is determined as a period during which the target system needs additional server resources to handle an expected demand. Based on the dynamic allocation period and server management data, a set of allocation candidates are nominated from the spare server pool, by eliminating therefrom spare servers which are likely to fail during the dynamic allocation period. An appropriate allocation candidate is then selected for allocation to the target system, such that the selected candidate will satisfy a specified requirement during its allocation period.

Abstract: A packet sorting device includes: a buffer for storing packets belonging to a plurality of communication flows; and a control section which determines, when receiving one of a series of packets, whether the one of the received packets is a disorder packet by a determination process, and sorts the received packets in a correct order by storing the disorder packet and communication flow information thereof in the buffer so that the disorder packet and communication flow identification information are correlated. The disorder packet is one of the received packets which is received in an order different from a transmission order of the packets. The communication flow information identifies the plurality of communication flows.

Abstract: An analyzer may include a body housing having a first ID, a first measurement module having a second ID that is different from the first ID, the first measurement module being releasably attachable to the body housing, a first memory in the body housing, the first memory being configured to store the first ID, first setting data and first correction data, a second memory in the first measurement module, the second memory being configured to store the second ID, second setting data and second correction data, a first CPU in the body housing, the first CPU being configured to detect the first measurement module having the second ID, and a first data transmission unit in the body housing, the first data transmission unit being configured to transmit the first setting data and the first correction data to the second memory.

Abstract: A system, method and computer program product are provided. In use, execution of a portion of internal code of an interface is identified. Further, in response to the execution of the portion of internal code, at least one aspect of an invocation of the interface is monitored and/or analyzed.

Abstract: A method is disclosed. In at least one embodiment, the method includes providing a system specification of the system; deriving a number N1 of base patterns dependent on the system specification, a base pattern representing at least one service and having a number N2 of parameterisable events and a parameterisable control section representing a control flow and/or a data flow between the events; selecting a number N3, wherein N3?N1, of base patterns and providing a control structure representing a control flow and/or a data flow between the selected base patterns dependent on an event trace expected as a result of the system run; and providing the reference data having at least the selected base patterns and the provided control structure.

Abstract: The present invention is related to a microcomputer mutual monitoring system in which mutual monitoring is performed between a first microcomputer 11 and a second microcomputer 12, characterized in that if a reset of the second microcomputer is performed due to an occurrence of an abnormal event in the second microcomputer, the monitoring of the first microcomputer is performed by an alternative monitoring function 142 incorporated in the first microcomputer instead of the monitoring of the first microcomputer by a monitoring function of the second microcomputer during the reset. With this arrangement, the microcomputer mutual monitoring system, which can prevent reduced marketability while maintaining reliability as a system, can be obtained.

Abstract: In the system management server, an information processing apparatus that is an event-information acquisition target is registered as a monitored apparatus in configuration information; event information that complies with a rule stored in advance is identified from among a plurality of pieces of event information stored in the system management server; a server apparatus for a network service related to the event information is identified; and a message is displayed which indicates that the cause of the event that occurred in a client information processing apparatus which has generated event information is an event related to the network service, which occurred in the server apparatus.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: The invention discloses a method (200) for use in a cellular system (100) with an RBS (120) which controls traffic to and from a cell (110), with one User Equipment, UE (130, 140), in the cell. The RBS and the UE receive and transmit information between each other, one of them being a sending party and the other one is a receiving party, and errors in messages (BSN 1, BSN 4) which are received can be detected by the receiving party by a first error detection method and if errors are detected in received messages, the receiving party can request a retransmission from the transmitting party. The receiving party stores the order in which retransmissions are requested, so that erroneous retransmissions may be detected by the receiving party without the first error detection method.

Abstract: Methods for managing response data within an information handling system (IHS), where the method includes the step of obtaining response data from at least one component in the IHS, the response data generated in response to receiving a command. The method also includes accumulating the response data from the at least one component to compute a total response time.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: An approach is provided for enabling the accounting of closures to support query requests established by a device. A computation processing and accounting infrastructure determines one or more closures based, at least in part, on a query request. One of the one or more closures based, at least in part, on one or more predetermined policies is selected to generate a response to the query.

Abstract: An internal combustion engine is controlled by a plurality of partially reliability-relevant functional units. Every reliability-relevant functional unit comprises at least one functional module and at least one monitoring module. The monitoring module is separate from the functional module associated therewith and monitors the functioning of the functional module. The control device also comprises a higher order monitoring functional group. The monitoring module has an entry point for communication with the higher order monitoring functional group. When an error is detected, the monitoring module signals the error to the higher order monitoring functional group using the entry point.

Abstract: Systems and methods for parallel stream item counting are disclosed. A data stream is partitioned into portions and the portions are assigned to a plurality of processing cores. A sequential kernel is executed at each processing core to compute a local count for items in an assigned portion of the data stream for that processing core. The counts are aggregated for all the processing cores to determine a final count for the items in the data stream. A frequency-aware counting method (FCM) for data streams includes dynamically capturing relative frequency phases of items from a data stream and placing the items in a sketch structure using a plurality of hash functions where a number of hash functions is based on the frequency phase of the item. A zero-frequency table is provided to reduce errors due to absent items.

Abstract: A system for executing a high-reliability application and a third party application is provided. The system includes an application module and a second module. The application module has control logic for executing the high reliability application and the third party application. The high reliability application generates a message sequence. The application module includes a normal operating mode, a high reliability mode, and a high reliability boot. The second module is in communication with the application module, and includes a first control logic for monitoring the message sequence when the application module is operating in the normal operating mode. The second module also includes control logic for initiating the high reliability boot in the application module.

Abstract: A method and structure for notifying operating system events, includes standard filesystem interfaces provided for event consumers to use for one or more of registering for event notifications of a set of events, receiving an event notification when each event occurs, and getting details of events that have occurred.

Abstract: A device may detect and report failure in point-to-point Ethernet links. In one implementation, the device may determine, based on a periodic timing signal, whether at least one packet was received on an incoming Ethernet link during a previous period of the periodic timing signal. The device may update an entry in a circular buffer to indicate whether the at least one packet was received during the previous period of the periodic timing signal and analyze the circular buffer to determine whether there is a signal failure on the incoming Ethernet link.

Abstract: Various embodiments provide a guard mechanism that is configured to prevent transmission of synchronous function calls to hung application components. In at least some embodiments, the guard mechanism receives a synchronous function call that is intended for an application component. Before permitting the synchronous function call to be transmitted to the application component, the guard mechanism determines whether the component is hung. Responsive to determining that the component is not hung, the guard mechanism permits the synchronous function call to be transmitted to the component. If, however, the guard mechanism determines that the application component is hung, a hung component recovery process is initiated.

Abstract: A high-reliability controller for inverter is provided with a simple configuration. The controller for inverter includes a CPU 14 controlling energy of a vehicle, a CPU 15 controlling a power generation amount or an assist amount of a first motor 26, a CPU 16 controlling a power generation amount or an assist amount of a second motor 27, a regulator 8 generating power supplied to the CPUs 14, 15 and 16, a first inverter 23 controlled by the CPU 15, a second inverter 24 controlled by the CPU 16, and a communication line 17 that connects the CPUs 14 to 16. The first inverter 23 and the second inverter 24 are controlled in a cooperative or an independent manner.