Abstract: A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

Abstract: A counter counts pulses of a clock generated by an oscillator. A control register clears the counted value, in response to a reset signal sent from an external circuit. In the case where the counted value exceed, a limit value, an output control circuit outputs a reset signal for instructing to execute the reset process, to the external circuit. This reset signal is provided also to the control register. The control register controls the counter to count the pulses of the clock, in response to the reset signal. Then, abnormal operations occurring in the external circuit during the execution of the reset process can be detected.

Abstract: The novel method synchronizes an electronic device for monitoring the operation of a microprocessor (watchdog) with the microprocessor when the microprocessor is run up from a quiescent mode to an operating mode. The synchronization is effected by a trigger signal that is transmitted from the microprocessor to the monitoring device and that signals the operational availability of the microprocessor. The monitoring device, in order to receive the trigger signals, temporally toggles between a CLOSED window status, in which a trigger signal cannot be detected by the monitoring device, and an OPEN window status, in which the received trigger signal brings about synchronization between the microprocessor and the monitoring device. The microprocessor watchdog device has a trigger signal input which toggles, in a clocked manner, between a disabled position (CLOSED window) and an enabled position (OPEN window). The trigger signal is received during the OPEN window.

Abstract: Device for monitoring the periodicity of the messages sent over a multiplexed data-transmission network, in particular of a motor vehicle, characterized in that it includes a memory (4) for storing object messages which are received from the network and each have a value (8) indicating the reception deadline of the message, local clock means (9) which are synchronized by a periodic internal signal and continuously generate a local time-value signal, means (13) for comparing each message-reception deadline value (21, 22, 23) with the local time value and for generating an overdue signal when the value indicating the reception deadline of the message is less than or equal to the local time value, and means (15) for generating a signal, intended for an external microcontroller (5) and indicating that the message has not been received, on the basis of the overdue signal.

Abstract: The present invention is directed to preventing the generation of a jarring noise when a voice/data multiplexing modem is in a diverging condition. This is accomplished by the modem including an encoder section 14, where a voice signal encoded by mapping it to 63 codes out of the 64 codes that can be expressed with 6 bits. When the unused code is detected by a detector section 28, the reproduced voice signal is masked.

Abstract: A method of determining a route to be tested in the testing of a load module which includes a multiplicity of routes (route patterns) from the start to the end of the program, each route pattern being composed of a multiplicity of route paths. The method comprises the steps of: (1) testing an untested route pattern and managing the current state of the testing of all the route patterns with the untested route pattern changed to a tested route pattern; (2) managing the current state of the testing of all the route paths with the route paths constituting the untested route pattern changed to tested route paths; and (3) determining an untested route pattern which is constituted by the largest number of untested route paths to be the route pattern to be tested next. These steps are repeated until there exists no untested route path in the load module test.

Abstract: The invention relates to an electronic system, in particular a mobile data capture and data output device in which the electronic system has a processor (1) and at least one i/o unit (8) with a control unit (7), and in which the processor (1) is connected to the control unit (7), and the control unit (7) is connected with at least one i/o unit (8). The electronic system is switched to a standby-mode, in which a control software unit (2), which is connected to the processor (1) and the control unit (7) executes part of the processor work, and the control software unit (2) monitors the time when data input from at least one i/o unit (8) commences. If commencement of data input is registered the steps needed for data capture are initiated and concluded before the data input is terminated.

Abstract: The specified monitoring program enables the recognition of endless loops or blocked processes in a computer system, in particular in a telecommunication switching system. When such software errors are recognized, error indices can be collected and stored, which enable a later error analysis and removal. The endless loops or, respectively, blocked processes can also be reset in a suitable way, so that no negative effects on other processes result.

Abstract: Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles.

Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Abstract: A microcomputer (10) is proposed, which includes a central processing unit (11), a non-volatile memory (13), a volatile memory (14), a monitoring circuit (12) and also an input/output unit (16). Two different operating states are possible in the microcomputer (10). In the first operating state, the microcomputer executes a program which is located in the non-volatile memory (13). In the second operating state, the microcomputer (10) executes a program which is located in the volatile memory (14). The monitoring circuit (12) effects a resetting of the microcomputer (10) whenever it does not receive a monitoring signal for a predetermined time (watchdog timer). The microcomputer is distinguished in that it includes an element for suppressing monitoring signals which are always active whenever the microcomputer (10) is operating in the second operating state.

Abstract: Reliably detecting malfunction of an abnormality-monitoring circuit during operation of a processing unit. An electronic control unit provided with a CPU level-inverts and outputs an actuating signal during each iteration of a base routine. An abnormality-monitoring circuit clocks a fall interval of the actuating signal as charging voltage of a gradually discharged capacitor, and outputs a reset signal to the CPU when this charging voltage falls to a defined value. When a check-starting condition is fulfilled, the CPU inhibits a subsequent level inversion of the actuating signal until a predetermined time elapses after a prior level inversion. When the signal inhibition is canceled, when the charging voltage VC of the capacitor is not within a reference range (VL-VH), the CPU determines the abnormality-monitoring circuit to have malfunctioned.

Abstract: A uni-direction protection switched ring node which switches from a working path to a protection path or vice versa includes a failure-information detect circuit which detects a failure occurring on the working path and a failure occurring on the protection path independently of each other as failure information. A failure-information-path identifying circuit determines whether a working path with a failure occurring thereon is an active or standby path or determines whether a protection path with a failure occurring thereon is an active or standby path. A select circuit selects either the working or protection path as an active path in accordance with results of detection and determination by the failure-information detect circuit and the failure-information-path identifying circuit respectively.

Abstract: A method and system in a server cluster for monitoring and controlling a resource object, such as a physical device or application. A cluster service connects to a resource monitoring component to control and monitor the health of one or more resource objects. The resource component includes a plurality of methods, common to all such resource components, for calling by the resource monitor to control and monitor operation of the resource object therethrough. The common methods enable the cluster server to treat all resources similarly without regard to the type of resource.

Abstract: There is proposed a process for the monitoring of integrated circuits (ASICs 21, 22) in safety-critical applications, in which the ASICs (21, 22) with identical constructions are connected in parallel and simultaneously to all inputs. The ASICs (21, 22) operate closely synchronized with each other and mutually monitor each other. They carry out a comparison of interim results, end results and output data. The logic condition is monitored at different monitoring points; namely, the freely defineable interim and end results of an information processing, the suitable internal switching conditions and the internal signals at discrete scanning points in time.

Abstract: A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.

Abstract: A method of identifying unacceptable levels of defects in specific sections or work centers of a manufacturing process on a real time basis and initiating corrective action is disclosed. The system allows a user to define defect tolerances or thresholds for manufacturing work centers, tracks defects at the work centers, compares the level of faults with the tolerances, reports out of tolerance work centers, automatically initiates contact with the appropriate personnel to affect a correction to the out of tolerance work center, and maintains records of corrective actions taken.

Abstract: A watchdog timer for a computer with a CPU and a peripheral controller. The watchdog timer includes a program in the peripheral controller and a corresponding program in the peripheral interrupt service routine of the CPU. When the watchdog timer function is enabled, the peripheral controller will interrupt the CPU periodically and check the response from the CPU. If the CPU is not responding, or wrong data is returned from the CPU, the peripheral controller will generate a reset signal to reset the CPU and reboot the system.

Abstract: A data-analyzing unit monitors and/or analyzes events on an information bus. The data-analyzing unit comprises an event recognition unit with one or more comparators coupled to the information bus and a sequencer state machine for determining sequential dependencies of events, whereby a state of the sequencer state machine depends on the history of information as provided thereto. The data-analyzing unit preferably comprises one or more counters coupled to the event recognition unit, thus allowing an analysis of data and/or events on the information bus. The data-analyzing unit may also comprise one or more memories coupled to the event recognition unit, thus providing a trace memory. In a preferred embodiment, the event recognition unit of the data-analyzing unit provides customized rules for monitoring defined event sequences of event behaviors thus allowing the monitoring of defined event sequences of event behaviors and possibly the drawing of conclusions therefrom e.g.

Abstract: A method for loading sub-processors in system having a plurality of sub-processors connected with main processor via a repeater and utilizing broadcasting function is disclosed. The method comprises the Steps of inspecting a transfer path communicating the main processor and the plural sub-processors; collecting a loading request signal transmitted from the sub-processors at predetermined time period; and loading simultaneously the sub-processors using broadcasting function after interconnecting the sub-processors which request the collected loading during the collecting Step with the main processor via the repeater in multipoint base. The sub-processors having the collected signal are simultaneously loaded using broadcasting function, it has the effect for reducing loading time.

Abstract: A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.

Abstract: In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, during the transmission of a message packet from a first routing element to a second routing element in the MPP system, link lock-up can be prevented effectively by determining whether the message packet contains a certain predefined quantity of data. Control codes, used for establishing the end to the message packet, can then be inserted into the message packet if it is determined that the message packet does, in fact, contain the predefined quantity of data.

Abstract: A timer is periodically reset by a software agent executing on a processor. If the timer is not reset within a predetermined period of time, an interrupt is generated. An interrupt handler then periodically resets the timer, and if the timer is not reset within an additional predetermined period of time, the computer system is partially reset.

Abstract: An instruction flow monitoring mechanism performs control flow error detection in a reduced instruction set computer (RISC) processor using signature monitoring. The signature monitoring is integrated into the RISC processor such that the instruction set of the RISC processor is enhanced to perform signature checking under all execution conditions. A signature monitor instruction causes the instruction flow to be checked for errors by comparing a pre-computed reference signature with a current signature and raising an error condition if the two signatures are unequal. The instruction also initializes the current signature.

Abstract: A smart built-in-test device for classifying fault behavior in electronic systems comprising a temporal monitor monitoring fault, classifying fault behavior and generating fault behavior data as the system operates in real time; one or more sensors for measuring environmental stress conditions in real-time and outputting environmental stress condition data. A fault correlator device for receiving the fault behavior data and the environmental stress condition data and correlating fault behavior to environmental stress conditions to determine if significant correlation exists.