Abstract: A multi-CPU system including plural CPUs, comprising a failure state detection unit for detecting a failure in an operating program, and a recovery unit for determining, when the failure state detection unit has detected a failure, whether or not recovery of data involved in the failure is possible on the basis of content of the detected failure, and for recovering the data when recovery is determined to be possible.

Abstract: In a work-process tracking system, each of event-data collecting threads collects event data from each of work systems. A storing thread stores the event data collected in a database. When a termination instruction is received, a thread in operation is terminated. For example, when an instruction to start (or terminate) an event-data collecting process is received, a control unit initiates (or terminates) the event-data collecting thread. Similarly, when an instruction to start (or terminate) a storing process, the control unit initiates (or terminates) the storing thread.

Abstract: A server device constituting a group management system includes one or more manufacturing apparatuses for performing a preset process on a target substrate, and the server device includes a measurement information storage unit for storing therein one or more measurement information; an instruction receiving unit for receiving an output instruction of the measurement information, which contains information specifying a predetermined start point and valid time information; a measurement information acquisition unit for acquiring, from the measurement information storage unit, measurement information ranging from the predetermined start point to a time point of the valid time; an output information composing unit for composing output information by using the acquired measurement information; and an output unit for outputting the output information composed by the output information composing unit.

Abstract: An electronic control device according to an embodiment of the present invention includes an arithmetic device such as a microcomputer having a watchdog timer circuit, and a runaway monitoring circuit which monitors the arithmetic device for an operational failure by receiving a pulse output from the arithmetic device, in which the watchdog timer circuit or the runaway monitoring circuit detects occurrence of a failure of the arithmetic device according to the state (high level or low level) of an indication signal (wakeup signal) which shows the operational state of the arithmetic device.

Abstract: A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error detection circuitry is provided for detecting a control path error associated with an error in operation of the control circuitry and data path error handling circuitry is arranged to handle recovery from errors in the data values. The control path error detection circuitry is configured to cause the data path error handling circuitry to perform recovery from detected control path errors enabling the series of data processing operations to continue despite the occurrence of the control path error. An associated method and computer program product are also provided.

Abstract: Disclosed is a method and system for modeling invariant relationships between flow intensity measurements in a distributed system. In the method, a measurement is randomly selected from a plurality of flow intensity measurements. The method searched for relationships between the randomly selected measurement and each remaining one of the plurality of flow intensity measurements, and each of the flow intensity measurements having a relationship with the randomly selected measurement is grouped into a cluster with the randomly selected measurement. The method than determines relationships between all of the flow intensity measurements in the cluster. This method is repeated with the remaining flow intensity measurements until all of the flow intensity measurements are grouped into a cluster.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: A printer comprising a reception unit for receiving a command or data sent from a host computer, a timer for counting elapsed time after the command or data is received, and an error detection unit for reporting that the host computer is in an error state when the command or data from the host computer is not received within a predetermined time after the timer starts counting the elapsed time.

Abstract: A program product is embedded in a media accessible by a computer operative to request a plurality of program tasks for wakeup so as to execute the plurality of program tasks in a predetermined schedule. The program product causes at least one of the computer and another computer to execute the instructions of measuring a delay period between a request of at least one of a plurality of program tasks and a wakeup thereof. The instructions include comparing the measured delay period with a predetermined first timeout value, thus determining whether at least one of the plurality of tasks is abnormally executed by the computer based on the comparison result.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: A gaming machine includes a processor adapted to execute a program of a game; a biometric reader configured to capture first biometric data from the player, and a trusted cache. The trusted cache includes a nonvolatile memory that is configured to store the first biometric data; a context data save engine configured to save the context of the program to the nonvolatile memory and to associate the stored first biometric data with the saved context of the program upon the processor receiving a request from the player to suspend game play, and a context data recovery engine configured to recover the saved context from the nonvolatile memory and to cause continued execution of the program from the recovered saved context upon the biometric reader capturing second biometric data from the player that matches the stored first biometric data and receiving a request from the player to resume game play.

Abstract: Methods, systems, and computer program products for identifying cyclical behaviors are provided. A method includes defining a time-based set of splines in an equation for a dataset, identifying a periodicity of a cycle derived from implementing the time-based set of splines on the dataset, and taking a responsive action as a result of identifying the periodicity of the cycle.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met, and recovering in a recovering step back from any of the nx escalation levels to a previous level or mode, if a de-escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: The present invention extends to methods, systems, and computer program products for maintaining message state at a message log. Messages are accumulated at a message log in accordance with a message retention policy. Any of a variety of message capture assurances can be used when capturing a message from a message producer within a message log. A message becomes visible to message consumers after the outcome of writing the message is known (either failure or success). Messages are requested using (e.g., monotonically increasing) sequence numbers. Messages are also dropped from the message log in accordance with the message retention policy.

Abstract: An industrial process control apparatus and method that includes a number of processors and a number of input/output modules. Each processor is connected to a plurality of the input/output modules by a unidirectional command line. Each input/output module is connected to a plurality of the processors by a unidirectional response line. The processors are arranged to issue an identifier request to all of the connected input/output modules and each input/output module is arranged to respond to the identifier request via the respective response line with a response that includes a unique identifier. Such a configuration allows each processor to identify the physical location of each respective input/output module.

Abstract: The present invention provides a connection manager, method, system and program product for centrally managing computer applications. Specifically, under the present invention, a connection manager is provided that centrally manages the applications through a queue broker, and communicates with components of a heartbeat manager and cleanup manager. The connection manager of the present invention provides, among other things, a centralized point for: (1) applications to directly connect to one another; (2) heartbeats of the applications to be monitored; and (3) any necessary cleanup actions to be implemented.

Abstract: A network having a plurality of subscribers has at least one message transmitter and at least one message receiver. The at least one message transmitter sends messages at predefined time intervals. The message receiver receives the messages at the predefined time intervals. A delay time of the messages is monitored on the basis of time outs. In addition, at least one of the subscribers repeatedly estimates a current delay time using a time measurement between sending out a request message and receiving a response message. The estimated delay time is compared with a predefined threshold value. If the estimated delay time exceeds the defined threshold value, an error signal is generated.

Abstract: A method for checking expected network traffic is disclosed. The method for checking expected network traffic includes accessing pre-registered expected results of a network traffic checking exercise that include expected packet content verification information for individual packets of the network traffic. In addition, the method includes accessing network traffic where individual packets of the network traffic include actual packet content verification information. Individual packets are identified that have expected packet content verification information that does not match their actual packet content verification information and individual packets are identified that have expected packet content verification information that does match their actual packet content verification information.

Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.

Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.

Abstract: The electronic control apparatus includes a microcomputer having a control function of controlling an actuator mounted on a vehicle in accordance with an input signal indicative of a running state of the vehicle, and a self-monitoring function of monitoring whether or not the control function is functioning properly on the basis of the input signal, and a monitor module communicably connected to the microcomputer and having a digital circuit for monitoring whether or not the self-monitoring function is functioning properly. The monitor module includes a reference counter counting up a clock serving as operation reference of the digital circuit. The microcomputer includes a module monitoring section configured to take in a count value of the reference counter and to monitor whether or not the monitor module is functioning properly on the basis of a changing state of the count value taken in.

Abstract: Hardware independent performance metrics for application tasks are assembled and submitted to a central repository from multiple installations in the field. These metrics are requested by and provided to specific computing devices, and used to calculate expected performance times for given application tasks on specific hardware configurations. Computing devices can automatically identify performance problems by comparing actual performance times of application tasks to calculated expected performance times. Events that take longer than expected to execute indicate a computing device performance issue.

Abstract: A network device for use in a communication system having a technical support center operated by a technical support staff, the technical support center being in communication with the network device through a packet switching network. The network device includes one or more hardware subsystems, one or more software subsystems and means for monitoring the status of the hardware and software subsystems so that when a problem occurs with respect to one or more of the hardware and software subsystems of the network device, the network device for transmitting a first message to the technical support center to notify the technical support center of the problem, wherein the technical support staff is able to diagnose the problem without interruption to the operation of the network device.

Abstract: A system is disclosed that can determine whether a routine is stalled. The system does not require the developer of the routine to add code for the purpose of detecting whether the routine is stalled. Furthermore, the system can be used to monitor various routines at different levels of granularity, such as at the thread level, method level, or other levels. One embodiment of the present invention allows a user to specify a method and an expected time frame. Code for that method is modified to add additional code that implements a timing mechanism. The timing mechanism is used to detect when a thread enters that method and does not return within an approximation of the expected time frame. Other embodiments are also within the scope of the present invention.

Abstract: In a global shared memory (GSM) environment, an initiating task at a first node with a host fabric interface (HFI) uses epochs to provide reliability of transmission of packets via a network fabric to a target task. The HFI generates a packet for the initiating task addressed to the target task, and automatically inserts a current epoch of the initiating task into the packet. A copy of the current epoch is maintained by the target task, which accepts for processing only packets having the correct epoch, unless the packet is tagged for guaranteed-once delivery. When a packet delivery is accepted, the target task sends a notification to the initiating task. If the initiating task does not receive the notification of delivery for the issued packet, the initiating task updates the epoch at both the target node and the initiating node and re-transmits the packet.

Abstract: The present invention relates to computers executing in time-share mode, under the control of their operating systems, a number of separate and independent application programs. The present invention relates in particular to the networks of onboard computer networks of IMA type executing application programs written independently of the hardware specifications of the computers and not permanently resident in the computers. The method of the present invention associates with the digital core of each computer of the network a monitoring state machine operating independently and in having the monitoring state machine monitor the correct observance by the associated computer of the time sequencing of the tasks and memory partition allocations. Furthermore, the monitoring state machines can be configured to execute monitoring service applications of time-out or watchdog type to which the application programs executed by the computers of the network can subscribe.

Abstract: A programmable processor calculates a hash value of a memory region, then monitors program operation to detect a security monitoring system initialization. The hash value is added to extend a security measurement sequence if the security monitoring system initialization clears a security state. Processors that implement similar methods, and systems using such processors, are also described and claimed.

Abstract: Avoiding failure repetition in data processing includes storing a sequence of circumstances leading up to a previous failure, monitoring circumstances in a current process, matching a sequence of circumstances in the current process to a stored sequence of circumstances, and applying rules to determine if the current process should proceed.

Abstract: An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined time till the reference time elapses.

Abstract: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to the microcontroller as interrupt events for processing. In order correctly to combine interrupt processing and watchdog operation, the watchdog circuit is connected to the interrupt circuit and cooperates therewith in such a way that the interrupt circuit feeds at most a predetermined number of interrupt events to the microcontroller within a watchdog period.

Abstract: Method and apparatus for identifying a cause for a response time problem for a transaction in a distributed computing system that includes a central server and a plurality of subsystems. Data is stored at each subsystem relating to sub-transactions of transactions performed by the subsystems. When a problem is discovered in connection with the completion of a particular transaction, each subsystem of the plurality of subsystems that was involved in the particular transaction is identified, and both instance data relating to all of the sub-transactions of the particular transaction stored at each identified subsystem and current hourly aggregate data stored at each identified subsystem is forwarded to the central server. Root-Cause Analysis is then performed using the forwarded instance data and aggregate data to identify the particular subsystem that caused the transaction problem.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A CPU reads a clear pattern held in a register in a watchdog timer when a system is booted up or reset, thereby determining whether or not the boot-up or the reset is a reset performed by the system or a reset due to runaway of a program to be executed and performing a process for booting up the system so as not to restart the task in which the runaway has occurred.

Abstract: A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.

Abstract: A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: A method for monitoring a system, having a control unit defined as a master and a number of control units defined as slaves, with the aid of a monitoring module, in which in reply to an inquiry from the master and the slaves a response is given in each instance and a joint response provided on the basis of these responses is checked by the monitoring module.

Abstract: A method for monitoring the correct operations of a data processing device including changing a subsystem from an authorized state to an unauthorized state, executing the partial operating sequence, and resetting any subsystem state from the unauthorized state to the authorized state.

Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.

Abstract: In addition to setting tasks and maintenance tasks for each portion of a storage apparatus, for which ease of operation is demanded, a storage system enables notification of a monitoring and maintenance terminal, for which high reliability is demanded, of fault information, without detracting from reliability. The functions of a SVP 23 and SVP 25 are functions to monitor the storage apparatus 3, and functions for notification to a remote maintenance center terminal 13 or similar, for which high reliability is demanded. The notification function involves notification to a remote maintenance center terminal 3 or similar of a fault or other event in the storage apparatus 3, detected by the monitoring function. The functions of the SVP 23 and SVP 25 are limited to functions for notification of faults in the storage apparatus 3, notification of information other than faults, and SNMP functions, so that the volume of the OS and other programs installed on the SVP 23 and SVP 25 is reduced.

Abstract: Systems for detecting unexpected program flow may include a hardware program flow monitor to generate an interrupt signal if a software program flow value does not match an incrementally updated hardware value when a processor executes a program flow check instruction. In some examples, a program of instructions may include a number of program flow check instructions. When a program flow check instruction is executed, the processor may send the software value to be compared to the hardware register value. In an illustrative example, program execution causes the hardware value to be incremented in a hardware register. Upon execution of a program flow check instruction, the hardware value is compared to a software value associated with the program flow check instruction to determine if the program instructions have been executed in an expected sequence (e.g., according to an expected program flow).

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: A method for providing remote management and maintenance of a node or service within a data communications network that is activated by the data communications network management system's receipt of signals of an abnormal condition at a node or service or failure to receive operational status signals from a node or service. A control adapter running on a node within a Point of Presence is started. The control adapter is capable of starting all service adapters associated with all services running on the node. Operational status signals and abnormal condition signals are transmitted from the control adapter and service adapters on to an information bus. If a network management control host receives abnormal condition signals, notification is sent to a remote system administrator that alerts of an error experienced by a node or service.

Abstract: A method and apparatus are provided for performing health check requests on one or more network devices or network resources. The method and apparatus provide a build tool for building a health check request having an extensible data format adaptable to a protocol supported by the network device or network resource of concern. The health check request can be built using data captured from a unit of network traffic on a transmission medium or with data provided via a user interface, or a combination of both. A health check request built using the method or apparatus can support any protocol including proprietary protocols avoiding the need for a requestor to learn a protocol format in order to build a health check request checking an operational characteristic of a network device or network resource. The method and apparatus allow this to be accomplished using data captured from a successful transaction.

Abstract: Occurrence of a failure in a computer system is appropriately detected, and information required for removing the failure is automatically collected.

Abstract: Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Abstract: Described are techniques for use with an error handling policy for a data storage system. Error handling criteria may be specified for controlling behavior of the data storage system upon the occurrence of an internal processing error occurring when performing an ancillary task associated with a data operation received by the data storage system. The error handling criteria may include a threshold counter value, and one or more of: a device, a specific device location or address, and a host. An error may be conditionally returned to the host upon the occurrence of an internal processing error in accordance with the error handling criteria.

Abstract: A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.