Abstract: An apparatuses for radio access network configuration for video approximate semantic communications includes a transceiver that receives from a transmitter a bitstream corresponding to a video coded data transmission wherein the received bitstream includes bitwise transmission errors and a processor that performs FEC decoding and correcting at least one bitwise transmission error of the video coded data transmission whereas at least one bitwise transmission error is left in a bit-inexact reception of the video coded data transmissions post FEC decoding, applies, by a smart video decoder in a video approximate semantic communications mode, semantic error correction to decoded video coded data transmissions to correct and conceal one or more video artifacts in response to the bit-inexact reception of the video coded data transmissions post FEC decoding, and reconstructs a video uncoded representation of concealed approximate semantic content relative to the received bitstream corresponding to the video coded da

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A network node is arranged to provide communication at least in an unlicensed band where clear channel assessment, CCA, is required before transmissions. The unlicensed band comprises a plurality of carriers, or sets of carriers, defining channels.

Abstract: A storage management technique involves: receiving from a requesting node a write request for writing target data into a first target storage space in a redundant array of independent disks (RAID); if a storage device associated with the first target storage space does not fail, acquiring first data stored in the first target storage space and a first parity value corresponding to the requesting node and stored in a parity storage space; determining a target parity value based on the target data, the first data, and the first parity value; and updating a stripe with the target data and the target parity value. Accordingly, locks caused by updating the parity value can be avoided, so that different nodes can perform parallel write to different storage spaces in the same stripe in the RAID.

Abstract: A cyclic redundancy check (CRC) system includes an input unit, a plurality of CRC engines for 1 byte to n/2 byte, and an output unit. The input unit has a data de-multiplexer for receiving n byte data. The plurality of CRC engines for 1 byte to n/2 byte are connected to the data de-multiplexer for processing demultiplexed n byte data. The output unit has a data multiplexer for providing processed CRC output data. The plurality of CRC engines for 1 byte to n/2 byte are arranged in two columns. A first column includes one or more CRC engines for 1 byte to n/2 byte and a second column includes a CRC engine for n/2 byte.

Abstract: A system and a method for monitoring the integrity of code are provided. Dummy code is provided in an on demand decryption area of an object file while runtime code is provided elsewhere (and may be in the same object file or another object file). A compensation area is also provided which is initially blank. During execution, checksums can be calculated based on the result of an exclusive or (XOR) operation between contents of the on demand code decryption area and a compensation area such as a compensation area. As the runtime code populates the on demand code decryption area with the runtime code (potentially with the exception of areas masked to maintain integrity of relocation instructions allowed to remain in the dummy code) the compensation area is populated with the result of an XOR operation between the dummy code and the runtime code. As a result, the checksums will be the same throughout execution as long as integrity of the code has not been compromised.

Abstract: A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit, and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the data are determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: Performance anomalies in production applications can be analyzed to determine the dynamic behavior over time of hosting processes on the same or different computers. Problematic call sites (call sites that are performance bottlenecks or that are causing hangs) can be identified. Instead of relying on static code analysis and development phase load testing to identify a performance bottleneck or application hang, a lightweight sampling strategy collects predicates representing key performance data in production scenarios. Performance predicates provide information about the subject (e.g., what the performance issue is, what caused the performance issue, etc.). The data can be fed into a model based on a decision tree to identify critical threads running the problematic call sites. The results along with the key performance data can be used to build a call graph prefix binary tree for analyzing call stack patterns. Data collection, analysis and visualizations of result can be performed.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device determines a respective operational state of each of one or more threads of a process executing on the embedded-system device. The embedded-system device stores the respective operational state of each of the one or more threads in a thread state register in a memory of the embedded-system device. The embedded-system device stores information data associated with the respective operational state of each of the one or more threads in the thread state register. The embedded-system device determines that operation of at least one thread of the one or more threads is abnormal. The embedded-system device retrieves the stored operational states of the one or more threads from the thread state register in response to the determination. The embedded-system device outputs the retrieved operational states.

Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

Abstract: A semiconductor device and or system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a command/address signal, a first datum and a second datum. The first semiconductor device may be configured to receive a comparison signal relating to the first datum and the second datum. The second semiconductor device may be configured to store a first error code of the first datum and a second error code of the second datum based on the command/address signal during a write operation. The second semiconductor device may be configured to compare the first error code with the second error code to output the comparison signal based on the command/address signal during a read operation.

Abstract: Technologies for secure software update include an update server and one or more client computing devices. The update server generates a software release including release components, such as packages and/or bundles, and a version number. The update server generates an integrity hash tree over the software release and a Lamport one-time signature key pair for each node of the integrity hash tree. The update server generates a Merkle signature scheme authentication tree based on the key pairs and signs each node of the integrity hash tree. The update server signs the root of the authentication tree with an anchor private key. A client computing device downloads one or more release components and verifies the release components with the integrity hash tree, the signatures, and the authentication tree. The client computing device verifies the root of the authentication tree with an anchor public key. Other embodiments are described and claimed.

Abstract: Code for an application programming interface (API) can be automatically generated. For example, a processing device can receive a definition data describing functional and behavioral characteristics of the API in an API description language. The processing device can also receive a template data defining code logic for the API. The template data can include (i) template code in a template language, and (ii) program code in a programming language that is different from the template language and the API description language. The processing device can generate source code in the programming language using the template data and the definition data by performing operations in accordance with the template code. The operations can include at least replacing template variables with corresponding values from the definition file. The processing device can then compile the source code into an executable file, and execute the executable file to implement the API.

Abstract: The present disclosure involves systems and methods for managing data in a distributed storage system. The distributed storage system may include non-volatile memory (NVM) storage devices and utilize erasure code replication for storage of data. A controller may first store at least some of the K data chunks in NVM devices before storing the coding chunks in other storage devices. In addition, the controller may transmit read requests to the NVM devices of the system first to begin receiving data chunks or coding chunks related to the data object. By writing to and reading from NVM devices first, storage and reading of the data object may occur faster than conventional storage systems.

Abstract: Systems and methods are presented for managing physical access to an access-controlled area using a local access control system. In certain embodiments, information that may be used in access control determinations managed by a remote domain controller may be communicated to a local access control system for use in connection with local access control determinations performed by the access control system independent of the domain controller. In some embodiments, such a configuration may allow for access control determinations to be performed when communication with the domain controller is interrupted and/or otherwise limited.

Abstract: A recovery method and apparatus for use in a redundant array of independent disks (RAID) storage device is provided that includes a plurality of nonvolatile memory devices. The recovery method includes: reading a data chunk, in which an uncorrectable error occurs, from the plurality of nonvolatile memory devices, selecting a plurality of sub-stripes including a parity and excluding the data chunk, and performing, in parallel, a first recovery operation of adjusting a read level to recover the data chunk and a second recovery operation of processing the plurality of sub-stripes to recover a sub-stripe including the data chunk. The parallel performance of the first and second recovery operations is completed according to an earlier completion of one of the first and second recovery operations.

Abstract: A method for verifying a target computer file with respect to a reference computer file, including defining a first area delimiting a portion of a reference file, and a second area delimiting a portion of a target file, the second area exhibiting the same size as the first area and being situated, inside the target file, at the same relative position with respect to the origin of this target file as the first area with respect to the origin of the reference file; calculating a first digital imprint, by applying a hash function solely to that portion of the reference file which is contained inside the first area to be tested; calculating a second digital imprint, by applying the same hash function solely to that portion of the target file which is contained inside the second area to be tested; comparing the first and second digital imprints.

Abstract: Devices, systems, and methods are provided that include a controller configured to receive a first data packet from a memory device; determine a bit error count for the first data packet; and determine whether the bit error count exceeds a predetermined threshold. When the bit error count exceeds the predetermined threshold, the controller corrects errors identified in the bit error count; generates and inserts pre-defined data into the first data packet at a location where errors occurred in the first data packet; and generates and inserts a tag into the first data packet. The tag includes information indicating a size and a location of the pre-defined data in the first data packet.

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Abstract: A memory system includes a memory device for storing data, and a controller for controlling the memory device by outputting control signals to the memory device. In the memory device, when an address of a selected operation is received in response to the control signals, the memory device simultaneously initializes a page buffer included in the memory device.

Abstract: A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a management device. The apparatus may be a management device. The management device receives a first command. The management device determines whether the management device is in a protected mode for executing a protected process. The management device, in response to a determination that the management device is in the protected mode, determines whether the first command, when executed, interrupts the execution of the protected process. The management device, in response to a determination that the first command interrupts the execution of the protected process, discards the first command.

Abstract: An integration device and an integration method thereof are provided. The integration device executes an artifact integration procedure to integrate the artifacts in a first database and the artifacts in the second database. Based on the access authority of each process role in the first database and the access authority of each process role added from the second database into the first database, the integration device further modifies a plurality of application programming interfaces associated with the integrated artifacts and modifies a plurality of processes according to the modified application programming interfaces. In addition, the integration device further executes a process role integration procedure to integrate the process roles of the first database and the process roles added from the second database into the first database.

Abstract: A data storage system, such as an archival storage system, implements failure decorrelation methods. In some embodiments, a selector is employed to select one or more data storage devices of a host for storage of incoming data. In some of such embodiments, the selector selects from among the storage devices in a random, pseudorandom, stochastic, or deterministic fashion so as to prevent correlation of one or more failure modes associated with storage of the data.

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.

Abstract: The present invention relates to methods and Validity securing arrangement and embodiments thereof for effectively securing validity of a target database in a node in a Lawful Interception Network. Said target database is intended to be identical to a source target database. The arrangement comprises a processing means being adapted to send a request for a target database checksum to the node comprising the target database, to receive a response comprising the target database checksum from the requested node, to compare the received target database checksum to a source target database checksum determined for the corresponding source target database, and to send an order to start an audit and synchronisation process if the two compared checksums differ.

Abstract: Embodiments herein described relate to methods for enabling the detection of inner pack receive errors at a receiving site for a marketplace by comparing quantities of predicted and received items by receiving a predicted quantity, determining a received quantity, performing a modulus division of the predicted and received quantities of items, and using the remainder to detect the presence of inner packs within received packages of items.

Abstract: A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.

Abstract: A database system and method for managing and storing sensitive and non-sensitive vehicle data. Received vehicle data messages are processed to separate out sensitive and non-sensitive data. The data is stored in a database having: an encrypted table, a plain-text table, and an identification mapping table. The encrypted table contains the sensitive data entries in an encrypted format. The plain-text table contains the non-sensitive data entries in a plaintext form. The identification mapping table contains a plurality of mapping data entries, wherein each mapping data entry associates a unique identifier to an affiliated identifier that is used to recall data from the encrypted table and the plain-text table.

Abstract: A stream architecture for data representation is disclosed. A stream is retained with respect to write transactions to a given volume. The stream includes the write transactions and provides a sequence of the write transactions according to the order in which the write transactions were received for the given volume. By way of example, a stream image can be associated to the stream. The stream image provides a representation of the data in the given volume for a point in time by referencing a non-contiguous subset of the sequence of write transactions in the stream.

Abstract: Methods and systems for enhanced error recovery are described. A first one or more data blocks to write to a first drive are received by a first drive controller module. A first parity block is calculated by the first drive controller module based on a first data block parity group. The first one or more data blocks are written by the first drive controller module to the first drive. The first parity block is written by the first drive controller module to the first drive.

Abstract: A decoding device includes a reception unit and a correction unit. The reception unit receives data obtained by segmenting transmit data into multiples of a predetermined number of bits, calculating parity data for each bit position in a segment, attaching the parity data to the transmit data, and performing bit number conversion coding on the transmit data so that a ratio of a frequency of occurrence of a first code and a frequency of occurrence of a second code becomes a predetermined ratio. The correction unit corrects a 1-bit error in the received data on a basis of a decoding error occurring in the bit number conversion coding performed on the data received by the reception unit, and a parity error detected according to the parity data from the received data obtained by decoding the data.

Abstract: In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison.

Abstract: A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.

Abstract: In a method, error detection and correction is performed on output data from a memory cell of a memory device to generate a result of error detection and correction. The memory cell is determined as a weak cell by determining a number of times of data retention failures of the memory cell based on the result of the error detection and correction. In a refreshing cycle, normal cells and the weak cell are refreshed and the weak cell is additionally refreshed at least once.

Abstract: Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.

Abstract: Techniques for improved multicast content delivery are described. In some embodiments, for example, an apparatus includes a processor circuit, a communication component operative by the processor circuit to receive a data transmission containing a description segment and a correspondence segment, a correspondence processing component operative by the processor circuit to determine a plurality of multicast content streams representing different versions of a media content based on the correspondence segment, and a selection component operative by the processor circuit to select and receive one or more of the plurality of multicast content streams based on characteristics identified in the description segment. In various such embodiments, the apparatus includes an adaptation component operative by the processor circuit to adaptively switch across the plurality of multicast content streams for reception and processing based on characteristics identified in the description segment.

Abstract: Techniques described and suggested herein include systems and methods for storing, indexing, and retrieving original data of data archives on data storage systems using redundancy coding techniques. For example, redundancy codes, such as erasure codes, may be applied to archives (such as those received from a customer of a computing resource service provider) so as allow the storage of original data of the individual archives available on a minimum of volumes, such as those of a data storage system, while retaining availability, durability, and other guarantees imparted by the application of the redundancy code. Sparse indexing techniques may be implemented so as to reduce the footprint of indexes used to locate the original data, once stored. The volumes may be apportioned into failure-decorrelated subsets, and archives stored thereto may be apportioned to such subsets.

Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.

Abstract: A security surveillance apparatus with a networking function and a video recording function and a failure detecting and repairing method for a storage device are provided. The failure detecting and repairing method includes the following steps. First, the storage device is powered and detected. Then, whether a file system of the storage device is abnormal is determined. When the file system is abnormal, the file system is repaired by a file system repairing procedure. Next, whether a multimedia file is abnormal is determined. When the multimedia file is abnormal, the multimedia file is repaired by a file repairing procedure. Finally, the storage device is mounted on the security surveillance apparatus.

Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

Abstract: The present invention provides a method and apparatus for detecting intrusions in a processor-based system. One embodiment of the method includes calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions. This embodiment of the method also includes issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated.

Abstract: A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.

Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract: A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.

Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: In one aspect, a method includes sending a conditional read request from a host to a storage array requesting data in a data block stored at the storage array. The conditional read request includes a first hash of data in the data block at the host. The method also includes determining a second hash of the data in the data block stored at the storage array, comparing the first hash and the second hash, sending a reply from the storage array to the host with the data in the data block stored at the storage array if the first hash and the second hash differ and sending a reply from the storage array to the host without the data in the data block stored at the storage array if the first hash and the second hash are the same.