Error Checking Code Patents (Class 714/52)
  • Patent number: 10296416
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Patent number: 10283174
    Abstract: A memory system includes a memory device for storing data, and a controller for controlling the memory device by outputting control signals to the memory device. In the memory device, when an address of a selected operation is received in response to the control signals, the memory device simultaneously initializes a page buffer included in the memory device.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventor: Yong Soon Park
  • Patent number: 10223187
    Abstract: A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ashok Raj, Narayan Ranganathan, Mohan J. Kumar, Vincent J. Zimmer
  • Patent number: 10198275
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a management device. The apparatus may be a management device. The management device receives a first command. The management device determines whether the management device is in a protected mode for executing a protected process. The management device, in response to a determination that the management device is in the protected mode, determines whether the first command, when executed, interrupts the execution of the protected process. The management device, in response to a determination that the first command interrupts the execution of the protected process, discards the first command.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 5, 2019
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Pravinash Jayapaul, Venkatesan Balakrishnan
  • Patent number: 10133769
    Abstract: An integration device and an integration method thereof are provided. The integration device executes an artifact integration procedure to integrate the artifacts in a first database and the artifacts in the second database. Based on the access authority of each process role in the first database and the access authority of each process role added from the second database into the first database, the integration device further modifies a plurality of application programming interfaces associated with the integrated artifacts and modifies a plurality of processes according to the modified application programming interfaces. In addition, the integration device further executes a process role integration procedure to integrate the process roles of the first database and the process roles added from the second database into the first database.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 20, 2018
    Assignee: Institute For Information Industry
    Inventors: Kai-Hsuan Chan, Yan-Ming Chen, Chien-Yao Wang
  • Patent number: 10102065
    Abstract: A data storage system, such as an archival storage system, implements failure decorrelation methods. In some embodiments, a selector is employed to select one or more data storage devices of a host for storage of incoming data. In some of such embodiments, the selector selects from among the storage devices in a random, pseudorandom, stochastic, or deterministic fashion so as to prevent correlation of one or more failure modes associated with storage of the data.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 16, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Paul David Franklin
  • Patent number: 10091249
    Abstract: The present invention relates to methods and Validity securing arrangement and embodiments thereof for effectively securing validity of a target database in a node in a Lawful Interception Network. Said target database is intended to be identical to a source target database. The arrangement comprises a processing means being adapted to send a request for a target database checksum to the node comprising the target database, to receive a response comprising the target database checksum from the requested node, to compare the received target database checksum to a source target database checksum determined for the corresponding source target database, and to send an order to start an audit and synchronisation process if the two compared checksums differ.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 2, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Amedeo Imbimbo, Lorenzo Fiorillo
  • Patent number: 10089173
    Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 10074071
    Abstract: Embodiments herein described relate to methods for enabling the detection of inner pack receive errors at a receiving site for a marketplace by comparing quantities of predicted and received items by receiving a predicted quantity, determining a received quantity, performing a modulus division of the predicted and received quantities of items, and using the remainder to detect the presence of inner packs within received packages of items.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 11, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Patrick Christopher Engdahl
  • Patent number: 10020822
    Abstract: A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: July 10, 2018
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Tong Zhang, Hao Wang
  • Patent number: 9946606
    Abstract: A stream architecture for data representation is disclosed. A stream is retained with respect to write transactions to a given volume. The stream includes the write transactions and provides a sequence of the write transactions according to the order in which the write transactions were received for the given volume. By way of example, a stream image can be associated to the stream. The stream image provides a representation of the data in the given volume for a point in time by referencing a non-contiguous subset of the sequence of write transactions in the stream.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 17, 2018
    Assignee: DataCore Software Corporation
    Inventors: Nicholas C. Connolly, Robert Bassett, Ziya Aral, Roni J. Putra
  • Patent number: 9946744
    Abstract: A database system and method for managing and storing sensitive and non-sensitive vehicle data. Received vehicle data messages are processed to separate out sensitive and non-sensitive data. The data is stored in a database having: an encrypted table, a plain-text table, and an identification mapping table. The encrypted table contains the sensitive data entries in an encrypted format. The plain-text table contains the non-sensitive data entries in a plaintext form. The identification mapping table contains a plurality of mapping data entries, wherein each mapping data entry associates a unique identifier to an affiliated identifier that is used to recall data from the encrypted table and the plain-text table.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 17, 2018
    Assignee: General Motors LLC
    Inventor: Primo Mark Pettovello
  • Patent number: 9830220
    Abstract: Methods and systems for enhanced error recovery are described. A first one or more data blocks to write to a first drive are received by a first drive controller module. A first parity block is calculated by the first drive controller module based on a first data block parity group. The first one or more data blocks are written by the first drive controller module to the first drive. The first parity block is written by the first drive controller module to the first drive.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: November 28, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: David W. Harvey
  • Patent number: 9819363
    Abstract: A decoding device includes a reception unit and a correction unit. The reception unit receives data obtained by segmenting transmit data into multiples of a predetermined number of bits, calculating parity data for each bit position in a segment, attaching the parity data to the transmit data, and performing bit number conversion coding on the transmit data so that a ratio of a frequency of occurrence of a first code and a frequency of occurrence of a second code becomes a predetermined ratio. The correction unit corrects a 1-bit error in the received data on a basis of a decoding error occurring in the bit number conversion coding performed on the data received by the reception unit, and a parity error detected according to the parity data from the received data obtained by decoding the data.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Tsutomu Hamada
  • Patent number: 9740557
    Abstract: In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 22, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Ranjit J Rozario, Ranganathan Sudhakar
  • Patent number: 9715428
    Abstract: A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 25, 2017
    Assignee: Sanmina Corporation
    Inventors: Abbas Morshed, Chuan-Wen George Tsang, Christopher Youngworth
  • Patent number: 9685217
    Abstract: In a method, error detection and correction is performed on output data from a memory cell of a memory device to generate a result of error detection and correction. The memory cell is determined as a weak cell by determining a number of times of data retention failures of the memory cell based on the result of the error detection and correction. In a refreshing cycle, normal cells and the weak cell are refreshed and the weak cell is additionally refreshed at least once.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sergiy Romanovskyy, Cormac Michael Oconnell
  • Patent number: 9575852
    Abstract: Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 21, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Young-Su Kwon
  • Patent number: 9565672
    Abstract: Techniques for improved multicast content delivery are described. In some embodiments, for example, an apparatus includes a processor circuit, a communication component operative by the processor circuit to receive a data transmission containing a description segment and a correspondence segment, a correspondence processing component operative by the processor circuit to determine a plurality of multicast content streams representing different versions of a media content based on the correspondence segment, and a selection component operative by the processor circuit to select and receive one or more of the plurality of multicast content streams based on characteristics identified in the description segment. In various such embodiments, the apparatus includes an adaptation component operative by the processor circuit to adaptively switch across the plurality of multicast content streams for reception and processing based on characteristics identified in the description segment.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 7, 2017
    Assignee: INTEL CORPORATION
    Inventor: Ozgur Oyman
  • Patent number: 9459959
    Abstract: Techniques described and suggested herein include systems and methods for storing, indexing, and retrieving original data of data archives on data storage systems using redundancy coding techniques. For example, redundancy codes, such as erasure codes, may be applied to archives (such as those received from a customer of a computing resource service provider) so as allow the storage of original data of the individual archives available on a minimum of volumes, such as those of a data storage system, while retaining availability, durability, and other guarantees imparted by the application of the redundancy code. Sparse indexing techniques may be implemented so as to reduce the footprint of indexes used to locate the original data, once stored. The volumes may be apportioned into failure-decorrelated subsets, and archives stored thereto may be apportioned to such subsets.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: October 4, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Paul David Franklin, Bryan James Donlan, Claire Elizabeth Suver
  • Patent number: 9417844
    Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 16, 2016
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 9411690
    Abstract: A security surveillance apparatus with a networking function and a video recording function and a failure detecting and repairing method for a storage device are provided. The failure detecting and repairing method includes the following steps. First, the storage device is powered and detected. Then, whether a file system of the storage device is abnormal is determined. When the file system is abnormal, the file system is repaired by a file system repairing procedure. Next, whether a multimedia file is abnormal is determined. When the multimedia file is abnormal, the multimedia file is repaired by a file repairing procedure. Finally, the storage device is mounted on the security surveillance apparatus.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 9, 2016
    Assignee: VIVOTEK INC.
    Inventor: Chien-Wei Chang
  • Patent number: 9342394
    Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Murugasamy Nachimuthu, Mohan J. Kumar, Theodros Yigzaw, Jose A. Vargas, Rajender Kuramkote
  • Patent number: 9141800
    Abstract: The present invention provides a method and apparatus for detecting intrusions in a processor-based system. One embodiment of the method includes calculating a first checksum from first bits representative of instructions in a block of a program concurrently with executing the instructions. This embodiment of the method also includes issuing a security exception in response to determining that the first checksum differs from a second checksum calculated prior to execution of the block using second bits representative of instructions in the block when the second checksum is calculated.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 22, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Reza Yazdani
  • Patent number: 9111648
    Abstract: A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: August 18, 2015
    Assignee: Apple Inc.
    Inventors: Avraham Poza Meir, Alexander (Sasha) Paley
  • Patent number: 9104542
    Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Ariel Szapiro, Alexander Gendler
  • Patent number: 8996926
    Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Simon Brewerton, Simon Cottam, Frank Hellwig
  • Patent number: 8984233
    Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: March 17, 2015
    Assignee: Microsoft Corporation
    Inventors: Thomas J. Miller, Jonathan M. Cargille, William R. Tipton, Surendra Verma
  • Patent number: 8984374
    Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiro Yoshihara
  • Patent number: 8984379
    Abstract: A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 17, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Bradley Engel, Brian Butcher
  • Patent number: 8954673
    Abstract: In one aspect, a method includes sending a conditional read request from a host to a storage array requesting data in a data block stored at the storage array. The conditional read request includes a first hash of data in the data block at the host. The method also includes determining a second hash of the data in the data block stored at the storage array, comparing the first hash and the second hash, sending a reply from the storage array to the host with the data in the data block stored at the storage array if the first hash and the second hash differ and sending a reply from the storage array to the host without the data in the data block stored at the storage array if the first hash and the second hash are the same.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 10, 2015
    Assignee: EMC International Company
    Inventors: Assaf Natanzon, Zvi Gabriel BenHanokh, Felix Shvaiger
  • Patent number: 8935580
    Abstract: Methods and apparatus for associating each data packet in a media stream with logic corresponding to a particular quality-of-service (QoS) and/or error correction requirement. In an exemplary embodiment, each packet in the media stream is assigned a frame tag which designates a particular quality-of-service and/or error correction scheme for the corresponding packet. At least a portion of each packet is encoded according to the packet's designated quality-of-service as indicated by the frame tag. A receiver accesses the frame tags from within the transmitted media stream in order to determine the appropriate means for processing or decoding the encoded portion of each packet. In this manner, each packet within the media stream can have its own quality-of-service and/or error correction requirements and processing, thereby enhancing link efficiency and better enforcing QoS policy across the system.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 13, 2015
    Inventor: Harry Bims
  • Patent number: 8930780
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Patent number: 8910131
    Abstract: A safety controller designed to control an automated installation having a plurality of sensors and a plurality of actuators. A method for generating a user program for the safety controller comprises the step of generating a source code having a number of control instructions for controlling the actuators and having a number of diagnosis instructions for producing diagnosis reports. Safety-related program variables are processed in failsafe fashion during execution of the control instructions. A machine code is generated on the basis of the source code. At least one checksum is determined for at least some of the machine code. The diagnosis instructions are ignored for the determination of the checksum.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: December 9, 2014
    Assignee: Pilz GmbH & Co. KG
    Inventors: Peter Moosmann, Matthias Reusch
  • Patent number: 8909854
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Yamagishi, Atsushi Shiraishi, Misao Hasegawa
  • Patent number: 8892963
    Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: November 18, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
  • Patent number: 8856603
    Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 7, 2014
    Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SAS
    Inventors: Florent Miller, Thierry Carriere, Antonin Bougerol
  • Patent number: 8850281
    Abstract: Technologies are generally described for secure digital signatures that employ hardware public physically unclonable functions. Each unique digital signature generator can be implemented as hardware such that manufacturing variations provide measurable performance differences resulting in unique, unclonable devices or systems. For example, slight timing variations through a large number of logic gates may be used as a hardware public physically unclonable function of the digital signature unit. The hardware digital signature unit can be parameterized such that its physical characteristics may be publicly distributed to signature verifiers. The verifiers may then simulate randomly selected portions of the signature for verification.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: September 30, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 8799562
    Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 8793440
    Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: July 29, 2014
    Assignee: Microsoft Corporation
    Inventors: Thomas J. Miller, Jonathan M. Cargille, William R. Tipton, Surendra Verma
  • Patent number: 8781114
    Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Michael Goessel, Rainer Goettfert
  • Patent number: 8767531
    Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
  • Patent number: 8768901
    Abstract: A method and apparatus for selectively storing data on a server. The method operates by accessing a computer file and defining a data block as a current block of data. The current block is subsequently checksummed using a rolling error identification code. The method then determines if the calculated checksum for the current block has been previously stored in a database. If a matching checksum for the data is found in the database, then a duplicate of the current block already exists and the process repeats by selecting a new block of data. Alternatively, if the calculated checksum is absent from the checksum and the process has advanced one block length, the process moves back one block length and stores the current block in an archive. Otherwise, the checksum advances one byte forward to form a new current block of data and the process repeats.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Symantec Operating Corporation
    Inventor: Robert Somerville
  • Patent number: 8762777
    Abstract: In a mechanism for supporting detection of a failure event, history information of a system including log information of the system including plural components and/or failure information output from each component upon occurrence of a failure in the system is collected. A detection rule for detecting an event included in a component related to the failure that has occurred is generated, and a symptom with additional information added to the generated detection rule is applied to detect the event that has caused the failure. System configuration information as configuration information of the system is acquired, and from the acquired system configuration information, partial configuration information as system configuration information related to the component that sent out the event the selection of which has been accepted is extracted. The extracted partial configuration information is added to the symptom to update the symptom.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yasuhisa Gotoh, Yuhsuke Kaneyasu
  • Patent number: 8762962
    Abstract: Embodiments of the methods and apparatus for automatic cross language program code translation are provided. One or more characters of a source programming language code are tokenized to generate a list of tokens. Thereafter, the list of tokens is parsed to generate a grammatical data structure comprising one or more data nodes. The grammatical data structure may be an abstract syntax tree. The one or more data nodes of the grammatical data structure are processed to generate a document object model comprising one or more portable data nodes. Subsequently, the one or more portable data nodes in the document object model are analyzed to generate one or more characters of a target programming language code.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: June 24, 2014
    Assignee: Beek Fund B.V. L.L.C.
    Inventors: Guy Ben-Artzi, Yotam Shacham, Yehuda Levi, Russell William McMahon, Amatzi Ben-Artzi, Alexei Alexevitch, Alexander Glyakov, Tal Lavian
  • Patent number: 8738988
    Abstract: A method for sending data from a transmitter to a receiver in a transmission network comprising receiving outgoing data that is eight-bits-ten-bits (8b10b) encoded at a Gigabit Ethernet (GE) line rate from a physical medium attachment (PMA) layer, 8b10b decoding the received outgoing data, 64-bits-to-66-bits (64b66b) encoding the 8b10b decoded outgoing data, forward error correction (FEC) encoding the 64b66b encoded outgoing data, and serializing and sending the 64b66b and FEC encoded outgoing data at the GE line rate to a physical medium dependent (PMD) layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventors: Huafeng Lin, Frank J. Effenberger, Zhishan Feng, Zhenping Wang
  • Patent number: 8726070
    Abstract: Out-of-order reconstruction of a RAID storage device at a replacement storage device enables the replacement storage device to execute I/O for reconstructed regions during reconstruction of the replacement storage device. In one embodiment, the failed storage device is analyzed to find recoverable information, which is copied to the replacement storage device to reduce the need for reconstruction. In another embodiment, the priority for region's reconstruction is increased upon detection of an I/O to the region. The I/O is queued until reconstruction of the region and then executed after reconstruction of that region so that I/O at the region need not be repeated during reconstruction of the remainder of the replacement storage device.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 13, 2014
    Assignee: Dell Products L.P.
    Inventors: Chandrashekar Nelogal, Bang Kim Le, Frank Widjaja Yu
  • Patent number: 8707140
    Abstract: A device (102) supports error correction. A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a table and to create codewords, the decoder storing the datagrams in table columns to create codewords in table rows. A user interface (126) is coupled to the decoder and configured to render images corresponding with the datagrams on the user interface. Advantages of the invention include efficient signal processing and prolonged battery life in mobile wireless devices.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: April 22, 2014
    Assignee: ST-Ericsson SA
    Inventors: Scott Guo, Manikantan Jayaraman
  • Patent number: 8707110
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 22, 2014
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 8706105
    Abstract: A method, system and machine-readable storage medium for providing fault tolerance in a distributed mobile architecture (dMA) system. The method includes receiving a message or failing to receive the message within a predetermined time relating to a first dMA gateway (dMAG) at a second dMAG. It is determined whether the first dMAG is not operational or is otherwise offline based on the received message or the failure to receive the message. One or more dMA nodes associated with the first dMAG are notified in order to request connections to an external system via the second dMAG. The external system is also notified to request connections to one or more dMA nodes associated with the first dMAG via the second dMAG.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 22, 2014
    Assignee: Lemko Corporation
    Inventor: Shaowei Pan