Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: The present invention relates to a coprocessor comprising a calculation unit for executing a command, and a securization device for monitoring the execution of the command and supplying an error signal having an active value as soon as the execution of the command begins and an inactive value at the end of the execution of the command, if no abnormal progress in the execution of the command has been detected. The coprocessor further comprises means for preventing access to at least one unit of the coprocessor, while the error signal is on the active value. Application is provided particularly but not exclusively to the protection of integrated circuits for smart cards against attacks by fault injection.

Abstract: A cable transmitter supports a number of low density parity check (LDPC) coding rates, e.g., 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10; and supports a number of quadrature amplitude modulation (QAM) schemes, e.g., 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM or higher. For a selected modulation scheme, the cable transmitter selects between using a non-uniform symbol constellation or a uniform symbol constellation as a function of a selected coding rate.

Abstract: In a communications channel coupled to multiple duplicated subsystems, a method, interposer and program product are provided for verifying integrity of subsystem responses. Within the communications channel, a first checksum is calculated with receipt of a first response from a first subsystem responsive to a common request, and a second checksum is calculated for a second response of a second subsystem received responsive to the common request. The first checksum and the second checksum are compared, and if matching, only one of the first response and the second response is forwarded from the communications channel as the response to the common request, with the other of the first response and the second response being discarded by the communications channel.

Abstract: A computer program product, apparatus, and method for providing exception condition feedback at a control unit to a channel subsystem in an I/O processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a command message at the control unit from the channel subsystem, and detecting an exception condition in response to unsuccessful execution of at least one command in the command message. The method further includes identifying a termination reason code associated with the exception condition, writing the termination reason code to a response message, and sending the response message to the channel subsystem.

Abstract: A system and method for compiler error recovery, comprising analyzing the syntactic structure of a first program in a first programming language, wherein the first program can be represented by a first set of tokens, detecting a syntax error in the first program, remedying the syntax error by adding at least one token to the first set of tokens according to one of: 1) a prefix definition; and 2) an idiom definition, and wherein the detection of the syntax error occurs at the behest of an extensible compiler framework.

Abstract: Disclosed is a method of verifying the integrity of data acquired from a device emulating a hard disk to a host computer over a data transfer pathway. A storage medium containing known data is connected to the data transfer pathway, the storage medium capable of emulating a hard disk. The known data is transferred from the storage medium to the host computer over the data transfer pathway for storage on the host computer. A characteristic of the data stored on the host computer is compared with a corresponding characteristic of said known data to determine whether data corruption has occurred during data transfer over said data transfer pathway. The characteristic could be a hash code value, such as a Message-Digest 5 (MD5) or Secure Hash Algorithm (SHA) value.

Abstract: An embodiment relates generally to a method of restoring data in storage systems. The method includes providing for a current snapshot of a primary storage system at a secondary storage system and mounting an empty volume in the primary storage system. The method also includes receiving a request for a selected block of data in the primary storage system and retrieving a restore block from the secondary storage system, where the restore block encompasses the selected block of data. The method further includes writing the restore block to the empty volume in the primary storage system as an incremental restore process.

Abstract: According to an aspect of an embodiment, a memory controller for writing data into and reading data from a memory, comprises an error detector for detecting an error of data stored in the memory when reading the data, a time stamper for generating first time information indicative of the time when data is written into the memory, the first time information being written together with the data into an address location of the memory where the error has been detected, a timer for measuring a time period from the time indicated by the first time information until the time of subsequent occurrence of an error of data stored in said address location and a counter for counting a number of accesses to the address location over the time period.

Abstract: A method and apparatus for multi-layer integration for use in error recovery is disclosed. An error is detected in a multimedia data based on a first layer protocol and the detected error in the multimedia data is concealed based on a second layer protocol. In one aspect, the error in a multimedia data is detected based on a communication layer protocol and controlled based on a transport layer protocol. An error distribution of the controlled error is then determined based on a sync layer protocol and the detected error in the multimedia data is concealed based on an application layer protocol. In another aspect, a method and apparatus for multimedia data processing comprises error recovery as well as scalability. Finally, a method and apparatus as disclosed allows processing of multimedia stream by receiving multiple streams of encoded multimedia data, performing error recovery on an erroneous portion of a stream, and reconstructing the multimedia data from the multiple streams.

Abstract: When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.

Abstract: As disclosed herein, an interface for a device adapted to couple to an interconnect may comprise decode and error check logic and a plurality of decode logic units. The decode and error check logic may receive error check bits and a target address from the interconnect and may determine whether the target address was received in error. At least one of the decode logic units also may receive the error check bits and correct the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

Abstract: A data storage method comprises storing first data in at least a first data chunk, wherein the first data chunk is a logical representation of one or more sectors on at least a first disk drive in a storage system; storing first metadata, associated with the first data, in at least a first appendix, wherein the first appendix is a logical representation of a sector region on at least the first disk drive in the storage system, and wherein the first metadata comprises first atomicity metadata (AMD) and first validity metadata (VMD) associated with the first data; and storing a copy of the first VMD for the first data in at least one low latency non-volatile storage (LLNVS) device.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: Disclosed is a bus module that can be connected to a bus system and comprises means for outputting safety-relevant signals in the form of repeated unambiguous code sequences. The bus module further comprises a first and second arithmetic unit with means for executing software programs. A code generator program of the first arithmetic unit generates a first partial code sequence of the code sequence while a code generator program of the second arithmetic unit generates the remaining portion of the code sequence as a second partial code sequence. Advantageously, a proper code sequence is output at the output of the bus module only when both arithmetic units function properly. A deviation in the code sequence that is output can then be detected by a monitor or actuator.

Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.

Abstract: The invention relates to a method for controlling data-processing software modules (4, 5, 6, 7), wherein the data to be processed are organized in files, and wherein the processing is performed in a plurality of successive processing sections and the files in one processing section are processed by at least one software module (4, 5, 6, 7). To prevent the propagation and spreading of deviations occurring during the processing in the software modules (4, 5, 6, 7) in subsequent processing sections, information about the data processed are collected in the software modules (4, 5, 6, 7) of the processing sections and are signalized to a control system (8), said control system (8) comparing the information signalized and stopping the processing in a subsequent processing section if the comparison of the information revealed that a predetermined, admissible maximum deviation has been exceeded.

Abstract: A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.

Abstract: An example system and method for generating an error code involve detecting an error condition of a product and generating an error code by combining information indicative of the detected error condition with an identifier associated with, the product.

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.

Abstract: A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.

Abstract: A system and method of updating firmware and a method of creating firmware are provided. The system includes a firmware storage module having first firmware and second firmware. The first and second firmware each have image header file data, including a cyclic redundancy checksum (CRC) and an image header file creation time. The method of updating firmware includes determining whether the first and second firmware have an abnormality according to the CRC information. When an abnormality is present in the first or second firmware, the abnormality-stricken firmware is replaced with new firmware. When the abnormality is absent from the first and second firmware, the first firmware is compared with the second firmware in terms of the image header file creation time such that the firmware with the earlier creation time is replaced by the new firmware. Operable firmware is available even if the firmware updating operation fails.

Abstract: A method, system and program product for validating a runtime environment deployed across multiple computing systems is disclosed. The method includes generating, using a validation tool, a first set of checksums corresponding to message flows in a first instance of a runtime module deployed on a first system, the validation tool excluding in the first set of checksums generated any unique system data corresponding to the first system, while reading only common executable data of the runtime module. The method further includes running the validation tool on at least a second system for generating a second set of checksums corresponding to message flows in a second instance of the runtime module deployed on the second system. Further, the method includes comparing the second set of checksums to the first set of checksums to validate that the runtime module deployed on the second system is identical to the first system.

Abstract: A method for a model checking algorithm is provided. The method includes determining whether a class representative for a state has been processed, and generating a successor state for the state when the class representative for the state has not been processed. The method also includes determining which of a plurality of nodes is assigned to process the successor state, and processing the successor state at a node of the plurality of nodes that is assigned to process the successor state. Additionally another method for checking a model of a system is provided. This method processes a plurality of states for the model with a plurality of nodes using a distributed model checking technique. Each of the plurality of nodes uses symmetry reduction techniques to check if a representative state for a first state has been processed prior to processing the first state.

Abstract: A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data block associated with a first address and a second data block associated with a second address. In response, the slave device may send to the master device a portion of the first data block in a first burst and a portion of the second data block in a second burst via a plurality of bidirectional data paths. The slave device may further generate and send to the master device via one or more unidirectional data paths a cyclic redundancy code (CRC) based upon the first data block and the second data block.

Abstract: According to one embodiment, a memory interface module is configured to read one of instructions stored in a memory in accordance with a memory address designated by a fetch request issued from a processor. An error detection module is configured to detect an error in the read instruction. An instruction transmission module is configured to send to the processor, upon detection of an error in the read instruction, a first instruction to hold on a stack the same memory address as the one designated by the fetch request and a second instruction to jump to an error correction routine for correcting an error of the read instruction.

Abstract: Where code execution results in an error attributable to multiple data elements, the code is revised so the error results from one element. Where execution improperly functions without error, and the elements contain required but missing properties, the code is improperly functioning in its required-property handling. Errors are organized into classes and error-causing elements are organized into independent sets corresponding to the classes. Elements that are not within any set are determined. Symptom, error, no-error, refined-symptom, and function databases can be employed during code execution analysis. Symptom database entries correspond to elements and indicate errors, or that no errors, are attributable to the elements. Error database entries correspond to elements resulting in errors upon execution. No-error database entries correspond to elements resulting in no errors upon execution. Refined-symptom database entries correspond to root cause elements of errors.

Abstract: A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.

Abstract: An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC format detection and switching without requiring a user to have knowledge of the format or how to accomplish its change.

Abstract: An agent of a storage area network generates a first checksum value for a first set of zone configuration data used to at least initially configure the storage area network. At a later time, after a potential change to the first zone configuration data of the storage area network, the agent generates a checksum value based on current zone configuration data presently used to configure the zone in the storage area network. The agent then compares the first checksum value and the second checksum value to identify whether there has been a change to the first zone configuration data. That is, if the first checksum value does not equal the second checksum value, the agent flags that there has been a change to zone configuration data of the storage area network. Users can control behavior of zoning importation and activation depending on whether current zone configuration data has been changed.

Abstract: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: To copy protect an optical disc, such as a DVD, program chains additional to the main program chain are provided. These program chains may lead to the genuine data but in an incomplete or incorrect order or to false data. Sufficient additional program chains are provided to make it difficult to identify the main program chain amongst all of the program chains provided on the disc. The structure of the further program chains ape that of the main program, again to hide the main program chain. The navigation path which leads to the main program chain, and hence to the content on the DVD, is dynamically generated and at least some of the information required to generate the navigational path arises by setting parameters associated with a player or with a user. Thus a search of all of the navigation information on the disc will fail to reveal the navigation path to the content.

Abstract: A signal transmission apparatus is connected to a network as one node among a plurality of nodes involved in the network which is provided with an audio signal transmission period for transmitting a plurality of channels of audio signals each transmission cycle and a control data transmission period for transmitting control data of the plurality of the nodes each control cycle by using an idle time period other than the audio signal transmission period. In the signal transmission apparatus, a storage section stores configuration information of the one node. A transmitting section transmits the control data including an error checking code of the configuration information. A receiving section receives request data from another node, the request data requesting the one node for transmission of an information block of the configuration information. A control section controls the transmitting section to transmit the information block in response to the request data.

Abstract: A Fast Backup Storage and fast Recovery of Data (FBSRD) method for a facility, preferably with a SAN, coupled to a network with servers and workstations, operating in both a storage mode and a recovery mode. Coupled to the network are a primary storage, a repository, and a Backup Appliance computer BA. The BA runs a Backup Computer Program in association with at least one computer. When in storage mode, data is retrieved out of primary storage for back up, by taking snapshots and saving the retrieved data into repository in block format. In recovery mode, backed-up data is retrieved from repository and recovered into primary storage in either one of both block format and file format. The BA runs interactively with an Agent Computer Program residing in each server and workstation, and with a Backup User Interface management computer program operated by a user.

Abstract: In one embodiment, the present invention is a method for automatically preventing errors in computer software. The method includes storing the computer software in a code repository; executing a plurality of software verification tools to verify the computer software, wherein each of the plurality of software verification tools automatically generates one or more test cases; generating verification results responsive to executing the plurality of software verification tools and the automatically generated test cases; processing the verification results for generating an objective criterion of quality of the computer software; and customizing the scope of one or more of the plurality of verification tools responsive to the objective criterion of quality of the computer software.

Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.

Abstract: A booting system includes: a non-XIP memory, for storing a plurality of booting images, wherein the booting images comprise a source image and a plurality of duplicates of the source image; an XIP memory, coupled to the non-XIP memory; and a code shadowing module, coupled to the non-XIP memory and the XIP memory, for shadowing a specific booting image to the XIP memory if no errors are detected when carrying out error detection (EDC) checking on the specific booting image; wherein if at least a specific part of a booting image does not pass EDC checking, the code shadowing module shadows error-free parts of the booting image to the XIP memory, carries out EDC checking on at least a duplicate of the specific part, and then shadows an error-free part corresponding to the specific part to the XIP memory.

Abstract: A computer system includes a plurality of system boards each of which includes two systems arranged in a duplicated structure and a data relay device. The data relay device includes a degeneration determining unit that determines whether each of the systems is degenerated based on a signal that is transmitted from the each of the systems; a dummy-information creating unit that creates dummy information by adding dummy data to identification information and destination information, the identification information indicating a head of proper data that is transmitted from one of the systems constituting the duplicated structure with the other system that has been determined as being degenerated, and the destination information indicating destination of the data; and a data transmitting unit that transmits, as synchronized data, proper information that is transmitted from the one of the systems, and the dummy information.

Abstract: Described are techniques for performing data recovery processing for two failed devices included in a set of devices. It is determined whether the two failed devices are each one of the data devices, a horizontal parity device, or a diagonal parity device. Each of the data devices is partitioned into N?1 data segments. The horizontal parity device includes N horizontal parity segments each including parity information for a horizontal grouping of N?1 of the data segments. The diagonal parity device includes N diagonal parity segments each including parity information for a diagonal grouping of N?1 of the data segments. Recovery processing is performed to recover two failed devices in accordance with the diagonal parity device, the horizontal parity device, and the data devices.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.

Abstract: Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Abstract: A method and apparatus for enhancing performance of parity check in computer readable media is provided. For example, in a RAID (N+1) configuration, a virtual data strip is added for a calculation of parity. Data of the virtual data strip is set so that a predetermined portion of a data area in the virtual data strip has a predetermined value. Consequently, performance of parity check performed in a data processing system having a RAID configuration can be enhanced.

Abstract: A data transmission apparatus and a data transmission method for receiving an input of control frame and a data frame, transmitting or discarding the data frame according to the control frame input, outputting the control frame, and outputting the data frame which has been transmitted. This enables discarding of an error frame in the middle of transmission, thereby preventing waste of a band on the network or the waste of the destination host processing ability by the error frame.

Abstract: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.

Abstract: Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly.

Abstract: An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.