Error Checking Code Patents (Class 714/52)
-
Patent number: 8935580Abstract: Methods and apparatus for associating each data packet in a media stream with logic corresponding to a particular quality-of-service (QoS) and/or error correction requirement. In an exemplary embodiment, each packet in the media stream is assigned a frame tag which designates a particular quality-of-service and/or error correction scheme for the corresponding packet. At least a portion of each packet is encoded according to the packet's designated quality-of-service as indicated by the frame tag. A receiver accesses the frame tags from within the transmitted media stream in order to determine the appropriate means for processing or decoding the encoded portion of each packet. In this manner, each packet within the media stream can have its own quality-of-service and/or error correction requirements and processing, thereby enhancing link efficiency and better enforcing QoS policy across the system.Type: GrantFiled: June 18, 2013Date of Patent: January 13, 2015Inventor: Harry Bims
-
Patent number: 8930780Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.Type: GrantFiled: August 28, 2012Date of Patent: January 6, 2015Assignee: LSI CorporationInventors: Shaohua Yang, Bruce A. Wilson
-
Patent number: 8910131Abstract: A safety controller designed to control an automated installation having a plurality of sensors and a plurality of actuators. A method for generating a user program for the safety controller comprises the step of generating a source code having a number of control instructions for controlling the actuators and having a number of diagnosis instructions for producing diagnosis reports. Safety-related program variables are processed in failsafe fashion during execution of the control instructions. A machine code is generated on the basis of the source code. At least one checksum is determined for at least some of the machine code. The diagnosis instructions are ignored for the determination of the checksum.Type: GrantFiled: October 19, 2011Date of Patent: December 9, 2014Assignee: Pilz GmbH & Co. KGInventors: Peter Moosmann, Matthias Reusch
-
Patent number: 8909854Abstract: According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition.Type: GrantFiled: March 20, 2012Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Yamagishi, Atsushi Shiraishi, Misao Hasegawa
-
Patent number: 8892963Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.Type: GrantFiled: November 9, 2006Date of Patent: November 18, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
-
Patent number: 8856603Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.Type: GrantFiled: June 18, 2009Date of Patent: October 7, 2014Assignees: European Aeronautic Defence And Space Company EADS France, Astrium SASInventors: Florent Miller, Thierry Carriere, Antonin Bougerol
-
Patent number: 8850281Abstract: Technologies are generally described for secure digital signatures that employ hardware public physically unclonable functions. Each unique digital signature generator can be implemented as hardware such that manufacturing variations provide measurable performance differences resulting in unique, unclonable devices or systems. For example, slight timing variations through a large number of logic gates may be used as a hardware public physically unclonable function of the digital signature unit. The hardware digital signature unit can be parameterized such that its physical characteristics may be publicly distributed to signature verifiers. The verifiers may then simulate randomly selected portions of the signature for verification.Type: GrantFiled: May 12, 2009Date of Patent: September 30, 2014Assignee: Empire Technology Development LLCInventor: Miodrag Potkonjak
-
Storage apparatus and data control method for generating and storing format data and guarantee codes
Patent number: 8799562Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.Type: GrantFiled: December 28, 2012Date of Patent: August 5, 2014Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Junji Ogawa -
Patent number: 8793440Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.Type: GrantFiled: June 17, 2010Date of Patent: July 29, 2014Assignee: Microsoft CorporationInventors: Thomas J. Miller, Jonathan M. Cargille, William R. Tipton, Surendra Verma
-
Patent number: 8781114Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.Type: GrantFiled: September 7, 2005Date of Patent: July 15, 2014Assignee: Infineon Technologies AGInventors: Berndt Gammel, Michael Goessel, Rainer Goettfert
-
Patent number: 8767531Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.Type: GrantFiled: June 14, 2011Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Frank D. Ferraiolo, William R. Kelly, Robert J. Reese, Susan M. Rubow, Michael B. Spear
-
Patent number: 8768901Abstract: A method and apparatus for selectively storing data on a server. The method operates by accessing a computer file and defining a data block as a current block of data. The current block is subsequently checksummed using a rolling error identification code. The method then determines if the calculated checksum for the current block has been previously stored in a database. If a matching checksum for the data is found in the database, then a duplicate of the current block already exists and the process repeats by selecting a new block of data. Alternatively, if the calculated checksum is absent from the checksum and the process has advanced one block length, the process moves back one block length and stores the current block in an archive. Otherwise, the checksum advances one byte forward to form a new current block of data and the process repeats.Type: GrantFiled: May 1, 2012Date of Patent: July 1, 2014Assignee: Symantec Operating CorporationInventor: Robert Somerville
-
Patent number: 8762962Abstract: Embodiments of the methods and apparatus for automatic cross language program code translation are provided. One or more characters of a source programming language code are tokenized to generate a list of tokens. Thereafter, the list of tokens is parsed to generate a grammatical data structure comprising one or more data nodes. The grammatical data structure may be an abstract syntax tree. The one or more data nodes of the grammatical data structure are processed to generate a document object model comprising one or more portable data nodes. Subsequently, the one or more portable data nodes in the document object model are analyzed to generate one or more characters of a target programming language code.Type: GrantFiled: June 15, 2009Date of Patent: June 24, 2014Assignee: Beek Fund B.V. L.L.C.Inventors: Guy Ben-Artzi, Yotam Shacham, Yehuda Levi, Russell William McMahon, Amatzi Ben-Artzi, Alexei Alexevitch, Alexander Glyakov, Tal Lavian
-
Patent number: 8762777Abstract: In a mechanism for supporting detection of a failure event, history information of a system including log information of the system including plural components and/or failure information output from each component upon occurrence of a failure in the system is collected. A detection rule for detecting an event included in a component related to the failure that has occurred is generated, and a symptom with additional information added to the generated detection rule is applied to detect the event that has caused the failure. System configuration information as configuration information of the system is acquired, and from the acquired system configuration information, partial configuration information as system configuration information related to the component that sent out the event the selection of which has been accepted is extracted. The extracted partial configuration information is added to the symptom to update the symptom.Type: GrantFiled: March 12, 2013Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Yasuhisa Gotoh, Yuhsuke Kaneyasu
-
Patent number: 8738988Abstract: A method for sending data from a transmitter to a receiver in a transmission network comprising receiving outgoing data that is eight-bits-ten-bits (8b10b) encoded at a Gigabit Ethernet (GE) line rate from a physical medium attachment (PMA) layer, 8b10b decoding the received outgoing data, 64-bits-to-66-bits (64b66b) encoding the 8b10b decoded outgoing data, forward error correction (FEC) encoding the 64b66b encoded outgoing data, and serializing and sending the 64b66b and FEC encoded outgoing data at the GE line rate to a physical medium dependent (PMD) layer.Type: GrantFiled: June 27, 2011Date of Patent: May 27, 2014Assignee: Futurewei Technologies, Inc.Inventors: Huafeng Lin, Frank J. Effenberger, Zhishan Feng, Zhenping Wang
-
Patent number: 8726070Abstract: Out-of-order reconstruction of a RAID storage device at a replacement storage device enables the replacement storage device to execute I/O for reconstructed regions during reconstruction of the replacement storage device. In one embodiment, the failed storage device is analyzed to find recoverable information, which is copied to the replacement storage device to reduce the need for reconstruction. In another embodiment, the priority for region's reconstruction is increased upon detection of an I/O to the region. The I/O is queued until reconstruction of the region and then executed after reconstruction of that region so that I/O at the region need not be repeated during reconstruction of the remainder of the replacement storage device.Type: GrantFiled: September 27, 2010Date of Patent: May 13, 2014Assignee: Dell Products L.P.Inventors: Chandrashekar Nelogal, Bang Kim Le, Frank Widjaja Yu
-
Patent number: 8706105Abstract: A method, system and machine-readable storage medium for providing fault tolerance in a distributed mobile architecture (dMA) system. The method includes receiving a message or failing to receive the message within a predetermined time relating to a first dMA gateway (dMAG) at a second dMAG. It is determined whether the first dMAG is not operational or is otherwise offline based on the received message or the failure to receive the message. One or more dMA nodes associated with the first dMAG are notified in order to request connections to an external system via the second dMAG. The external system is also notified to request connections to one or more dMA nodes associated with the first dMAG via the second dMAG.Type: GrantFiled: June 27, 2008Date of Patent: April 22, 2014Assignee: Lemko CorporationInventor: Shaowei Pan
-
Patent number: 8707129Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.Type: GrantFiled: June 20, 2013Date of Patent: April 22, 2014Assignee: Interdigital Technology CorporationInventor: Kyle Jung-Lin Pan
-
Patent number: 8707140Abstract: A device (102) supports error correction. A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a table and to create codewords, the decoder storing the datagrams in table columns to create codewords in table rows. A user interface (126) is coupled to the decoder and configured to render images corresponding with the datagrams on the user interface. Advantages of the invention include efficient signal processing and prolonged battery life in mobile wireless devices.Type: GrantFiled: September 19, 2006Date of Patent: April 22, 2014Assignee: ST-Ericsson SAInventors: Scott Guo, Manikantan Jayaraman
-
Patent number: 8706701Abstract: Example embodiments of the present invention provide authenticated file system that provides integrity and freshness of both data and metadata more efficiently than existing systems. The architecture of example embodiments of the present invention is natural to cloud settings involving a cloud service provider and enterprise-class tenants, thereby addressing key practical considerations, including garbage collection, multiple storage tiers, multi-layer caching, and checkpointing. Example embodiments of the present invention support a combination of strong integrity protection and practicality for large (e.g., petabyte-scale), high-throughput file systems. Further, example embodiments of the present invention support proofs of retrievability (PoRs) that let the cloud prove to the tenant efficiently at any time and for arbitrary workloads that the full file system (i.e.Type: GrantFiled: June 30, 2011Date of Patent: April 22, 2014Assignee: EMC CorporationInventors: Emil P. Stefanov, Marten E. Van Dijk, Alina M. Oprea, Ari Juels
-
Patent number: 8707110Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.Type: GrantFiled: September 6, 2013Date of Patent: April 22, 2014Assignee: Rambus Inc.Inventors: Ian Shaeffer, Craig E. Hampel
-
Patent number: 8677141Abstract: A client-side enforcement mechanism may allow application security policies to be specified at a server in a programmatic manner. Servers may specify security policies as JavaScript functions included in a page returned by the server and run before other scripts. At runtime, and during initial loading, the functions are invoked by the client on each page modification to ensure the page conforms to the security policy. As such, before a mutation takes effect, the policy may transform that mutation and the code and data of the page. Replicated code execution may take place at both the client and the server where the server runs its own shadow copy of a client-side application in a trusted execution environment so that the server may check that the method calls coming from the client correspond to a correct execution of the client-side application The redundant execution at the client can be untrusted, but serves to improve the responsiveness and performance of the Web application.Type: GrantFiled: November 23, 2007Date of Patent: March 18, 2014Assignee: Microsoft CorporationInventors: Ulfar Erlingsson, Yinglian Xie, Ben Livshits, Cedric Fournet
-
Patent number: 8671250Abstract: A data storage device is disclosed comprising a non-volatile memory. A write command is received comprising a first logical block address (LBA) and first user data, and a second LBA and second user data. The first LBA is mapped to a first physical block address (PBA) for addressing a first memory segment. The second LBA is mapped to a second PBA for addressing a second memory segment. First redundancy is generated in response to the first user data, second redundancy in generated in response to the second user data, and parity data is generated in response to the first and second user data. Third redundancy is generated in response to the parity data and in response to at least one of the first LBA and the first PBA and at least one of the second LBA and the second PBA.Type: GrantFiled: December 15, 2011Date of Patent: March 11, 2014Assignee: Western Digital Technologies, Inc.Inventor: Patrick J. Lee
-
Patent number: 8667332Abstract: A method for optimizing a diagnostic reasoner model, for use in connection with a diagnostic system for testing a system under test of an aircraft, includes the steps of querying for a plurality of primary indicators, further querying for a plurality of supplemental indicators, and updating the diagnostic reasoner model based at least in part on the supplemental indicators. The primary indicators identify one or more potential faults in the system under test. Each supplemental indicator provides information either validating or invalidating a particular primary indicator or association of primary indicators.Type: GrantFiled: April 24, 2007Date of Patent: March 4, 2014Assignee: Honeywell International Inc.Inventors: Raj M. Bharadwaj, Darryl G. Busch, Daniel P. Johnson, Ranjana Ghosh
-
Patent number: 8667029Abstract: A computer system having a transaction based file system is disclosed. The computer system includes file system software that manages the file data and the file system structure of files stored on a persistent data storage device and maintains a transaction file that includes a plurality of transaction records. The file system software executes a startup process in which a reconstructed file system is generated in random access memory from the transaction records. The startup process may skip verification of some of the transactions. The file system software may error check at least one of the skipped transactions in response to a request to access a file identified by a file node record in the reconstructed filed system after the startup process is completed.Type: GrantFiled: August 30, 2011Date of Patent: March 4, 2014Assignee: QNX Software Systems LimitedInventor: Dan Dodge
-
Patent number: 8661300Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: GrantFiled: June 27, 2011Date of Patent: February 25, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
-
Electronic device, memory controlling method thereof and associated computer-readable storage medium
Patent number: 8656089Abstract: An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence.Type: GrantFiled: June 24, 2011Date of Patent: February 18, 2014Assignee: Mstar Semiconductor, Inc.Inventors: Chia-Ming Hsu, Wen-Hao Sung -
Patent number: 8656252Abstract: A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.Type: GrantFiled: May 3, 2012Date of Patent: February 18, 2014Assignee: Panasonic CorporationInventors: Hirokazu So, Toshiyuki Honda
-
Patent number: 8650461Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.Type: GrantFiled: June 3, 2013Date of Patent: February 11, 2014Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Yoav Kasorla
-
Patent number: 8650440Abstract: A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.Type: GrantFiled: January 16, 2008Date of Patent: February 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Michael Rohleder, Gary Hay, Stephan Mueller, Manfred Thanner
-
Patent number: 8645800Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.Type: GrantFiled: April 19, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Roy Daron Cideciyan, Hisato Matsuo, Thomas Mittelholzer, Kenji Ohtani, Paul J Seger, Keisuke Tanaka
-
Patent number: 8627153Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N?K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (?).Type: GrantFiled: September 2, 2008Date of Patent: January 7, 2014Assignees: STMicroelectronics SA, Centre National de la Recherche Scientifique (CNRS)Inventors: Adrian Voicila, David Declercq, Marc Fossorier, François Verdier, Pascal Urard
-
Patent number: 8621326Abstract: An error correction circuit 1 in accordance with an aspect of the invention includes an associative memory 20, a logic circuit 10 disposed in parallel with the associative memory 20, and selection unit 30 that receives an output signal from the associative memory 20 and an output signal from the logic circuit 10 as an input. The associative memory 20 includes a table that handles an input signal as a word and holds an output signal related to the word and an error correction code used to correct the output signal as data. The associative memory 20 further includes error correction unit that outputs a signal in which an error was corrected based on data related to a word corresponding to an input signal. The selection unit 30 selects and outputs one of an output signal from the associative memory 20 and an output signal from the logic circuit 10.Type: GrantFiled: June 29, 2010Date of Patent: December 31, 2013Assignee: NEC CorporationInventor: Shusaku Uchibori
-
Patent number: 8611229Abstract: Disclosed are a retransmission method, a base station, and a user device in a multicast system. In order to reduce uplink signaling resource, a new MNI (Multiple NACK Indicator) message is added to an uplink common feedback channel in an existing E-MBMS system. The MNI message enables decision of an XOR retransmission group which satisfies the XOR retransmission condition. As compared to a conventional XOR retransmission, the number of uplink signalings does not depend on the number of receivers. That is, when a plenty of receptions are present, it is possible to significantly reduce uplink signalings.Type: GrantFiled: January 21, 2009Date of Patent: December 17, 2013Assignee: Panasonic CorporationInventors: Qiang Wu, Ming Xu, Zheng Zhao, Atsushi Sumasu, Katsuhiko Hiramatsu
-
Patent number: 8572461Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.Type: GrantFiled: April 2, 2012Date of Patent: October 29, 2013Assignee: Interdigital Technology CorporationInventor: Kyle Jung-Lin Pan
-
Patent number: 8566682Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.Type: GrantFiled: June 24, 2010Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, Patrick J. Meaney, Lisa C. Gower
-
Patent number: 8566689Abstract: An integrity unit can be calculated from a first data unit, and a first storage device can be requested to store the first data unit. A second storage device, which can be separate from and/or a different type of device from the first storage device, can be requested to store metadata, which includes the integrity unit, in nonvolatile memory. Also, a second data unit can be received from the first storage device in response to a request for the first data unit. The integrity unit can be received from the second storage device, and the second data unit and the integrity unit can be analyzed to determine whether the second data unit matches the first data unit. Alternatively, a first integrity unit can be stored in a metadata region of a nonvolatile memory block, where the block also stores the data from which the first integrity unit was calculated.Type: GrantFiled: October 22, 2009Date of Patent: October 22, 2013Assignee: Microsoft CorporationInventors: Shiv K. Rajpal, Vladimir Sadovsky, Robin A. Alexander
-
Patent number: 8566685Abstract: A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.Type: GrantFiled: December 29, 2010Date of Patent: October 22, 2013Assignee: Hynix Semiconductor Inc.Inventor: Choung-Ki Song
-
Patent number: 8566686Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.Type: GrantFiled: May 13, 2011Date of Patent: October 22, 2013Assignee: LSI CorporationInventor: Naveen Krishnamurthy
-
Patent number: 8555116Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.Type: GrantFiled: November 1, 2012Date of Patent: October 8, 2013Assignee: Rambus Inc.Inventors: Ian Shaeffer, Craig E. Hampel
-
Patent number: 8549383Abstract: A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.Type: GrantFiled: August 24, 2011Date of Patent: October 1, 2013Assignee: Oracle International CorporationInventors: Ramaswamy Sivaramakrishnan, Aaron S. Wynn, Connie Wai Mun Cheung, Satarupa Bose
-
Patent number: 8514852Abstract: There exists a need to reduce re-transmission delays in real time feeds (such as video) by sending the packet with sufficient repair/recovery information inside the packet container so the relaying stations and/or the receiving devices can fix errors in transmission by perusing the contents of the packet and the repair information, and modify the packet and then relay it. By providing the relaying station the ability to fix the error, retransmission of the packet is avoided along each relay station along the network path from source to destination and also by receiving devices that would otherwise request a re-transmission. This application teaches a method so real time streams (e.g. video) may be more efficiently transported over a CSMA based network.Type: GrantFiled: November 24, 2009Date of Patent: August 20, 2013Assignee: Mesh Dynamics, Inc.Inventors: Francis daCosta, Sriram Dayanandan
-
Patent number: 8516600Abstract: An information processing device, for executing content reproduction processing from an information recording medium, includes a security information processing unit for determining output messages based on security check information in a content reproduction sequence, and outputting a message output command accompanied by selection information of the output message to a user interface processing unit, and a user information processing unit for obtaining message information based on the selection information input from said security information processing unit and outputting to a display unit.Type: GrantFiled: September 23, 2011Date of Patent: August 20, 2013Assignee: Sony CorporationInventor: Yoshikazu Takashima
-
Patent number: 8510608Abstract: Provided is an information security apparatus that has enhanced stability and confidentiality of a hash key. The information security apparatus includes an information generating PUF unit that has tamper resistance set, using physical characteristics, so as to output a preset hash key, a partial error-correction information storage unit that stores partial error-correction information, an error correcting PUF unit that has tamper-resistance set, using physical characteristics, so as to output error-correcting PUF information, an error-correction information generating unit that generates error-correction information using partial correction information and the error-correcting PUF information, and an error correcting unit that corrects an error for the hash key outputted from the information generating PUF unit and outputs an error-corrected hash key.Type: GrantFiled: November 2, 2007Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Yuichi Futa, Kaoru Yokota, Masao Nonaka, Manabu Maeda, Natsume Matsuzaki
-
Patent number: 8504847Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.Type: GrantFiled: April 18, 2010Date of Patent: August 6, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Wesley Leggette
-
Patent number: 8495241Abstract: Provided are a communication apparatus and a method therefor that are capable of executing a checksum attachment processing without increase of a circuit scale. A data generating unit (for example, a CPU) that forms a communication apparatus generates data, and stores the data in a memory. A checksum processor calculates a checksum for the data read from the memory, and writes the checksum into a predetermined position in the data stored in the memory. A data sending unit (for example, a transmission processor, a MAC processing circuit, and a PHY processing circuit) reads the data having the written checksum from the memory, and sends the data to a network.Type: GrantFiled: August 12, 2009Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventor: Weiyu Wu
-
Patent number: 8479079Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.Type: GrantFiled: April 9, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Roy Daron Cideciyan, Hisato Matsuo, Thomas Mittelholzer, Kenji Ohtani, Paul J Seger, Keisuke Tanaka
-
Patent number: 8479080Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.Type: GrantFiled: June 24, 2010Date of Patent: July 2, 2013Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Yoav Kasorla
-
Patent number: 8468426Abstract: Methods and apparatus for associating each data packet in a media stream with logic corresponding to a particular quality-of-service (QoS) and/or error correction requirement. In an exemplary embodiment, each packet in the media stream is assigned a frame tag which designates a particular quality-of-service and/or error correction scheme for the corresponding packet. At least a portion of each packet is encoded according to the packet's designated quality-of-service as indicated by the frame tag. A receiver accesses the frame tags from within the transmitted media stream in order to determine the appropriate means for processing or decoding the encoded portion of each packet. In this manner, each packet within the media stream can have its own quality-of-service and/or error correction requirements and processing, thereby enhancing link efficiency and better enforcing QoS policy across the system.Type: GrantFiled: July 2, 2008Date of Patent: June 18, 2013Assignee: Apple Inc.Inventor: Harry Bims
-
Patent number: 8397107Abstract: A data storage device is disclosed comprising a non-volatile memory including a plurality of memory segments. A write command is received comprising a logical block address (LBA) and user data. The LBA is mapped to a physical block address (PBA) for addressing one of the memory segments. First error code redundancy is generated in response to the LBA, and second error code redundancy in response to the PBA. User data and the first and second error code redundancy are written to the memory segment addressed by the PBA.Type: GrantFiled: December 11, 2009Date of Patent: March 12, 2013Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, William B. Boyle