Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.

Abstract: Described are techniques for processing data requests in connection with an I/O operation. A write data request is sent from a host to a target data storage system. The host performs a data validation, such as a checksum calculation, using the data of the data request. The data request is sent to the target data storage system. The target data storage system may be enabled to perform data validation processing on a per device basis by setting one or more device flag bits for a device. The target data storage system performs data validation processing in accordance with the flag bit settings of a device associated with a data request. A target checksum value using the data received on the target data storage system is determined and compared to the host checksum value in order to determined data validity. Data recovery processing is performed if data corruption is determined.

Abstract: Disclosed are a system and method for forwarding data packets from ingress ports to egress ports on a switch. A forwarding circuit may commence forwarding data packets from an ingress port through a switch fabric to a transmit queue of an egress port prior to completion of a checksum operation.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: A technique includes writing blocks of data from a plurality of servers to an array of disks that are shared in common by the servers. Prior to the writing in each block of data to the array of disks, the method includes storing in a journal a copy of the block of data to be written to the array of disks. Also stored in the journal is at least one header, and this header(s) indicates that the copy was successfully stored in the journal.

Abstract: The present invention is directed to a method and system for high bandwidth fault tolerance in a storage system while the system, maintaining dual parity scheme, may tolerate the failure of more than one disk. An array controller may comprise a parity buffer sufficiently large enough to hold all of the parity blocks for an entire stripe of data. This may provide for high bandwidth fault tolerance without reading the source blocks twice while the dual parity values are calculated using two different/independent parity computations for a given stripe. Such a dual parity scheme may allow the storage system to tolerate the failure of more than one disk.

Abstract: A method for identifying, managing, and signaling uncorrectable errors among a plurality of clusters of symmetric multiprocessors (SMPs) detects, manages and reports data errors. The method allows merging of newly detected errors, including memory, cache, control, address, and interface errors, into existing error status. Also, error status is distributed in several possible formats, including separate status signals, special UE (uncorrectable errors) ECC codewords, encoded data patterns, parity error injection, and response codepoints. The error status is also available for logging and analysis while the machine is operating, allowing for recovery and component failure isolation as soon as the errors are detected without stopping the machine.

Abstract: Disclosed is a technique for fault isolation. A first error check is performed on a block of data in storage to determine whether the block of data was corrupted after the block of data was transferred from memory to the storage. When the first error check indicates that the block of data was corrupted, a second error check is performed using the block of data in the memory to determine whether the block of data was corrupted before being transferred from the memory. When the second error check indicates that the block of data was corrupted before being transferred from the memory, it is determined that the block of data was corrupted before being stored in the memory. When the second error check indicates that the block of data was corrupted after being transferred from the memory, it is determined that the block of data was corrupted by at least one of the memory or a formatter that performed the transfer.

Abstract: A bus bridge circuit is connected to first and second buses and performs data transfer between devices. In the bus bridge circuit, a new parity bit is generated from a parity bit generated by a first PCI device and from a byte enable signal from a second PCI device, and is transmitted to the second PCI device, together with read data from the first PCI device. Consequently even if the byte enable values are different on the primary-side and secondary-side buses, parity errors on the secondary-side bus can be correctly transmitted to the primary-side bus.

Abstract: A semiconductor memory comprises, a data memory having a plurality of memory regions to store data at addresses specified, a code memory having the same address space as the data memory to store error correction codes, an error correction code control circuit including an error correction code generation circuit, a syndrome generation circuit and an error correction code decoding circuit, generating an error correction code for correcting data before the data is written back into the memory region, and comparing the generated error correction code with corresponding error correction code, thereby to determine whether the data is erroneous, and an error correction code function invalidity control circuit invalidating an error correction function of the error correction code control circuit when the memory regions are accessed first after power application.

Abstract: A retransmission control apparatus for use in a radio communication system that uses an orthogonal frequency division multiplexing technique, the apparatus comprising a transmitter which transmits to a radio station a data sequence, which serves as communication data that has been transformed into a time waveform of an orthogonal frequency division multiplexing symbol; a receiver which receives from the radio station a retransmission request for retransmitting the communication data; a transformation mechanism configured to transform, in response to the retransmission request, the data sequence of the communication data to be retransmitted into an orthogonal frequency division multiplexing symbol having a time waveform different from the time waveform of the orthogonal division multiplexing symbol which had been sent before the retransmission request; and a retransmitting mechanism configured to retransmit the communication data transformed by the transformation mechanism to the radio station.

Abstract: A method of storing defective data site information for a storage device according to a particular embodiment of the invention includes determining a first defective data site associated with the storage device, determining a second defective data site associated with the storage device, determining a spacing value that represents spacing between the first defective data site and the second defective data site, and storing the spacing value. Apparatus and method aspects according to other embodiments of the invention also are disclosed.

Abstract: An example of a method for error tracking includes sending a data object to a first location. This example also includes determining if the data object was successfully stored at the first location, and if so, storing meta data corresponding with the data object, wherein the meta data includes first path information. This example of the method also includes sending the data object to a second location. This example further includes determining if the data object was successfully stored at the second location, and if so, adding second path information to the meta data corresponding with the data object, to update the meta data. Some examples of the invention may be called a data centric error tracking and problem analysis method (and system), because the error tracking is generally based on the path traveled by the data.

Abstract: An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.

Abstract: A proxy generator produces computer code for compilation as a client-side proxy in support of client-server distributed software applications. Using information from a software “contract” file that defines the desired functionality of the distributed application, and, optionally, from a configuration file that tailors proxy operation for a specific application, the proxy generator generates proxy code for compilation as a generated proxy. This generated proxy interfaces a client application with a server application, and insulates the client application from the complexities of distributed computing. More particularly, the generated proxy automatically includes exception-handling mechanisms tailored to the software contract for both recoverable and non-recoverable errors. Information in the configuration file determines the generated proxy's response to recoverable errors, such as the number of retries attempted for a given type of network communication error.

Abstract: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise.

Abstract: A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.

Abstract: One embodiment of the present invention provides a system that fixes bit errors encountered during references to a cache memory. During execution of an application, the system performs a reference to the cache memory by retrieving a data item and an associated error-correcting code from the cache memory. Next, the system computes an error-correcting code from the retrieved data item and compares the computed error-correcting code with the associated error-correcting code. If the computed error-correcting code does not match the associated error-correcting code a bit error has occurred. In this case, the system stores an identifier for the reference in a register within a set of one or more registers associated with the cache memory, so that the bit error can be fixed at a later time. The system also allows the application to continue executing.

Abstract: In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed.

Abstract: An information recording device includes a control unit and a memory interface unit. An ICV for each sector data of data to be stored in units of sectors is stored in the redundant part of each sector. An ECC and an ICV are stored in the redundant part of each sector, so that sector-unit ICV storage can be performed without reducing the storage capacity of the data part of the sector. processing that combines data parts by using the file system of a device can be performed similarly to conventional data combination processing that only combines data parts in which ones purely used as data are stored. The control unit does not have any load because only each sector which is regarded as valid (no interpolation) as a result of ICV checking is transmitted to the control unit, and the ICV checking is performed by the memory interface unit.

Abstract: A method for transmitting/receiving wireless data and an apparatus therefor according to the quality of an application service and features of a coder/decoder (CODEC) of an application layer are provided. The method for transmitting/receiving wireless data includes the steps of: establishing a catalog of information related to the application data service; adding header information of each layer by referring to the catalog established in the above step, and error detecting codes to the application data; deciphering a header if data errors are detected by the error detecting codes added to the data during the reception, and transmitting the data to the upper ranking layer according to the quality of service, if the deciphered value of the header belongs to the catalog established in the above step.

Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor.

Abstract: A method, apparatus and computer program product are provided for implementing uncorrectable error isolation in a computer system while the system continues to run. A memory controller performs data fetching from a system memory, capturing error information, and responsive to detecting an uncorrectable error, generates a predefined attention to a service processor. The service processor utilizing a processor runtime diagnostic (PRD) program, reads the captured error data and identifies a memory extent with the uncorrectable error. Then the memory controller performs accelerated scrubbing of the identified memory extent with the uncorrectable error, capturing error information and responsive to a scrub correctable error threshold being exceeded, sends a predefined scrub threshold exceeded attention to the service processor. The service processor reads the captured error data and identifies a failed memory chip.

Abstract: A flexible format for heterogeneous data records includes a fixed-length header containing a header ECC, a table of contents descriptor, and a table of contents ECC descriptor; a variable-length table of contents containing multiple entries, each entry containing a record descriptor and a corresponding record ECC descriptor; multiple variable-length records corresponding to the multiple entries in the table of contents; and optional ECCs corresponding to the ECC descriptors. Preferably, the format is used for vital component data in non-volatile memory of a computer system field replaceable unit, and is read by the system to identify the unit and configure the system.

Abstract: A signaling mechanism associated with errors in a processor are promoted or demoted based on a set of stored values.

Abstract: When a program is activated, data recorded in a predetermined sector is reproduced by an error correction. When no reproduction error occurs, the data in the predetermined sector is reproduced without conducting the error correction. When reproduced data are not a predetermined pattern, it is determined that write software illegally writes dummy data to the predetermined sector, instead of the predetermined pattern, and an optical disc where the program is activated is a copied optical disc. Accordingly, a process conducted by the program is terminated. Therefore, a process realizing original functions based on the program cannot be executed.

Abstract: A method of allocating data sites of a storage device based on quality of the data sites, according to a particular embodiment of the invention, includes determining the quality of the data sites of the storage device by determining attribute information for the data series, and allocating certain of the data sites as spare data sites, based on their quality, for use in accommodating one or more defects in the storage device.

Abstract: Methods, apparatus and systems are directed to managing network traffic using a variable length Cyclical Redundancy Check (CRC) index to hash an address header. The invention copies an address header of a data packet to a CRC generator. A CRC index is determined based, in part, on the address header. A subset of bits is determined from the CRC index based, in part, on a predetermined bit mask. The address header and the data payload are then combined with the subset of bits from the CRC index. The modified data packet is subsequently forwarded over a network. In one embodiment, the invention is implemented on a hardware circuit residing on a traffic device.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device; (B) compressing the programming item to present a compressed item; (C) storing the programming item in a programming field of the file in response to generating; and (D) storing the compressed item in a non-programming field of the file in response to compressing.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device, (B) storing the programming item in a programming field of the file in response to generating, and (C) storing at least one of the parameters in a non-programming field of the file.

Abstract: An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

Abstract: Respective error detection codes (CRC) are selectively added to respective source coded signal parts depending on the type of source coded signal part. Further, important source coded signal parts may be provided with respective error detection codes, whereas less important source coded parts are not provided with error detection codes. If the source coded signal comprises source coded packets, the error detection codes (CRC) may relate to a part of given source coded packets (p2), e.g. a header (H).

Abstract: In order to control efficiently a flash memory in the case where small-scale data are frequently rewritten, a method of controlling a flash memory in which a data storage region is divided into unit sectors and data can be erased by every sector as a unit, is configured that the sector comprises a sector control region and a plurality of pages, and included are both available/unavailable flag information about the page concerned and an occupied/unoccupied map showing a data storage location of the data storage region on the page concerned. By employing such a configuration, it is easy to decide whether the page referred to is available or unavailable and the configuration is suitable for frequently renewing and adding pages, which are of a large quantity and on a small scale.

Abstract: Described are techniques used in detection of a data corruption in a computer system. A host issues a write request that includes a checksum value determined in accordance with data associated with the write request. The write request is received by a data storage system that performs data validation using the checksum. If the data validation succeeds, the write operation proceeds. Otherwise, it is determined that the data is corrupt and a checksum error is returned to the issuing host. The host issues a vendor-defined write request operation that includes the checksum as a data field in the request packet sent to the data storage system. Filter drivers are used in obtaining the checksum and modifying the write request packet to specify a vendor-defined write operation if checksumming is enabled for the write operation.

Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: A system and method for verifying integrity of data signals communicated from a data transmit device to a receive device over a communications channel of limited bandwidth. The method comprising steps of: a) detecting instances of idle data transmit activity at the transmit device; b) accumulating data integrity information for data transmitted over the communication channel between detected idle transmit instances, the accumulating being performed by data integrity verifier devices at both transmit and receive devices; c) communicating accumulated data integrity information for data transmitted since a last detected idle data transmit instance during a current detected idle data transmit instance; and, d) verifying accumulated data integrity information communicated over the channel at the receiver device.

Abstract: Disclosed is one embodiment of a system and method for negotiating a compression technique while signaling is occurring in a communications network, the method comprising sending a message with a compression negotiation indicator, receiving a response to the message, determining if the response contains an error code in response to the compression header, if the message contains an error code, then continuing signaling without using compression techniques. On the other hand, if the message does not contain an error code, then the method negotiates a compression technique and may continue signaling with the negotiated compression technique.

Abstract: Described are techniques used in detection of a data corruption in a computer system in connection with read and write operations. For a write operation, a host issues a write request that includes a checksum value determined in accordance with data associated with the write request. The write request is received by a data storage system that performs data validation using the checksum. The host issues a vendor-defined write request operation that includes the checksum as a data field in the request packet sent to the data storage system. For a read operation, a host issues a read request and the data storage system determines a checksum value before servicing the read request. The checksum is validated at the top of the I/O stack on the host by the file system filter driver.

Abstract: The present invention provides systems and methods for providing run-time type checking to prevent software errors. In architecture, a representative system includes a compiler that parses a program and further comprises a logic that generates a checksum for a block of code in the program, a logic that stores the checksum in the block of code, and a logic that inserts checksum instruction code into the block of code. The present invention can also be viewed as a method for providing run-time type checking to prevent software errors. A representative method operates by generating a checksum for a block of code in the program, and storing the checksum in the block of code. During execution of the program, a run-time checksum is generated for the block of code, and the block of code is executed if the checksum equals the run-time checksum, and the execution of the block of code is skipped if the checksum does not equals the run-time checksum.

Abstract: An apparatus and method for detecting and controlling audible errors in a sound communication system at the receiver utilizes channel quality data and also iterative synthesis. Errors occurring in synthesized speech are detected by searching for atypical sound with a stringency dependent upon channel quality. The greater the channel quality deficiency is, the higher the typicality standards will be. Errors are controlled by either re-synthesizing the signal in an iterative way using typicality standards which vary with channel quality deficiency, or by modifying the output signal using typicality standards which vary with channel quality deficiency, or both.

Abstract: A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the entry is changed. In another embodiment, each status bit is provided with a corresponding shadow status bit. Each status bit and its corresponding shadow status bit is always loaded with the same data. In this manner, every change 1-bit change to a status bit is made as two identical 1-bit changes to the status bit and its corresponding shadow status bit. The two identical 1-bit changes are parity neutral, thereby permitting status changes without requiring recomputing and saving a new parity.

Abstract: The present invention provides systems and methods for preventing software errors caused by address range or alignment errors. In architecture, a representative system includes a compiler that parses a program and further comprises a logic that generates a verification value for a block of code in the program, a logic that stores the verification value in the block of code, and a logic that inserts verification value instruction code into the block of code. The present invention can also be viewed as a method for preventing software errors in a program. A representative method operates by generating a verification value for a block of code in the program, and storing the verification value in the block of code. During execution of the program, a runtime verification value is generated for the block of code, and the block of code is executed if the verification value equals the runtime verification value, and generates an error message if the verification value does not equals the runtime verification value.

Abstract: A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and then deferring the reporting of the transmission error. The method defers the reporting of the transmission error by saving a sequence number for the message and by setting a deferred error flag in a state saved for the flow. The method processes the deferred transmission error when it receives an acknowledgement that completes an immediately preceding message in the flow. When a positive acknowledgement is received, the deferred transmission error is reported. When a negative acknowledgement is received, the deferred transmission error is ignored and a remote error is reported.

Abstract: An intelligent MP3 error check detection method and apparatus. The claimed invention discloses an apparatus and method where all MP3 files are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The parameter W is not constant and conceptually represents a state of the error check method. The destructive value of a first predefined constant is added to the parameter W each time the integrity of the data within the frame cannot be verified. The constructive value of a second predefined constant is subtracted from the parameter W each time the integrity of the data within the frame is successfully verified. If the value of the parameter W equals or exceeds a predefined threshold, the remainder of the MP3 file is decoded and played without error check protection.

Abstract: In a sending unit, a deblocking circuit deblocks parent data into each piece of unit data, an ID-generating circuit generates an ID, and an ECC-generating circuit generates an ECC for a data sequence having unit data and an ID. A sending/receiving circuit sends the data sequence having the unit data and the ECC to a transmission path as send data. In the receiving unit, a sending/receiving circuit receives the send data as receive data. An ID-generating circuit generates an expected ID for the unit data in the receive data. An ECC calculating circuit calculates an expected ECC for the data sequence having the unit data and the expected ID. A compare circuit compares the ECC and the expected ECC. When both values are not identical, a resend-request circuit issues a resend request including the expected ID to the sending unit. When the ECC and the expected ECC are identical, a blocking circuit blocks each piece of unit data.

Abstract: A system for performing data error recovery includes a memory unit and a memory controller. The memory unit includes a plurality of memory locations, and the memory controller maintains a checksum in one of the memory locations. At various times, the memory controller receives requests to update the checksum with data values identified by the requests. In response, the memory controller combines the checksum with these data values and stores the foregoing data values into memory. In one embodiment, the memory controller stores the foregoing data values into a plurality of stacks based on which protection domains are associated with the data values. In response to a detection of a data error, the memory controller retrieves a plurality of the stored data values and recovers a previous state of a particular memory location by combining each of the retrieved data values to the checksum.

Abstract: A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.

Abstract: The invention relates to a method for protecting the program flow during sub-program calls. Known methods for protecting data contract the evaluation of data by specific interruption of the program, do not however offer any effective protection for modular programs, especially with regard to sub-program calls. According to the invention, the requested program therefor checks the data communicated directly or indirectly by the requesting program before or during the execution of the program.