Abstract: A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.

Abstract: Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test.

Abstract: A method for operating a memory that includes a plurality of analog memory cells includes storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group. After storing the data, respective second cell values are read from the memory cells in the first group, and differences are found between the respective first and second cell values for each of one or more of the memory cells in the first group. The differences are processed to produce error information, and the error information is stored in a second group of the memory cells.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: The invention provides a method for writing test data to a memory. In one embodiment, the memory comprises a data register. First, test data is written to a memory space of the memory. A read-back command and a read-back address of the memory space are then sent to the memory to direct the memory to read the test data from the memory space to the data register. A copy-back command and a copy-back command in a test range of the memory are then sent to the memory to direct the memory to write the test data stored in the data register to the copy-back address. Finally, when the test range of the memory has not been filled with the test data, the step of sending the read-back command and the read-back address is repeated, and the step of sending the copy-back command and the copy-back address is repeated.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.

Abstract: A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.

Abstract: A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.

Abstract: Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount of incorrect data stored in the volatile memory after a period of time during which the device was without power. The amount of incorrect data is used to determine the period of time during which the device was without power. A method of controlling a device based on the amount of incorrect data stored in a volatile memory after the device was without power is also disclosed. For example, the device can be controlled by altering a start-up sequence of one or more elements of the device.

Abstract: Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.

Abstract: A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer.

Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory.

Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. In one or more embodiments, the test module can include a linear-feedback shift register.

Abstract: A method according to one embodiment includes writing monitor data to at least one block of a memory device having finite endurance and/or retention; reading the monitor data after a period of time; determining a retention behavior of the at least one block based on the reading; and outputting a result of the determining. A memory device according to one embodiment includes a plurality of memory blocks having finite endurance and/or retention, at least one of the blocks having monitor data written therein; and circuitry for addressing the blocks. A system according to one embodiment includes a memory device having finite endurance and/or retention, the memory device comprising: a plurality of memory blocks, at least one of the blocks having monitor data written therein, wherein the at least one block has been written to a plurality of times prior to writing the monitor data; and circuitry for addressing the blocks.

Abstract: A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.

Abstract: Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.

Abstract: An invention is provided for providing a double data rate memory physical interface having self checking loopback logic is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

Abstract: A semiconductor integrated circuit has a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory, a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal, and a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.

Abstract: A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.

Abstract: A test apparatus includes a fail memory (AFM) for storing therein fail information in association with each of the addresses of a memory under test and a mark memory (CMM) for storing therein, in association with each of the addresses of the memory under test, validity information indicating whether the fail information stored in the AFM is valid. When the validity information read from the CMM in association with an address under test indicates that the fail information that has been stored in the AFM is invalid, the test apparatus overwrites the fail information stored in the AFM with the fail information that is newly generated by a current test. On the other hand, when the validity information read from the CMM indicates that the fail information is valid, the test apparatus updates the fail information stored in the AFM with the new fail information and writes the updated fail information back into the AFM.

Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.

Abstract: A method and apparatus for testing a three dimensional (3D) memory including a static array and an active array. The method is performed by a memory built-in self-test (MBIST) controller, and includes writing data to the static array, transferring data from the static array to the active array, and reading data from the active array. The method further includes, in a plurality of subsequent cycles, writing data to the static array; transferring data from static array to the active array, and reading data from the active array, wherein said writing data for each subsequent cycle is performed concurrently with reading data for a previous cycle.

Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Abstract: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output terminal. The flip-flop unit has a second input terminal coupled to the first output terminal, a clock signal input terminal for receiving a reference clock signal, and a second output terminal outputting an output data. The first buffer is coupled to the flip-flop unit to convert the output data to a high voltage data, and outputs the high voltage data. The second buffer is coupled to the first buffer to convert high voltage data to low voltage data and transmit the low voltage data to the feedback input terminal.

Abstract: A semiconductor memory device includes a determination circuit that generates a determination signal by determining an error of read data read out from a memory cell array, and an I/O circuit that outputs the read data or the determination signal to outside via a data input/output terminal. The I/O circuit outputs the read data to outside at a first timing in a normal: operation mode, and in a test mode, outputs the determination signal to outside at a second timing later than the first timing. A difference between the first timing and the second timing is an integer times of a cycle of a clock signal. In this way, the determination signal can be correctly output in the test mode, because an output timing of the determination signal is controlled to be delayed from an output timing of the read data within the device.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract: The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A method for performing a double pass nth fail bitmap of a memory array of a device under test includes a memory built-in test (MBIST) unit reading previously written data from each location of the memory array during a first pass, and detecting a failure associated with a mismatch between written and read data at each location. The method also includes storing within a storage, an address corresponding to a current failing location in response to determining that a predetermined number of locations have failed. The method further includes the MBIST unit reading the previously written data from each location during a second pass. The method includes locking and providing for output, read data stored at a current read address in response to a match between the current read address and any address stored within the storage.

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.

Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

Abstract: A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled to the data input-output terminals respectively. The memory core is coupled to the input-output buffers through input-output lines. The buffer selecting unit generates a parallel buffer select signal based on an expected signal having a pulse stream, wherein the expected signal is provided via the input terminal to select a buffer in a test mode, and applies the parallel buffer select signal to the plurality of input-output buffers to select a corresponding input-output buffer. Hence, the semiconductor memory device may increase efficiency of a pin in a test device.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

Abstract: A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to be added to the common pattern; and an each pattern adding section that reads the additional pattern for each of the device under tests based on a result signal outputted from the device under test and provides the additional pattern added with the common pattern to the device under test.

Abstract: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

Abstract: A method for testing a burner includes the steps of: providing a rewriter (RW) disk (4) in good burning condition, and inserting the RW disk into a test burner (3) connected to a computer (1); selecting a burner type for the burner; designating a source file to be burned, and setting a counter J=0, a loop time N and a maximum time of fail test M; erasing all data on the RW disk; burning the source file onto the RW disk; determining whether the source file is successfully burned to the RW disk; executing J=J+1 if the source file is successfully burned to the RW disk; repeating the erasing step, the burning step and the determining step, and counting a time of successfully burned process by the counter J, until J=N?M+1 which denotes that the burner is in good burning condition. A related method for testing a RW disk is also provided.

Abstract: A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data, a first fail memory storing a grouping of the read address and the fail data in a case where the read data and the expected value are not the same, a second fail memory storing fail data concerning addresses corresponding to each address of the memory under test, and an updating section updating fail data stored in the second fail memory and corresponding to the read address based on the grouping of the address and the fail data read from the first fail memory.

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

Abstract: One embodiment of the invention relates to a circuit board for testing upsets caused by charged particles delivered under testing conditions. The circuit board comprises a device under test including an internal memory, a memory control unit to generate test patterns for comparison with data read from stored areas within the internal memory of the device under test, and a memory that is configured to only store error data. Other embodiments are described and claimed.

Abstract: An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer for measuring an elapsed time after data is entered into a memory device, a read controller for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.

Abstract: Provided is a backup line allocation apparatus that determines which fail lines, in a memory provided with a plurality of backup lines, to allocate the backup up lines to, comprising a bit counting section that, for each fail bit contained in each fail line, counts a number of orthogonal fail bits, which is a number of fail bits in a fail line that includes the each fail bit and has an orientation that differs from the orientation of the each fail line, and stores the number of orthogonal fail bits associated with the each fail bit; a weight calculating section that calculates a weighting coefficient for each fail line based on the number of orthogonal fail bits of the fail bits contained in the each fail line, and stores the weighting of the each fail line; and an allocating section that determines which of the fail lines to allocate the backup lines to, based on the relative sizes of the weighting coefficients calculated by the weight calculating section.