Abstract: A system for calibrating timing for write operations between a memory controller and a memory device. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

Abstract: Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.

Abstract: Disclosed is a failure detection apparatus for a solid state driver tester, the failure detection apparatus including: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.

Abstract: Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

Abstract: A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

Abstract: A method includes: writing testing data to a testing target area of the memory; reading the written data; writing the readout data to a result storage area of the memory with a first data layout; and acquiring a first comparison result by reading the data written to the result storage area and comparing the readout data with check data; rewriting the data read from the testing target area of the memory to the result storage area of the memory while changing a writing destination with a second data layout different from the first data layout within the result storage area of the memory by the testing circuit; and acquiring a second comparison result by reading the rewritten data and comparing the readout data with the check data; and specifying a defective position of the memory in accordance with the first comparison result and the second comparison result.

Abstract: An error correction circuit 1 in accordance with an aspect of the invention includes an associative memory 20, a logic circuit 10 disposed in parallel with the associative memory 20, and selection unit 30 that receives an output signal from the associative memory 20 and an output signal from the logic circuit 10 as an input. The associative memory 20 includes a table that handles an input signal as a word and holds an output signal related to the word and an error correction code used to correct the output signal as data. The associative memory 20 further includes error correction unit that outputs a signal in which an error was corrected based on data related to a word corresponding to an input signal. The selection unit 30 selects and outputs one of an output signal from the associative memory 20 and an output signal from the logic circuit 10.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A memory testing support method includes executing a procedure using a plurality of test patterns on a memory to be tested; recording an observation result of a current value flowing in the memory during the execution of the procedure using each of the test patterns into a storing section; and determining superiority or inferiority of the test patterns in terms of effectiveness of testing the memory based on the observation results of the test patterns recorded in the storing section.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.

Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.

Abstract: A data processing device according to the present invention includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

Abstract: A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.

Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.

Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Abstract: A method according to one embodiment includes writing monitor data to at least one block of a memory device having finite endurance and/or retention; reading the monitor data after a period of time; determining a retention behavior of the at least one block based on the reading; and outputting a result of the determining. A memory device according to one embodiment includes a plurality of memory blocks having finite endurance and/or retention, at least one of the blocks having monitor data written therein; and circuitry for addressing the blocks. A system according to one embodiment includes a memory device having finite endurance and/or retention, the memory device comprising: a plurality of memory blocks, at least one of the blocks having monitor data written therein, wherein the at least one block has been written to a plurality of times prior to writing the monitor data; and circuitry for addressing the blocks.

Abstract: A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.

Abstract: A method of operating a disk drive comprises scanning each Logical Block Address (LBA) of the disk drive to detect a read error or reading the LBA from a media defect list. The LBA may then be converted to a corresponding physical location on the media and a scan of the corresponding physical location and of nearby physical locations that are within a proximity threshold of the corresponding physical locations may be performed to find media defects. Based thereon, it may then be determined whether a media scratch is present and at least one or more data sectors associated with the media scratch may be relocated to a spare location on the media if the media scratch is determined to be present. If the media scratch is determined not to be present, only the data sector associated with the corresponding physical location may be relocated to the spare location.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: A method and system for randomizing memory in a functional verification test of a user design is disclosed. A random number is generated during the functional verification test. The data stored in the memory of the user design is stored. Encryption keys unique for each memory address of the memory are generated. Each encryption key for each memory address is a function of the random number and the memory address. Data in each memory address of the memory is encrypted with the encryption keys unique for each memory address. After exiting a low-power or power-off state, data in each memory address is read and decrypted using the same encryption keys. Data before and after the low-power or power-off state are compared to test memory loss.

Abstract: An arithmetic processing apparatus includes a cache memory to store data in cache lines, an error detecting unit to detect an error occurring in one of the cache lines, a way comparing unit to compare way identification information of a cache line to be accessed with error-way identification information, a word comparing unit to compare a word address of the cache line to be accessed with an error word address, a column comparing unit to compare a column address of the cache line to be accessed with an error column address, and a control unit to disable all cache lines sharing a failed word line in response to results of comparisons made by the way comparing unit, the word comparing unit, and the column comparing unit when the error detecting unit detects a second error occurring in any one of the cache lines after the occurrence of the first error.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

Abstract: A method of testing a semiconductor memory device includes reading previously written test data from the semiconductor memory device simultaneously through at least two data I/O connections, e.g., pins or pads, of the semiconductor memory device. The signals from the two data I/O connections are combined to produce a compound output signal. The compound output signal is received by a single I/O channel of a tester. The tester compares the compound output signal to a predetermined voltage level, and determines whether the semiconductor memory device is operating properly based on the comparison of the compound output signal to the predetermined voltage level.

Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.

Abstract: A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.

Abstract: One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.

Abstract: A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.

Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.

Abstract: The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.

Abstract: A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.

Abstract: A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.

Abstract: A system for testing a plurality of memories includes a plurality of memory testing devices and a controller. Each of the memory testing devices is coupled to one of the memories. The controller is configured to generate a test vector and send the test vector to the memory testing devices. Each of the memory testing devices tests its coupled memory respectively according to the test vector and sends a test result to the controller.

Abstract: The present invention provides a digital data acquisition module, such as a digital oscilloscope, that includes a synchronous random access memory (RAM), a digital signal processing unit, and a master control unit. The digital signal processing unit is coupled to the synchronous RAM and includes at least one analog-to-digital (A/D) converter that digitizes an analog signal, and a digital signal processor that includes a dual-port RAM, a plurality of processing blocks and a communications interface. The plurality of processing blocks process the digitized analog signal data, store the processed signal data in the synchronous RAM, create display data from the stored signal data, store the display data in the dual-port RAM.

Abstract: A device and method for verifying the integrity of a memory in a remote device are provided. An exemplary memory integrity verification method compares, based on a verification parameter received from a verifier, the time for retrieving data block of a memory of a remote device with a maximum threshold time allowed to read the memory, and transmits to the verifier a remote verification code and a data status according to the result of comparison so that the verifier can verify the integrity of the memory. Instead of relying on the verifier, the remote device provides data status information for integrity verification by using the memory retrieval time. As a result, accurate integrity verification is provided, and no independent hardware is required to verify integrity.

Abstract: A method for operating a memory (36) includes storing data in a plurality of analog memory cells (40) that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry (48) that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller (28), which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.

Abstract: An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.

Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by cither successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.