Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code that, when compiled into machine test code, interfaces with the test engine. The machine test code is executed with the processor to test the memory cache to detect one or more faulty memory blocks in the memory cache. If any of the faulty memory blocks are detected, the test engine is instructed, through the machine test code, to set one or more bits in registers to functionally replace the faulty memory blocks with redundant blocks of the memory cache.

Abstract: According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.

Abstract: The invention provides read/write methods for a CD-MRW (Mount Rainier ReWrite). The read/write methods split a read-block or write-packet range in to several sub-ranges to simplify the complexity of the related read/write procedures and reduce the required capacity of DRAM buffer for the read/write procedures of the CD-MRW. The sub-ranges are continuous, partial, or defect ranges of packets or blocks.

Abstract: A system and method for handling errors is provided. Errors related to the processing and storage of inverse discrete cosine transform (IDCT) image data cause hardware to become stalled. Stalled hardware may result in multiple image frames being dropped or lost during video playback. To avoid the stalling of hardware, the hardware is used to analyze the data being processed. Data being stored may be analyzed to determine if any error-characteristics, such as overflow or underflow, are present in the storing of the data. The data is manipulated to avoid stalling due to the error-characteristics.

Abstract: Error detection using data block mapping is provided. One method includes receiving a write request to write a user data block having a first block size, generating an error detection code for the user data block, appending the error detection code to the user data block to form an extended data block, and mapping the extended data block to a plurality of actual data blocks, each actual data block having a block size equal to the first block size.

Abstract: A semiconductor device manufacturing process which includes a test process that minimizes the test time for a single wafer, reduces the test cost and improves the throughput. The test system is made up of a wafer which includes plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. Where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.

Abstract: A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is equal to or higher than 110% to create a code block 3 comprised of c bytes. The code information block in the code block is encoded such that an error correcting code is included therein to have an encoding gain of 6 dB or higher for a bit error ratio of 10?12. Associated check bits are placed in the empty area to eventually generate a super FEC signal.

Abstract: The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N?x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.

Abstract: An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.

Abstract: A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.

Abstract: An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with an applied address is passing or failing. The integrated circuit further includes a shared built-in self-test (BIST) and repair system coupled to all of the plurality of inputs and all of the plurality of outputs. The shared BIST and repair system applies addresses and data to the plurality of inputs to test the plurality of memory arrays for failing storage locations.

Abstract: A functional testing and evaluation technique is provided employing an abstraction matrix that describes a complex software component to be tested. The abstraction matrix includes at least one test case scenario and mapped expected results therefore. Test cases are derived from the at least one test case scenario and used to test the software component, thereby generating test results. The test results are automatically evaluated using the abstraction matrix. The evaluating includes comparing a test case to the at least one test case scenario of the abstraction matrix and if a match is found, comparing the test result for that test case with the mapped expected result therefore in the abstraction matrix.

Abstract: An existing trace array on a chip is used to store the locations of bit failures from the automatic self-testing of an SRAM array. If a system is having problems, a technician can trigger the automatic test and then scan the trace array, thereby locating a large number of errors on the SRAM array very quickly.

Abstract: An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.

Abstract: A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality of memory modules includes a plurality of the plurality of memory devices. The check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules. The check/correct circuit is coupled to receive the encoded data block from the memory, and is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block.

Abstract: A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A memory apparatus is configured by obtaining test information for each of group of memory locations within the memory apparatus, compressing the test information to produced compressed test information and, based on the compressed test information, replacing a group of redundant memory circuits respectively associated with the group of memory locations.

Abstract: Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.

Abstract: The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Abstract: A list of waveforms is received (the list being one that is to be driven to or received from a pin of a device under test, and each waveform in the list being associated with a weight). For each of at least two waveforms in the list, a number of test sample points lost by masking the waveform with a particular parent waveform in a child-parent waveform map is calculated. The number of lost test sample points is determined by 1) a difference in the number of test sample points in the waveform and the number of test sample points in the particular parent waveform, and 2) the weight associated with the waveform. In response to the calculations, a waveform masking is implemented such that the implemented waveform masking results in fewer lost test sample points than another waveform masking.

Abstract: A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Abstract: A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.

Abstract: A identification system comprising at least one non-volatile memory device containing identification data, a communication bus for the memory device that is independent of any other system bus, and a controller to manage the integrity of the identification data.

Abstract: A method, computer readable medium, apparatus and RAID controller for performing nondestructive write testing is disclosed. For data storage devices divided into sectors, the present invention performs nondestructive write testing by writing data to the sectors, reading data written to the sectors, and comparing the data written to the data read to detect errors. To increase efficiency, sectors previously written by a host or other computer are tracked, allowing sectors not previously written to be tested without saving and restoring data in the sectors. To locate the sectors written to by the host computer, write indicators such as a sector written indicator, a sector stripe written indicator, and a stripe written indicator are maintained. Upon detecting a defective sector, a new sector is allocated, and the defective sector is replaced by the allocated sector.

Abstract: This invention provides a method for creating/writing defect management information of an information recording medium and an apparatus and optical disc based on the method. In the present invention, it depends on the type of data to be reproduced whether or not defective sectors which are detected during reproduction operation are replaced with non-defective sectors. If read-out errors are detected in reproducing non-audio/video data, linear replacement algorithm is applied to the corresponding defective sectors. On the other hand, in case of audio/video data, location information of the corresponding defective sectors is just kept without any sector replacement. Therefore, this invention enables to reproduce audio/video data in real-time regardless of the presence of defective sectors and to avoid writing data to the defective sectors when new data is overwritten to the information recording medium.

Abstract: A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.

Abstract: A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing.

Abstract: A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the memory device following a request from the test apparatus. Then, the bit error tables are transmitted sequentially to the test apparatus for further processing.

Abstract: A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided on a chip to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Subsequently, the chip's register may be cleared and testing may continue.

Abstract: A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Abstract: Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as the reaction gas, the fluorocarbon gas containing CF4 and CHF3 supplied at flow rates in a ratio of 3:7 to 0:1 or contains CF4 and CH2F2 supplied at flow rates in a ratio of 2.5:1 to 0:1, thereby suppressing the formation of copper fluoride.

Abstract: A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.

Abstract: Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

Abstract: An adaptive error recovery routine allows for the recovery from errors in read data of a disk drive. In one embodiment, a disk drive is provided which has an error memory having error memory elements used to record an error type and recovery step for each error recovered from the disk drive. If another error is detected that is of the same type and which is in a location close to a recorded error, the error recovery step used for the previous error is performed for the new error. If the previous error recovery step is not successful, the disk drive performs error recovery using an existing error recovery table, and omits the previous error recovery step.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded. Also, in the defect management method, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.

Abstract: A memory device testing apparatus transfers at high speed a fail signal from a failure analysis memory unit 100 to a memory failure remedy analysis unit 200. The failure analysis memory unit 100 has a data storage memory 110 and a compact memory 120. The data storage memory 110 is divided into at least two sub address spaces. The divided sub address spaces are assigned to the addresses in the compact memory 120. An address generation control unit reads data stored in the compact memory 120. An address generation unit 132 generates a memory address signal 143 based on a sub address signal 141 and a detail address signal 142. The detail address signal 142 is incremented by the address generation control unit 125. The data in the sub address space storing the fail signal is transferred to the memory failure remedy analysis unit 200. If the data read from the compact memory 120 does not contain failure information, the data stored in the corresponding sub address space is not transferred.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN<TF, a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.

Abstract: This invention is directed to a chip-level architecture used in combination with a monolithic three-dimensional write-once memory array.

Abstract: A service processor for a server system includes an event log that, once full, stores recent events by overwriting events of intermediate age so that the information required to diagnose both cascade errors and hangs are preserved. This contrasts with bottom-up buffers that discard recent events when full and with circular buffers that discard the oldest events when full. The event log can be reset by moving an exception region, that is, a region that is not overwritten by recent events. Alternatively, a partial reset can initialize an exception region (e.g., a bottom-up sublog), while a circular region or sublog continues to operate without being reset.

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract: A failure analysis method is provided that allows high-precision failure mode classification. Based on the result of a predetermined test using an LSI tester (2), an original FBM (27a) is generated. The FBM (27a) is compressed with 8×8 bits per pixel to generate an FBM (27b). Based on the FBM (27b), an area where a failure bit exists in the FBM (27a) is determined. Then, by compressing a portion of the FBM (27a) which corresponds to the above area with 2×2 bits per pixel, FBMs (27c, 27d) are generated. Based on the FBMs (27c, 27d), failure bits are determined.

Abstract: A redundant data for substituting a sector in the second memory region for a damaged sector in the first memory region is stored in the 1088 sector of the flash memory (1), and a program-instruction for rewriting, the redundant data into the table RAM (7) and for writing a program instruction in a specific sector into a program RAM (3) is stored in the 0 sector of the flash memory (1). Because with this arrangement a separate redundant circuit is unnecessary, costs can be reduced.

Abstract: A memory device redundant repair analysis method, recording medium and apparatus allowing a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules. It is possible to provide a memory device redundant repair analysis method, recording medium and apparatus that allow a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules by carrying out processing of finally merging a plurality of repair codes corresponding to respective rules obtained by applying a plurality of redundant repair analysis rules into one code.

Abstract: A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.

Abstract: A logger system, comprising a core component configured to receive a log statement from an application program, the log statement including a group identifier and a level identifier, the core component further configured to direct a log report generated from the log statement to an output stream based on the group identifier and the level identifier of the log statement and log controls accessible to the core component.

Abstract: In a first aspect, a method of operating a disk drive includes detecting a trigger event during non-idle operation of the disk drive, and responding to the detected trigger event by performing a predictive failure analysis with respect to the disk drive. According to a second aspect, a method of operating a disk drive includes performing a predictive failure analysis with respect to the disk drive at a regular time interval, detecting a trigger event during non-idle operation of the disk drive, and responding to the detected trigger event by reducing the regular time interval at which the predictive failure analysis is performed. Numerous other aspects are provided.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.