Abstract: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.

Abstract: A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc; issuing reading commands to a recording/reproducing apparatus to be tested on which the test disc is loaded and verifying the disc in order to verify the reading operation; and issuing recording commands to the recording/reproducing apparatus to be tested on which the test disc is loaded and checking whether a temporary disc management area (TDMA) structure is properly updated on the disc in order to verify the modification operation.

Abstract: A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.

Abstract: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

Abstract: Suggested corrections for a code error are provided by a compiler or code editor, for example. Thus, there is much less ambiguity about how an error should be corrected. Preferably, a predetermined number of suggested corrections are presented to the user (e.g., up to three suggestions), and the user can choose a desired suggested correction. Corrections for a given error can be made, not only at the location of the error, but throughout the code document, or other files in the user's solution. Furthermore, by undoing one correction and trying another, the user can go through all of the suggested corrections to determine which suggestion would be most preferable.

Abstract: Embodiments of the invention improve the security of data written on a magnetic disk by performing re-allocation processing starting from a sector whose defect is large in automatic re-allocation processing. According to one embodiment of the present invention, after the reliability of each of data sectors that have been read out from a magnetic disk according to a read command is determined, re-allocation processing on the data sectors is performed in the order of increasing reliability. As a result, within a limited period of time, it is possible to replace by priority a data sector where there is a high possibility that data recovery will be unable to be achieved. This makes it possible to increase the security of data and the reliability of the HDD. The reliability of each data sector is determined on the basis of the number of bytes corrected by ECC.

Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.

Abstract: In an information handling system, when a memory location is accessed and there is a bit error detected in that memory location then the memory location is logged into an error-log. The memory locations of the logged bit errors stored in the error-log are evaluated to determine whether there is one or more bit errors in a particular memory range, e.g., a contiguous range of memory locations. If there is one or more bit errors in a memory range, then that memory range may be hot ejected, e.g., disabled from use by the operating system. The bit error may be single bit error and/or multiple bit errors of a memory location.

Abstract: A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as failure information in a failure information storage register. The circuit includes a storage determining circuit determining whether or not to store the failure information in a failure information storage register based on preset failure information storage method information.

Abstract: A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

Abstract: A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data is produced indicative of the results of the comparison. The fail data is compressed using a lossless compression scheme so that a record of the fail data can be transferred to a host in real time. The compressed fail data may be a literal record that specifies the value of consecutively repeating fail data as well as the number of times the fail data repeats. The fail data may also be a record specifying the literal records in a repeating sequence of literal records as well as the number of times the sequence repeats.

Abstract: Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.

Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive. The semiconductor memory drive includes a control module configured to control execution of data read and write on a nonvolatile semiconductor memory in units of a predetermined number of sectors. In a case where a data size of write data from the information processing apparatus main body is less than a data size of the predetermined number of sectors, the control module reads, from the nonvolatile semiconductor memory, data in a predetermined number of sectors including a sector in which the write data is to be written, and in a case where an error is detected in the read data, the control module stores, in a management table, defective sector information which is indicative of a sector storing the data in which the error is detected.

Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.

Abstract: A fault diagnosis method for a semiconductor device in which a memory and a register are monolithically integrated is provided. The fault diagnosis method is composed of: first testing the memory with respect to a series of addresses to identify a first error address; externally outputting the first error address; storing the first error address into the register; second testing the memory with respect to a series of addresses; identifying a second error address different from the first error address using a result of the second testing and the first error address stored in the register; externally outputting the second error address; and updating the register to store the second error address.

Abstract: A hard disk drive (HDD) according to an embodiment of the present invention uses three primary defect map (PDM) formats: a single-sector entry format; a multi-sector entry format; and a two-dimensional sector entry format. Methods of registering defective sectors in each such format are illustrated. Defects can be appropriately registered in a limited RAM capacity by selecting an appropriate format according to states of the defects on a magnetic disk.

Abstract: Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.

Abstract: An on-chip failure analysis circuit for analyzing a memory comprises a memory in which data is stored, a built-in self test unit which tests the memory, an failure detection unit which detects an failure of output of the memory, an fail data storage unit in which fail data is stored, the fail data including a location of the failure, an failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit.

Abstract: A method and system for performing diagnostic testing to speed the computer boot process. A boot process is initiated and an error counter value is read in any of memory, input/output, central processing, networking, mass storage, or other computing subsystems. The error counter values are compared to subsystem error thresholds. The method includes identifying subsets of subsystems with error counters exceeding error thresholds and then, performing diagnostic tests only on this subset of subsystems as part of the boot process. The error counter may be a correctable error counter that is incremented by an operating system error handler as it isolates subsystem errors. The method includes identifying subsystems in service less than a predefined time threshold by comparing a value stored in a power-on hours field in each subsystem to time thresholds, and including these modules in the tested subset.

Abstract: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired.

Abstract: The present invention relates to a method and a corresponding device for managing defective storage units on a record carrier, in particular on a rewritable optical record carrier. To avoid synchronization errors of a drive when accessing storage units located before or after a defective storage unit, it is proposed according to the present invention not only to map the actual defective storage unit (U1) but also one or more storage units (U2-U5) located before and/or after the defective storage unit (U1) as defective.

Abstract: Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.

Abstract: A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank.

Abstract: A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory cells, identifying faulty memory cells in the tested portion of the memory; writing an error map in another portion of the memory, the error map indicating the location of faulty memory cells found in the tested portion and, after executing the test routine and writing the error map, repairing at least some of the faulty memory cells using the error map. Once one portion of memory is tested, another portion is tested and a prior tested portion is used to write a new error map. Repairing, by analyzing the error map, is done at a slower speed than required for memory testing, allowing the use of a smaller logic section in the integrated circuit.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A system for processing tester information including receiving data from a tester and forming a user defined field for storing descriptive information. A bitmap is created and compressed into a compressed image. The user defined field and the compressed image are then combined into a data structure.

Abstract: A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under test; an OR comparator for outputting fail data when an output signal outputted by the memory under test is not matched with the expected value signal; a first FBM for storing the fail data in a first test; a second FBM for accumulating the fail data stored in the first FBM and fail data in a second test and storing therein the same; and a safe analysis section for performing a fail safe analysis on the memory under test with reference to the fail data stored in the first FBM. The first FBM accumulates the fail data stored in the second FBM and the fail data in the third test. The safe analysis section performs a fail safe analysis on the memory under test further with reference to the fail data stored in the second FBM.

Abstract: A method for use in a computer system provides a dynamic, “self tuning” soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or other circuits are “tuned” in a manner that gives them extreme susceptibility to cosmic neutron events (soft errors), higher than that of the “regular” SRAM components, memory modules or other components in the computer system. One such specially designed SRAM is deployed per server. An interface algorithm continuously sends read/write traffic to the special SRAM to infer the soft error rate (SER), which is directly proportional to cosmic neutron flux. The inferred cosmic neutron flux rate is employed in a Poisson SPRT algorithmic approach that dynamically compensates the soft error discrimination sensitivity in accordance with the instantaneous neutron flux for all of the regular SRAM components in the server.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber, calculating dynamic estimation errors for the precursor and/or purging process, and determining if the dynamic estimation errors can be associated with pre-existing BIST rules for the process. When the dynamic estimation error cannot be associated with a pre-existing BIST rule, the method includes either modifying the BIST table by creating a new BIST rule for the process, or stopping the process when a new BIST rule cannot be created.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber; determining a measured dynamic process response for a rate of change for a process parameter; executing a real-time dynamic model to generate a predicted dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the expected process response; and comparing the dynamic estimation error to operational limits.

Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.

Abstract: Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining a second part of the test data by testing the device at second points of the range of parameters using adaptive sampling.

Abstract: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade of the device is derived from the value. Preferred longevity parameters include a ratio of successfully-processed data to unsuccessfully-processed data and a deviation in a power consumption of the device. The grade serves as a forecast of a life expectancy of the memory. Preferred grades include: a comparison grade, a maximum grade, and an average grade.

Abstract: A method and the apparatus of defect areas management includes the steps as following: reading a defect area table in a random access memory; if the area is readable, then read the area. If the area is not accessible, then label and add one count in the defect area table of inability to read of the defect area, and else if the count of inability to read of the defect area is more than a predetermined value, then the defect area is defined as the area of being not to be read again. Then the defect area of being not to be read again is skipped and not to be read the next time in order to decrease the total access time.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.

Abstract: An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.

Abstract: A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit.

Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.

Abstract: An example memory error ranking system is provided. The system may include an error detector logic that detects memory errors and a ranking logic that ranks the quality of a memory location based on memory errors detected by the error detector logic.

Abstract: Categories are established for use in physiological monitoring devices and these categories are prioritized such that data indicative of a critical event self-triggers a communication to an external receiver for the purpose of re-transmitting the critical data for use by a clinician. The categories can be established by the clinician and, if desired, the precise monitored data parameters can be assigned to specific categories. Far-field transmission can be used to send certain stored data to an external receiver, provision is made for externally charging the device batteries.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A method for recycling a flash memory includes rearranging the capacity of cells, centralizing bad sectors at a cell, labeling the cell as a useless cell, examining the bad sectors in each cell of the flash memory to determine whether or not the number of bad sectors in each cell exceeds an allowable upper limit. If the number of bad sectors exceeds the allowable upper limit, the cells of the flash memory will be rearranged, and the area with densely distributed bad sectors is marked as a new cell, and such cell is deleted. In the process of the recycling method, the number repeated uses of the flash memory exceeding the maximum number of bad sectors can be arranged to extend the life expectancy of the flash memory, so that the flash memory device originally incapable of writing and reading data can be used again.

Abstract: A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memory using the DMLED test module, and executing the test case at an operating clock rate of a processor. The method further includes writing result signatures into the memory, and dumping the results signatures from the memory to a tester using the DMLED test module.