Abstract: Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells and a control circuit. The control circuit is configured to receive data, sort the received data to obtain unchanged data and ECC encoded data, and store the unchanged data and the ECC encoded data in the array of memory cells.

Abstract: Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, 64-bit MMX registers, ADD and SUB instructions, the MOVNTDQ instruction, and relying on an initial setting of the gate A20 and protected mode result in a substantially accelerated memory test.

Abstract: A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.

Abstract: Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.

Abstract: Method and system for reducing memory faults for computer systems. In one aspect, a notification is received that indicates that a single bit error has been detected in a portion of memory of the computer system. A service program is used to isolate the portion of the memory that includes the detected single bit error by allocating the portion of memory to itself, such that the portion of memory may no longer be accessed for data reading or writing by programs running on the computer system.

Abstract: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.

Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

Abstract: A system and method for logging and storing failure analysis information on disk drive so that the information is readily and reliably available to vendor customer service and other interested parties is provided. The information, in an illustrative embodiment, is stored on a nonvolatile (flash) random access memory (RAM), found generally in most types of disk drives for storage of updateable disk drive firmware. A known location of limited size is defined in the flash RAM, to form a scratchpad. This scratchpad is a blank area of known addresses, formed during the original firmware download onto the memory, and which is itself free of firmware code. This scratchpad is sufficient in size to write a series of failure codes in a non-erasable list as failures/errors (and user/administrator attempts to unfail the disk) are logged.

Abstract: Memory modules based on DDR-DRAMs are provided with a buffer and error checking module, which integrates an error data memory and a buffer/redriver functionality for conditioning data signals that are transferred to the memory module and output from the memory module and is suitable for the correction of user data stored erroneously in the DDR-DRAMs. The buffer and error checking module enables the integration of both error correction and buffer/redriver functionality on memory modules within the restricted memory module dimensions in accordance with definitive industry standards, simplified or improved routing of data lines and of control and address lines and also, by virtue of a reduction of erroneously transferred data to the data memory system, an increased real data transfer rate.

Abstract: If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect. This indication is stored in the memory device. In one embodiment, the quality indication is stored in a predetermined location of the defective memory block. Using the quality indication, it can be determined if a system's error correction code scheme is capable of correcting data errors resulting from the defect.

Abstract: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

Abstract: A method, system and article of manufacture to provide debugging of a computer system from firmware. A debugger in a first computer system is initialized during the pre-boot phase of the first computer system, the debugger to operate from a firmware environment of the first computer system. A communication channel of the first computer system is initialized to enable a second computer system to be communicatively coupled to the first computer system. The debugger is entered in response to a debug event. The first computer system is examined with the debugger. In one embodiment, the firmware of the first computer system operates in accordance with an Extensible Firmware Interface (EFI) specification.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated.

Abstract: A network monitoring program automatically sorts fault producing locations on a network. A memory unit stores a fault location determining table containing events indicative of failures of communications via the network, the events being associated with classified elements which can be causes of faults on the network. A communication situation monitoring unit monitors communication situations with respect to other apparatus on the network. A failure detecting unit detects an event indicative of a failure from a communication situation detected by the communication situation monitoring unit. A fault location determining unit determines an element which is responsible for the event detected by the failure detecting unit by referring to the fault location determining table. A fault information output unit outputs fault information representative of a determined result from the fault location determining unit.

Abstract: The present invention relates to a method and a device for the fast verification of sector addresses in a data stream obtained from a recording medium upon a request from a microcontroller. According to the invention, the method comprises the steps of: reading the data stream from the recording medium; decoding the data stream to obtain a decoded data stream comprising user data and sector addresses; comparing the sector addresses with a range of valid sector addresses; and transmitting only user data having sector addresses within the range of valid sector addresses; whereby dedicated comparing means are provided for performing the comparing step independently of the microcontroller.

Abstract: A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.

Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.

Abstract: A method and apparatus is provided which reduces the equipment and time requirements for hard disk drive performance testing during manufacturing. This invention executes self-contained performance testing code that resides within the drive's manufacturing firmware, rather than relying on external testers. The invention involves exercising the drive's enqueue, dequeue, and command execution firmware, as well as the physical process of reading and writing data by simulating the host interface in code. The invention enqueues commands that typify the desired workload, allows a command ordering algorithm to sort the commands for execution, and allows the drive side code to execute the commands just as if an external host interface were attached. The invention is advantageous because the performance testing can be done by only applying power to the drive. The present invention also lends itself to performance tuning that can be done in manufacturing, to reduce drive-to-drive performance variations.

Abstract: This invention provides a method for creating/writing defect management information of an information recording medium and an apparatus and optical disc based on the method. In the present invention, it depends on the type of data to be reproduced whether or not defective sectors which are detected during reproduction operation are replaced with non-defective sectors. If read-out errors are detected in reproducing non-audio/video data, linear replacement algorithm is applied to the corresponding defective sectors. On the other hand, in case of audio/video data, location information of the corresponding defective sectors is just kept without any sector replacement. Therefore, this invention enables to reproduce audio/video data in real-time regardless of the presence of defective sectors and to avoid writing data to the defective sectors when new data is overwritten to the information recording medium.

Abstract: A method and apparatus is provided for maintaining data integrity. According to the method, a physical checksum calculation is performed on a block of data. After performing the physical checksum calculation, a logical check is performed on the data contained with the block of data. If the block of data passes the logical check, then the block of data may be written to nonvolatile memory. Thereafter, when the block of data is read from nonvolatile memory a physical checksum verification procedure is performed on the block of data to determine whether the block of data was corrupted after performing the logical check on the data contained with the block of data.

Abstract: There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing a memory device having a burst function which automatically generates addresses for banks therein. Each of registers corresponding to the banks of the memory device holds a line address of the corresponding bank. When a start address of one of the banks is input to the memory device, a line address of the same bank as the start address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start address. Furthermore, during burst operation of the bank, the registers output the line address to the failure analysis memory together the same line address as the memory device generated by calculating the start address for each clock cycle.

Abstract: A memory test circuit comprises a memory which outputs stored data through n-bit data output pins, and a built-in self test (BIST) unit. The BIST unit writes test data in the memory, and by comparing the test data output from the memory with expected data, determines a failure cell address in the memory. The BIST unit generates k preliminary failure signals having failure information indicating whether the test data correspond with the expected data, and outputs the k preliminary failure signals for m cycles of a clock signal, by outputting k/m preliminary failure signals each cycle as first through k/m failure signals. In the memory test circuit and test system, the BIST unit testing a memory and generating a failure signal is disposed in a memory apparatus and a failure analysis circuit analyzing a failure signal output by the BIST unit is disposed in the test apparatus.

Abstract: In general, various methods, apparatuses, and systems that generate an augmented repair signature to repair all of the defects detected in a first test of a memory as well as in a second test of the memory.

Abstract: An approach for performing data block location verification includes inserting an address value into a data block that identifies a desired location in nonvolatile memory for storing the data block. Prior to performing an operation that stores the data block to the nonvolatile memory, a determination is made whether the address value in the data block correctly identifies the location in nonvolatile memory into which the operation will store the data block. The operation is performed only if the address value in the data block correctly identifies the location in nonvolatile memory into which the operation will store the data block. After the data block is read from the nonvolatile memory, an additional determination may be made to determine whether the data block was read from the desired location in the nonvolatile memory.

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract: A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Abstract: This invention provides a method for creating/writing defect management information of an information recording medium and an apparatus and optical disc based on the method. In the present invention, it depends on the type of data to be reproduced whether or not defective sectors which are detected during reproduction operation are replaced with non-defective sectors. If read-out errors are detected in reproducing non-audio/video data, linear replacement algorithm is applied to the corresponding defective sectors. On the other hand, in case of audio/video data, location information of the corresponding defective sectors is just kept without any sector replacement. Therefore, this invention enables to reproduce audio/video data in real-time regardless of the presence of defective sectors and to avoid writing data to the defective sectors when new data is overwritten to the information recording medium.

Abstract: A method for testing an CMOS ternary content addressable memory (TCAM) device includes a match line test to identify stuck match lines, a pull down test to identify weak pull downs (from the match line to ground), and a row-by-row match test. During the row-by-row match test a failed cell can be repaired or the row associated with the failed cell can be disabled. A failed cell or its associated row can also be repaired or disabled, respectively, after the test. Additionally, individual CAM cells which are identified as being defective can be further tested to identify which component of the CAM cell failed.

Abstract: A method is provided for monitoring error log files for specified error events through the use of a software program. In accordance with the method, each time the program is run, the steps are performed of: (a) accessing (405) an error log file, (b) identifying (419) those portions of the error log file not previously read by the program, (c) reading (413, 417) essentially only those portions of the error log file not previously read by the program and identifying (423) any predefined error conditions recorded therein, (d) generating a report (425, 429) which notes the existence of any predefined error conditions identified, and (e) terminating (427) the program.

Abstract: A built-in self test circuit includes a capture register storing data transmitted from a memory device, an operation controller controlling operation of the memory device and the capture register, a hold controller executing a hold operation to stop a read operation and a write operation of the memory device by transmitting a hold signal to the operation controller, and a test control circuit controlling the operation controller to transmit a capture signal so that the capture register stores the data to the capture register.

Abstract: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.

Abstract: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

Abstract: While executing a command that accesses a sector on a disk-shaped recording medium placed in a data recording device, an address of a sector where it is difficult to read data is recorded in a memory. After that, a determination is made as to whether or not the data recording device is executing a command. If it is judged that the data recording device is not executing a command, the address of the sector is read from the memory, and then a bad sector is searched for by detecting whether or not it is difficult to read data from each of surrounding sectors adjacent to the sector, the address of which has been read.

Abstract: A recording medium includes a spare area and the management information of the spare area. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, allocating a supplementary spare area. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information are recorded to efficiently manage the spare areas. In performing defect management, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.

Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.

Abstract: Various methods, apparatuses, and systems that use a replacement policy algorithm to implement tracking of one or more memory locations that have incurred one or more data transfer failures.

Abstract: An embedded memory on an integrated circuit has a memory cell array equipped with replacement cells and mapping logic for electronically substituting the replacement cells for defective cells at at least one location in the memory cell array. The memory also has programmable links for storing redundancy information in a compressed format, and decoding logic for decompressing the redundancy information and controlling the mapping logic.

Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.

Abstract: A semiconductor integrated circuit includes a memory which has redundant lines for repair in both a column direction and a row direction. A test pattern generating section generates a specific test pattern for the memory. A comparing section reads an output from the memory to judge whether or not a fault cell exists in the memory and outputs a signal which shows existence or nonexistence of a faulty cell. The circuit includes a first data storage section, which operates in a first test mode for a test of the memory and a second test mode for a scan test, and a second data storage section which receives an output signal of the comparing section to store a state of presence or absence of a failure corresponding to the existence or nonexistence of the faulty cell. A repair judging section receives an input to the first data storage section and an output of retained contents in the first data storage section and judges that the memory is repairable.

Abstract: A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Abstract: A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections—one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.

Abstract: A device monitors a system's available resources and produces either a deferred notification or an instant notification based on a comparison with an established threshold. The threshold may be adjusted if current or anticipated system resource utilization changes. Changes to the threshold may result in deferred notifications being removed from a queue and an instant notification being transmitted to a reporting facility.

Abstract: A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.

Abstract: Real-time audio video applications require guaranteed request service times from a hard disc drive. This requirement is not always fulfilled due to some unexpected delays in service times. Re-allocated sectors are one of the causes of such delays. A scheme for conversion of re-maps into slips in a hard disc drive is suggested. Converting re-allocated sectors into slipped or skipped sectors can prevent such a delay, since slipped sectors cause much less or even negligible performance loss than re-allocated sectors.

Abstract: An apparatus and method for transmitting and receiving a PDCCH for efficient transmission of a PDCH in a communication system supporting a packet data service. PDCCHs according to the present invention enable TDM and TDM/CDM transmission of the PDCH, Especially, CRC generators and CRC checker of the present invention allow a second user to utilize control information on a first PDCCH.

Abstract: A failure analysis memory is disclosed for use with a semiconductor tester for storing bit image failure information relating to a memory-under-test. The semiconductor tester has a plurality of channel cards disposed proximate the memory-under-test. The failure analysis memory includes a memory controller and a plurality of memory units disposed in communication with the memory controller. The memory units are distributed on the channel cards.

Abstract: A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.