Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Abstract: In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.

Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.

Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

Abstract: Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: Embodiments provide a method, a device, and system to implement session management on a UPF network element. The method includes: determining, by a network device, that a first logical interface group on a first UPF network element needs to be migrated; determining, by the network device, a second UPF network element for the first logical interface group; sending, by the network device to the second UPF network element, configuration information of the first logical interface group and information about a first IP address segment corresponding to the first logical interface group, to restore the configuration information of the first logical interface group and the information about the first IP address segment on the second UPF network element; and sending, by the network device, a first message used to restore, on the second UPF network element, information about one or more sessions corresponding to the first logical interface group.

Abstract: The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

Abstract: An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.

Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit (DAC), a receive analog DAC and a drive sense circuit configured to receive transmit digital data. The transmit DAC is configured to convert transmit digital data into an analog outbound data signal and the receive analog DAC is configured to convert an analog outbound data signal into an analog transmit signal. The drive sense circuit is configured to drive the analog transmit signal on to a bus coupled to the low voltage drive circuit as a signal that varies loading on the bus at a first frequency to represent the analog outbound data signal. The drive sense circuit is further configured to receive an analog receive signal from the bus at a second frequency, convert the analog receive signal into an analog inbound data signal, convert the analog inbound data signal into received digital data, and output the received digital data.

Abstract: A mobile terminal testing device includes a layer processing unit 3 that communicates with a mobile terminal 10 by performing processing of each layer of a layer-configured communication protocol with a plurality of layers, in which the layer processing unit 3 includes a PHY processing unit 31 that performs multiplexing, channel coding, or the like in order to transmit and receive communication data transmitted to and received from the mobile terminal 10, in which the PHY processing unit 31 transmits a dummy signal, by omitting higher processing from predetermined processing, for an interference signal in multi user-multi input multi output (MU-MIMO) multiplex signals, in a case of testing MU-MIMO terminal-to-terminal interference.

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

Abstract: An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

Abstract: A method to assist in the operation of a financial market. The method including receiving one or more transaction messages, where the one or more transaction messages include one or more orders or order commitments to be executed on the financial market; imposing one or more delays on the one or more orders or order commitments using a delay algorithm; processing the one or more order or order commitments by opening the one or more transaction messages after the one or more delays; matching the opened orders or order commitments; and executing the matched orders or order commitments.

Abstract: Method and apparatus for using components of a vehicle. The apparatus includes a computing device and a memory for instructions and an interface for components of the vehicle. The computing device is designed to control the components of the vehicle when the instructions are executed by the computing device. A first component is required for an automated driving mode of the vehicle and a second component are designed in a redundant manner with respect to one another. At least one load of the second component for an automated driving mode is either switched on or at least partially switched off depending on a condition. The condition characterizes the need for redundant operation of the first component and of the second component.

Abstract: Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command.

Abstract: An accelerated seasoning cycle criterion is associated with a memory die of a number of memory dies. The memory die is subjected to one or more accelerated seasoning conditions during accelerated seasoning cycles. Responsive to determining that the accelerated seasoning cycle criterion has been satisfied, a defect scan is performed on the memory die. The memory die is associated with a respective reliability bin of a plurality of reliability bins in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability bin.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range.

Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: An electronic system includes a first circuit and a second circuit. The first circuit includes a first activation unit and a first functional unit. The first activation unit receives a first challenge string, generates a first response string according to the first challenge string and a first key, and outputs the first response string. The first functional unit performs first designated function. The second circuit includes a second activation unit and a second functional unit. The second activation unit sends the first challenge string to the first circuit during a first activation operation, and determines whether the first activation operation passes certification or not according to the first challenge string, the first response string and the first key. The second functional unit performs second designated function when the first activation operation is determined to have passed the certification.

Abstract: A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.

Abstract: A current leg located in a voltage domain where the current leg includes a transistor of a current mirror having a maximum voltage rating of less than the voltage of the voltage domain. The current leg includes a resistive element circuit to provide a first resistance during a normal mode of operation of the current leg and a different resistance during of a stress test of the transistor in a test mode of the circuit.

Abstract: An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, wherein each oscillation of the second plurality of oscillations has second unique oscillation characteristics; selecting one of the second plurality of oscillations in accordance with a second portion of the transmit digital data to produce a second selected oscillation, and outputting the first selected oscillation and the second selected oscillation on an n-bit-by-n-bit basis to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analo

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range.

Abstract: Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

Abstract: A method for triggering and detecting a malicious circuit on an integrated circuit device is provided. A first run of test patterns is provided to logic circuits on the integrated circuit device. Each test pattern of the first run of test patterns includes a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector. The value of the first test output vector is compared to first expected values. Bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns are changed to generate a second run of test patterns. The second run of test patterns is provided to the logic circuits on the integrated circuit device. A value of the second run of test patterns is compared to second expected values.

Abstract: A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert an analog outbound data into an analog transmit signal that is transmitted on a bus, receive an analog receive signal from the bus, and convert the analog receive signal into the analog inbound data. The LVDC further includes a transmit digital to analog circuit configured to convert transmit digital data into the analog outbound data. The LVDC a receive analog to digital circuit that includes an analog to digital converter operable to convert the analog inbound data into digital inbound data, a digital filtering circuit operable to filter the digital inbound data to produce a set of frequency domain digital data signals, and a data formatting module operable to convert the set of frequency domain digital data signals into received digital data.

Abstract: An integrated circuit includes intellectual property (IP) processing circuitries each including a separate, respective at least one scan chain, and temperature management controller circuitry configured to transmit an input pattern including a plurality of bits to at least one scan chain of a first IP processing circuitry among the IP processing circuitries, detect a temperature of the first IP processing circuitries based on an output pattern received from the at least one scan chain in response to the input pattern being transmitted to the at least one scan chain of the first IP processing circuitry, and control at least one of an operation frequency or an operation voltage of the first IP processing circuitry based on the detected temperature of the first IP processing circuitry.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data.

Abstract: A method for implementing a full sweep in a digital instrument cluster system without a graphical processing unit (GPU) is disclosed. The method includes displaying a static asset as background for displaying of dynamic assets that point to different position values on the static asset, sequentially retrieving each of a plurality of subsets of dynamic assets such that each subset provides position indicators with a different level of position granularity, wherein an order of retrieving each subset moves from a lowest granularity subset to a highest granularity subset until all of the plurality of subsets of dynamic assets have been retrieved, and performing a full sweep, prior to retrieving of the dynamic assets, by sequentially displaying the dynamic assets from a minimum position to a maximum position of the static asset, and back, the sequentially displaying being based on a highest available granularity of dynamic assets that have been retrieved.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, wherein each oscillation of the second plurality of oscillations has second unique oscillation characteristics; selecting one of the second plurality of oscillations in accordance with a second portion of the transmit digital data to produce a second selected oscillation, and outputting the first selected oscillation and the second selected oscillation on an n-bit-by-n-bit basis to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analo