Built-in Testing Circuit (bilbo) Patents (Class 714/733)
  • Patent number: 11942961
    Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 26, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Oreggia, Marco Cignoli
  • Patent number: 11928441
    Abstract: A semiconductor memory device is provided, comprising: a memory cell region including a memory cell array; and a peripheral circuit region which at least partially overlaps the memory cell region and includes control logic configured to control operation of the memory cell array, wherein the control logic includes a state machine configured to output a plurality of state signals responsive to operation commands of the memory cell region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output from a second output terminal different from the first output terminal, a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal, and an accumulation circuit configured to receive an output of the logical sum calculator as a clock signal, and that outputs a toggle signal to one probing pad in response to the clock signal, the accumulation circuit being conn
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bong-Kil Jung
  • Patent number: 11902373
    Abstract: A system includes a plurality of control system elements (CSEs) and a control system platform (CSP) including a data repository and operatively connected to the plurality of CSEs, and configured to: receive, from a CSE of the plurality of CSEs, a state logging message including measurement device state information (MDSI) and a control system element identifier (CSEI); store the MDSI in the data repository; process the MDSI to obtain analytic information; obtain, from the data repository, client device notification criteria (CDNC) associated with the CSEI; perform a comparison between the MDSI and the analytic information against the CDNC; determine, based on the comparison, that at least one notification trigger specified in the CDNC has been met; generate, in response to determining, an analysis notification message comprising the MDSI and the analytic information; and transmit the analysis notification message to a client device operatively connected to the CSP via a network.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 13, 2024
    Assignee: FMC Technologies, Inc.
    Inventors: James C. Breter, Robert M. Smith, Frederick G. Weiser
  • Patent number: 11894085
    Abstract: Implementations described herein relate to memory section selection for a memory built-in self-test. A memory device may read a first set of bits stored in a test control mode register. The memory device may identify a test mode, for performing a memory built-in self-test, based on the first set of bits. The memory device may read a second set of bits stored in a section identifier mode register. The memory device may identify one or more memory sections of the memory device, for which the memory built-in self-test is to be performed, based on the second set of bits. The one or more memory sections may be a subset of a plurality of memory sections into which the memory device is divided. The memory device may perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Schaefer
  • Patent number: 11880574
    Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: January 23, 2024
    Inventors: Rachael R. Carlson, Aparna U. Limaye, Diana C Majerus, Debra M. Bell, Shea M. Morrison
  • Patent number: 11867757
    Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 9, 2024
    Inventors: Heejune Lee, Jinwoo Park, Younghyo Park, Eunhye Oh, Sungno Lee, Youngjae Cho, Michael Choi
  • Patent number: 11853195
    Abstract: A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I0) of the ISA, and (ii) an interesting case space (Ii) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (Ii) by the input space (I0); determining a special case fraction (Ii)/(I0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Gregory A. Kemp, Bryant Cockcroft, Debapriya Chatterjee, Bradley Donald Bingham
  • Patent number: 11808811
    Abstract: An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Kalyana Kantipudi, Niraj Vasudevan
  • Patent number: 11796591
    Abstract: An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 24, 2023
    Assignee: Ambarella International LP
    Inventors: Praveen Jaini, Hsin-Wu Hsu, Hejia Yan
  • Patent number: 11768241
    Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: September 26, 2023
    Assignee: NVIDIA Corporation
    Inventors: Anitha Kalva, Jue Wu
  • Patent number: 11763037
    Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit includes a voltage sampling module, wherein the voltage sampling module includes: a first metal oxide semiconductor MOS transistor and a capacitor for sampling a power supply voltage, wherein a gate terminal of the first MOS transistor is connected to the capacitor, a source terminal of the first MOS transistor is connected to a ground voltage. The power glitch signal detection circuit further comprises a second MOS transistor and a signal output module. One terminal of the second MOS transistor is connected to a gate terminal of the first MOS transistor, another terminal of the second MOS transistor is connected to the power supply voltage, and a drain terminal of the second MOS transistor is connected to a drain terminal of the first MOS transistor.
    Type: Grant
    Filed: September 19, 2020
    Date of Patent: September 19, 2023
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Jianfeng Xue, Jiang Yang
  • Patent number: 11726139
    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: August 15, 2023
    Assignee: NVIDIA Corporation
    Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
  • Patent number: 11726895
    Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventors: Masashi Niimura, Kenshi Fukuda
  • Patent number: 11720442
    Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeokjun Choe, Heehyun Nam, Jeongho Lee, Younho Jeon
  • Patent number: 11693811
    Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: July 4, 2023
    Assignee: SigmaSense, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11686771
    Abstract: A chip, a chip testing method and an electronic device are provided. The chip includes a combinational logic and a data path gating; the data path gating includes a first input terminal and an output terminal, the first input terminal of the data path gating detects a test enable signal, and the output terminal of the data path gating is connected to the combinational logic; the test enable signal is used to switch a test mode of the chip; the data path gating is configured to output a data path gating control signal to the combinational logic, in a case where the detected test enable signal indicates that a current test mode is irrelevant to a data path function of the combinational logic; and the combinational logic is configured to disable the data path function after receiving the data path gating control signal, to disable data path toggling.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 27, 2023
    Assignee: CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
    Inventors: Yuqian Cedric Wong, Shuiyin Yao, Hongchang Liang, Zhimin Tang
  • Patent number: 11680981
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: June 20, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11675589
    Abstract: Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Werhane, Daniel S. Miller
  • Patent number: 11631473
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Patent number: 11631472
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 18, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Patent number: 11616764
    Abstract: In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 28, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Todd Rope, Whay Sing Lee, Arash Farhoodfar
  • Patent number: 11586498
    Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rahul Mitchell Jairaj, Mark A. Hawes, Terry M. Grunzke
  • Patent number: 11580047
    Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 14, 2023
    Assignee: SigmaSense, LLC
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11573269
    Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA Corporation
    Inventors: Anitha Kalva, Jue Wu
  • Patent number: 11549984
    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
  • Patent number: 11519962
    Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: December 6, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jeong-Fa Sheu, Chen-Kuo Hwang, Mei-Chuan Lu, Wei-Chung Cho
  • Patent number: 11500748
    Abstract: A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Nir Ofir, Wilson P. Snyder, II, Amit Shmilovich
  • Patent number: 11486928
    Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: November 1, 2022
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Ignazio Pisello, Yu Yong Wang, Dario Arena, Qi Yu Liu
  • Patent number: 11480613
    Abstract: Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 25, 2022
    Assignee: Arm Limited
    Inventors: Richard Andrew Paterson, Rainer Herberholz, Peter Andrew Rees Williams, Oded Golombek, Einat Luko, Jeffrey Scott Boyer
  • Patent number: 11437080
    Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 6, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Xiaoxiao Li, Lei Zhang
  • Patent number: 11408934
    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 9, 2022
    Assignee: Nvidia Corporation
    Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
  • Patent number: 11404134
    Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 2, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Sheng-Lin Lin, Shih-Chieh Lin
  • Patent number: 11399405
    Abstract: Embodiments provide a method, a device, and system to implement session management on a UPF network element. The method includes: determining, by a network device, that a first logical interface group on a first UPF network element needs to be migrated; determining, by the network device, a second UPF network element for the first logical interface group; sending, by the network device to the second UPF network element, configuration information of the first logical interface group and information about a first IP address segment corresponding to the first logical interface group, to restore the configuration information of the first logical interface group and the information about the first IP address segment on the second UPF network element; and sending, by the network device, a first message used to restore, on the second UPF network element, information about one or more sessions corresponding to the first logical interface group.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 26, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiang Hu, Yuan Xia
  • Patent number: 11373723
    Abstract: The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 28, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11366711
    Abstract: A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiwoong Kim, Moonki Jang
  • Patent number: 11366780
    Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 21, 2022
    Assignee: SigmaSense, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11342042
    Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Johnson, Yoshinori Fujiwara, Kevin G. Werhane
  • Patent number: 11336273
    Abstract: An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: May 17, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan Finkelshtein, Aviv Hasson, Yaniv Strassberg, Ran Sela
  • Patent number: 11327771
    Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 10, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
  • Patent number: 11327917
    Abstract: A low voltage drive circuit includes a transmit digital to analog circuit (DAC), a receive analog DAC and a drive sense circuit configured to receive transmit digital data. The transmit DAC is configured to convert transmit digital data into an analog outbound data signal and the receive analog DAC is configured to convert an analog outbound data signal into an analog transmit signal. The drive sense circuit is configured to drive the analog transmit signal on to a bus coupled to the low voltage drive circuit as a signal that varies loading on the bus at a first frequency to represent the analog outbound data signal. The drive sense circuit is further configured to receive an analog receive signal from the bus at a second frequency, convert the analog receive signal into an analog inbound data signal, convert the analog inbound data signal into received digital data, and output the received digital data.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 10, 2022
    Assignee: SigmaSense, LLC.
    Inventors: Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand, Richard Stuart Seger, Jr., Kevin Joseph Derichs, Timothy W. Markison
  • Patent number: 11316599
    Abstract: A mobile terminal testing device includes a layer processing unit 3 that communicates with a mobile terminal 10 by performing processing of each layer of a layer-configured communication protocol with a plurality of layers, in which the layer processing unit 3 includes a PHY processing unit 31 that performs multiplexing, channel coding, or the like in order to transmit and receive communication data transmitted to and received from the mobile terminal 10, in which the PHY processing unit 31 transmits a dummy signal, by omitting higher processing from predetermined processing, for an interference signal in multi user-multi input multi output (MU-MIMO) multiplex signals, in a case of testing MU-MIMO terminal-to-terminal interference.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: April 26, 2022
    Assignee: ANRITSU CORPORATION
    Inventors: Tomoyuki Fujiwara, Akihiko Suenaga, Toshiaki Aoki
  • Patent number: 11294749
    Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Ramamurthy Krithivas, Anand K. Enamandram, Eswaramoorthi Nallusamy, Russell J. Wunderlich, Krishnakanth V. Sistla
  • Patent number: 11275112
    Abstract: An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: March 15, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Bharat P. Londhe, Jay Shah, Aniruddha M. Bhasale
  • Patent number: 11263694
    Abstract: A method to assist in the operation of a financial market. The method including receiving one or more transaction messages, where the one or more transaction messages include one or more orders or order commitments to be executed on the financial market; imposing one or more delays on the one or more orders or order commitments using a delay algorithm; processing the one or more order or order commitments by opening the one or more transaction messages after the one or more delays; matching the opened orders or order commitments; and executing the matched orders or order commitments.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 1, 2022
    Assignee: TAMER TRADING TECHNOLOGIES LLC
    Inventor: Brian F. Mannix
  • Patent number: 11254328
    Abstract: Method and apparatus for using components of a vehicle. The apparatus includes a computing device and a memory for instructions and an interface for components of the vehicle. The computing device is designed to control the components of the vehicle when the instructions are executed by the computing device. A first component is required for an automated driving mode of the vehicle and a second component are designed in a redundant manner with respect to one another. At least one load of the second component for an automated driving mode is either switched on or at least partially switched off depending on a condition. The condition characterizes the need for redundant operation of the first component and of the second component.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 22, 2022
    Inventors: Ralf Eichele, Malte Baumann
  • Patent number: 11250891
    Abstract: Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Gil Golov
  • Patent number: 11238950
    Abstract: An accelerated seasoning cycle criterion is associated with a memory die of a number of memory dies. The memory die is subjected to one or more accelerated seasoning conditions during accelerated seasoning cycles. Responsive to determining that the accelerated seasoning cycle criterion has been satisfied, a defect scan is performed on the memory die. The memory die is associated with a respective reliability bin of a plurality of reliability bins in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability bin.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 1, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
  • Patent number: 11231735
    Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 25, 2022
    Assignee: SigmaSense, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11210172
    Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 28, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Andrew Butcher, Anh Luong
  • Patent number: 11170867
    Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 9, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Chieh Lin, Sheng-Lin Lin