Abstract: The present invention discloses a memory channel bridge with a BIST module; and the memory channel bridge interfaces other channels in a SOC to access a memory module. During a DFT test, SOC memory channels and the BIST access the memory module concurrently by using an arbiter in the memory channel bridge to arbitrate the traffics from the SOC memory channels and the BIST to ensure the correctness and completeness of the whole design.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract: A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.

Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes a memory module that includes one or more memory blocks. Each memory block includes a memory array having a first memory portion and a redundant memory portion, a failed memory indicator that, in response to a memory test, is configured to provide an indication of a failed memory portion in the first memory portion, and a wrapper circuit that, in response to the indication of the failed memory portion, is configured to repair the memory array by using the redundant portion instead of the failed memory portion.

Abstract: In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation performed on the plural memories.

Abstract: A system includes a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execution of the test, the storage into the memory of the status of the digital circuit and configured for controlling, after the execution of the test, restoring the status of the digital circuit based on the status stored in the memory.

Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

Abstract: A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

Abstract: An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.

Abstract: Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a middle point, a left point, and a right point. The start point is a beginning of an eye opening at a reference voltage. The end point is at an ending of eye opening at the reference voltage. The middle point is at a center point of eye opening at the reference voltage. The left point is a left sampling location characterized by a minimum setup time requirement, and the right point is a right sampling location characterized by a minimum hold time requirement. Determining the points is based on shifting a DQS position and a DQ position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A circuit having a component for signal recovery, such as an adaptive equalizer, may be tested in order to ensure that the component operates properly. Unfortunately, external test equipment may be expensive and prone to being damaged. According to an aspect of the disclosure, there is provided a circuit including BIST (Built-in Self-Test) circuitry for testing a component for signal recovery with a stress signal that simulates an imperfect signal received over a communication channel. The circuit also has a detector for determining whether the component is operating properly with the stress signal. Thus, no external test equipment is needed for testing the component. In some implementations, the BIST circuitry includes a low-pass filter for filtering a transmit signal into the stress signal. Thus, the amount of circuitry involved in generating the stress signal can be reduced.

Abstract: According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result.

Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

Abstract: A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.

Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

Abstract: A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.

Abstract: A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m<N) and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies is provided.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal. The integrated circuit includes a switching element configured to receive the first enable signal and the second enable signal to generate a third enable signal. The integrated circuit includes combinational logic coupled to the loading circuit and the switching element, in which the combinational logic is configured to receive the third enable signal. The third enable signal is configured to disable toggling in the combinational logic while the loading circuit operates in the shift mode.

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.