Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data.

Abstract: An electronic system includes a first circuit and a second circuit. The first circuit includes a first activation unit and a first functional unit. The first activation unit receives a first challenge string, generates a first response string according to the first challenge string and a first key, and outputs the first response string. The first functional unit performs first designated function. The second circuit includes a second activation unit and a second functional unit. The second activation unit sends the first challenge string to the first circuit during a first activation operation, and determines whether the first activation operation passes certification or not according to the first challenge string, the first response string and the first key. The second functional unit performs second designated function when the first activation operation is determined to have passed the certification.

Abstract: A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.

Abstract: A current leg located in a voltage domain where the current leg includes a transistor of a current mirror having a maximum voltage rating of less than the voltage of the voltage domain. The current leg includes a resistive element circuit to provide a first resistance during a normal mode of operation of the current leg and a different resistance during of a stress test of the transistor in a test mode of the circuit.

Abstract: An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, wherein each oscillation of the second plurality of oscillations has second unique oscillation characteristics; selecting one of the second plurality of oscillations in accordance with a second portion of the transmit digital data to produce a second selected oscillation, and outputting the first selected oscillation and the second selected oscillation on an n-bit-by-n-bit basis to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analo

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range.

Abstract: Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

Abstract: A method for triggering and detecting a malicious circuit on an integrated circuit device is provided. A first run of test patterns is provided to logic circuits on the integrated circuit device. Each test pattern of the first run of test patterns includes a plurality of bits, a first portion of the plurality of bits being bits that do not influence a value of a resulting first test output vector, and a second portion of the plurality of bits being bits that will influence the value of the first test output vector. The value of the first test output vector is compared to first expected values. Bit values of the first portion of the plurality of bits for each test pattern of the first run of test patterns are changed to generate a second run of test patterns. The second run of test patterns is provided to the logic circuits on the integrated circuit device. A value of the second run of test patterns is compared to second expected values.

Abstract: A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert an analog outbound data into an analog transmit signal that is transmitted on a bus, receive an analog receive signal from the bus, and convert the analog receive signal into the analog inbound data. The LVDC further includes a transmit digital to analog circuit configured to convert transmit digital data into the analog outbound data. The LVDC a receive analog to digital circuit that includes an analog to digital converter operable to convert the analog inbound data into digital inbound data, a digital filtering circuit operable to filter the digital inbound data to produce a set of frequency domain digital data signals, and a data formatting module operable to convert the set of frequency domain digital data signals into received digital data.

Abstract: An integrated circuit includes intellectual property (IP) processing circuitries each including a separate, respective at least one scan chain, and temperature management controller circuitry configured to transmit an input pattern including a plurality of bits to at least one scan chain of a first IP processing circuitry among the IP processing circuitries, detect a temperature of the first IP processing circuitries based on an output pattern received from the at least one scan chain in response to the input pattern being transmitted to the at least one scan chain of the first IP processing circuitry, and control at least one of an operation frequency or an operation voltage of the first IP processing circuitry based on the detected temperature of the first IP processing circuitry.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data.

Abstract: A method for implementing a full sweep in a digital instrument cluster system without a graphical processing unit (GPU) is disclosed. The method includes displaying a static asset as background for displaying of dynamic assets that point to different position values on the static asset, sequentially retrieving each of a plurality of subsets of dynamic assets such that each subset provides position indicators with a different level of position granularity, wherein an order of retrieving each subset moves from a lowest granularity subset to a highest granularity subset until all of the plurality of subsets of dynamic assets have been retrieved, and performing a full sweep, prior to retrieving of the dynamic assets, by sequentially displaying the dynamic assets from a minimum position to a maximum position of the static asset, and back, the sequentially displaying being based on a highest available granularity of dynamic assets that have been retrieved.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; a first plurality of oscillations, wherein each oscillation of the first plurality of oscillations has first unique oscillation characteristics; selecting one of the first plurality of oscillations in accordance with a first portion of the transmit digital data to produce a first selected oscillation; generating a second plurality of oscillations, wherein each oscillation of the second plurality of oscillations has second unique oscillation characteristics; selecting one of the second plurality of oscillations in accordance with a second portion of the transmit digital data to produce a second selected oscillation, and outputting the first selected oscillation and the second selected oscillation on an n-bit-by-n-bit basis to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analo

Abstract: Embedded processor-based self-test and diagnosis using the compressed test data is described for ICs having on-chip memory. Techniques for compressing the test data before the compressed test data is transferred to a device under test (DUT) are also described. A modified LZ77 algorithm can be used to compress strings of test data in which don't care bits are handled by assigning a value to the don't care bits according to a longest match in the window as the data is being encoded. The compressed test data can be decompressed at the DUT using a software program transferred by the automated test equipment (ATE) to the DUT with the compressed test data. Decompression and diagnostics can be carried out at the DUT using an embedded processor and the on-chip memory. Results from the diagnostics can be read by the ATE.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus in a first frequency range and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus in a second frequency range.

Abstract: A signature encoded light system includes at least one light source. The at least one light source is configured to output a first encoded light signature embedded within light in the visible spectrum. A light signature detection device is configured to receive a composite light signal formed with light from the at least one light source and ambient light. The light signature detection device is configured to identify the first encoded light signature.

Abstract: A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data.

Abstract: An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

Abstract: A circuit for detecting a glitch in power supply includes a detection circuit to detect the glitch in a DC supply voltage of the power supply when a magnitude in the glitch in a DC supply voltage of the power supply exceeds a detection threshold, wherein the detection threshold is a function of the DC supply voltage, and wherein the detection circuit comprises a low pass filter, a control circuit coupled to the low pass filter, and a current mirror circuit coupled to the control circuit having an output for providing a logic signal indicative of a detected glitch.

Abstract: An electronic component module includes: a substrate including a conductive pattern; an electronic component provided to the substrate; a sealing portion covering the electronic component and substrate, and having an upper surface and a side surface that form an edge portion; a contact portion configured to be electrically connected with the conductive pattern, the contact portion exposed on a vertical surface continuous with the side surface of the sealing portion; a removal portion formed by removing the predetermined edge portion formed by the upper surface and the side surface of the sealing portion; and a shielding film covering the upper surface, the side surface and the contact portion of the sealing portion. The removal portion is a region allowing a conductive material to pass therethrough so that the contact portion is covered with the shielding film, the conductive material being scattered in vacuum atmosphere lower than atmospheric pressure.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: A low voltage drive circuit includes a transmit analog to digital circuit that converts transmit digital data into analog outbound data by: generating a DC component; and generating an oscillating component at a first frequency that conveys the transmit digital data, wherein the magnitudes of both the oscillating component and the DC component are limited to a range that is less than a difference between the magnitudes of the power supply rails of the circuit, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Abstract: A low voltage drive circuit includes a transmit analog to digital circuit that converts transmit digital data into analog outbound data. A receive analog to digital circuit converts analog inbound data into received digital data. A drive sense circuit is configured to: convert the analog outbound data into an analog transmit signal; drive the analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency; receive an analog receive signal from the bus; and isolate the analog receive signal from the analog transmit signal to recover the analog inbound data, wherein the analog inbound data is represented within the analog receive signal as variances in loading of the bus at a second frequency.

Abstract: A method for testing a detection sensor positioned facing a target fixed to a drive shaft that is intended to be installed in a motor vehicle. The method includes generating a pulsed voltage test signal, amplifying the high states of the generated test signal, filtering the amplified test signal so as to obtain a voltage test signal having high states the voltage of which is higher than a predetermined high-state detection threshold and low states the voltage of which is lower than a predetermined low-state detection threshold, and detecting the high states and the low states of the filtered test signal in order to test the sensor.

Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

Abstract: The present disclosure relates to a signal processing device, a signal processing method, and a program that enable detection of a failure without stopping signal processing. A toggle rate is calculated for each of signals of a preceding stage and a subsequent stage of a signal processing unit and, in a case where a difference therebetween is larger than a predetermined threshold value, it is assumed that an error caused by a failure is occurring in the signal processing unit. The present disclosure can be applied to a drive assistance device of a vehicle.

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

Abstract: The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24). Said interception means (18) are responsive to said generation means (16) in order to simultaneously feed the generated scan-in data into each of said scan chains (12) for initializing the electronic circuit (10). The invention further relates to a method for initializing an electronic circuit (10), as well as a data processing system (210) for initializing an electronic circuit (10).

Abstract: A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: A problem with a computing system is detected, a root cause is identified and a solution is also identified. Diagnostic data is obtained and an issue signature is generated that maps the issue to failed components and product functionality.

Abstract: An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Abstract: A computer implemented method, apparatus, and computer usable program code for embedding and importing content prediction instructions. Content prediction instructions are customized. The content prediction instruction is part of content prediction logic. The prediction instruction is embedded in a document in response to receiving a user selection to embed the prediction instruction.

Abstract: A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.

Abstract: A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

Abstract: Systems, methods, and non-transitory computer readable media configured to generate session information based on information regarding items of a plurality of item types associated with interactions performed by active users of a social networking system. A graph is generated based on the session information. At least a first item of the items is assigned to a cluster based on similarity between the item and the cluster. The cluster is provided to a recommender system to facilitate selection of relevant information for potential presentation to a user.

Abstract: The PRPG provides the test stimulus to the circuit, but it can only generate a finite number of care-bits from any given input seed which limits the maximum coverage that can be achieved. The only way to increase the coverage is to provide additional seed input data to the PRPG. The on-chip one time only programmable eFuse is used to store new PRPG seed data inputs and corresponding MISR output signature data for comparison. An XOR circuit option on the output of the MISR is operable to further compress the output data.

Abstract: Generating a routing between pins of a semiconductor device may include selecting one or more of candidate pins of the semiconductor device, generating a net list associated with the selected pins generating an interface script to execute the net list in a library-based disposition and wiring tool that is driven in a computer system, and executing the interface script through the library-based disposition. Pins may be selected from the candidate pins based on at least one of density, shapes, intervals, and sizes among the candidate pins. The net list may define a set of electrical connections between the selected pins.

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.