Abstract: The improved pin system enables a single, shared pin of a semiconductor device to have multiple functions that include: receiving data that determines the operating mode of the semiconductor device and also receiving data unrelated to the operating mode of the semiconductor device. The improved pin system comprises the single, shared pin coupled to a data latch. The data latch is configured to store operating mode data from the single, shared pin. This operating mode data preferably corresponds to a particular operating mode such as a functional mode or a test mode. Preferably, in response to the operating mode data stored in the data latch, the semiconductor device operates in either the functional mode or the test mode. As long as the data latch stores the operating mode data, this shared, single pin is capable of receiving data unrelated to the operating mode of the semiconductor device without changing the current operating mode of the semiconductor device.

Abstract: Accompanied by turning on power, power ON reset pulse from a power ON reset generation circuit is input to CPU and a fail determining circuit. After receiving the power ON reset pulse, the fail determining circuit intentionally outputs a fail detection signal. The CPU intentionally stops output of PRUN signal after confirming that fail detection signal. WDT confirms that output of the PRUN signal from the CPU is stopped in a predetermined time interval T and outputs PRUN abnormality signal. A reset pulse generation circuit confirms that PRUN abnormality signal is supplied from the WDT and outputs a reset pulse. A fail determining circuit receives a reset pulse and stops output of fail detection signal. When the fail determining circuit stops output of the fail detection signal, the CPU determines that the WDT, the reset pulse generation circuit and the fail determining circuit are in normal state.

Abstract: Methods and apparatus for interactive built-in self-testing with user-programmable test patterns are disclosed. The present invention operates in the context of an integrated circuit (IC) including built-in self-test (BIST) logic and a test interface circuit resident on the IC. The BIST logic executes a BIST routine for testing the IC, and the test interface achieves the inputting of an external test pattern into the BIST logic from an external logic circuit. The test interface includes a first flag storage element accessible to the BIST logic. The first flag storage element stores a first flag that indicates whether the test pattern will be provided to the IC from the external logic. A test data storage element in the test interface stores the external test pattern, and is also accessible to the BIST logic. A second flag storage element accessible to the BIST logic stores a second flag to indicate whether the test pattern is available in the test data storage element.

Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA

Abstract: A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.

Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.

Abstract: A method and apparatus are provided for automatically generating the design of a BIST for embedded memories of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates software that generates equations that can be used as inputs to a logic synthesis tool. The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

Abstract: In a mixed signal integrated circuit containing both an analog core circuit and a digital core circuit, a plurality of dedicated analog boundary scan cells disposed around the analog core circuit are connected in series by a dedicated analog boundary scan path. A plurality of dedicated digital boundary scan cells disposed around a digital core circuit are connected in series by a dedicated digital boundary scan path. The analog and digital boundary scan paths are independent of each other. In testing the analog or digital core circuit, the boundary scan path dedicated thereto is selected so that sets of test control data or test data are shifted only in the boundary scan cells dedicated thereto. As a consequence, a test pattern is shortened and the analog or digital core circuit can efficiently be tested in a shorter period of time.

Abstract: Methods and structure for storing context data regarding electronic test equipment and the device under test or stimulus sources in a manner integrated with the capture and storage of test data as well as test setup data associated with a test environment. The context data may include information regarding parameters of the test environment (e.g., test equipment or test bench set points and configurations, configuration information regarding the device under test, etc.). The context data may be provided in the form of standard textual data as well as user voice sequences to be recorded. The context data is associated with any stored test data or test setup data so as to be easily retrieved along with the retrieval of the associated data. The data are associated by any of several methods including file naming conventions, structured files, table lookups, etc.

Abstract: A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.

Abstract: Disclosed is an output interface for an integrated circuit permitting input and output pads to selectively receive binary data elements or electrical signals from multiple sources. The output interface contains a storage mechanism that stores the N binary information elements present on N internal lines of the integrated circuit and a multiplexer that presents the binary information in packets of K bits to a connection mechanism. Upon direction from a control mechanism, an insulation mechanism disconnects the pads from internal circuits on the chip, the connection mechanism connects the pads with the multiplexer, and the multiplexer sequentially makes the binary information available in packets of K bits to the K pads.

Abstract: ASIC (Application-Specific Integrated Circuit) testability, troubleshooting access and visibility of internal circuitry are the primary targets of test engineering analysis. The widely applied boundary-scan technique is a useful interface but does not solve all problems connected with the PBA (Printed Board Assembly) manufacturing process. The invention provides an extension of the boundary-scan technique currently implemented to provide improved ASIC testability. The Collateral ASIC Test (method and logic) implemented in a boundary-scan device according to the invention makes possible a test process standardization to ASIC design and testing.