Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: An interface testing circuit and method for testing an interface between two or more separate hardware components provides interface testing capability without requiring complex and expensive synchronized mixed signal testing between the hardware components. The interface testing circuit includes two or more sub-circuits, each of which is adapted to selectively route either a test signal from a test input/output pad to a hardware component or route an output signal from another hardware component to the test pad. Multiple testing modes are used to fully test the interface.

Abstract: A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Abstract: A semiconductor device is provided having an internal circuit to be tested, a redundancy circuit used when detecting a defective part in the internal circuit, and a switching unit connected to the internal circuit and the redundancy circuit. The switching unit switches wiring in order to ensure proper operation of the semiconductor. A test unit is connected to the internal circuit for testing for the internal circuit. An operation environment change unit is connected to the internal circuit, wherein for changing an environment of the internal circuit when during testing. According to the present invention, testing of semiconductor devices can be performed under an actual environment so that a defective part can be detected under the actual operation environment. Moreover, it is possible to widen the range of guaranteed operation of semiconductor devices when a plurality of tests are performed under a plurality of operation environments.

Abstract: A system (5) for testing and failure analysis of an integrated circuit (10) is provided using failure analysis tools (40, 50, 60). An analysis module (30) having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools (40, 50, 60) to be used. The rest of the integrated circuit contains function modules (20) arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module (30) using the failure analysis tools (40, 50, 60), physical parameters of the integrated circuit (10) are obtained and used in subsequent testing of the function modules (20) by the failure analysis tools (40, 50, 60), thus simplifying the testing of the integrated circuit (10) and reducing the time taken to perform a failure analysis procedure.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: There are provided a test apparatus and method for testing a semiconductor integrated circuit which enables improvements in the ease of operation and convenience of a BOST device and shortening of a test time. Numeric codes are assigned to tests. A test apparatus is equipped with memory and an analysis section. A test requirement table—in which hardware requirements required for conducting a test are set on a per-numeric-code basis—is stored in the memory. Test requirements corresponding to a numeric code are read from the memory, whereupon a test is performed. The analysis section analyzes a digital test output and sends the result of analysis to an external controller.

Abstract: A chip testing apparatus and method including a testing section, provided in a corresponding chip, for judging a normal/abnormal state of the corresponding chip by obtaining a test signature by accumulating a bit stream inputted in a system level using a predetermined testing method and by comparing the obtained test signature with a reference signature previously obtained and stored to verify the fault of the chip itself in the system level conveniently and rapidly. According to the chip testing apparatus and method, the fault that may be overlooked during the chip fabrication process can be discriminated, and thus a stable chip can be provided in implementing the whole system. Also, since it is prevented that the fault of the chip itself is wrongly detected as an error of the system construction, the shortening of the system development period and the improvement of the system performance can be achieved.

Abstract: A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit.

Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

Abstract: Methods are provided for virtually embedding and/or de-embedding balanced four-port networks into/from a device under test (DUT). For the methods, a set of scattering-parameters is acquired for the DUT. Additionally, a respective set of scatter-parameters is acquired for each of the balanced four-port networks to be embedded and/or de-embedded. A transfer-matrix is generating for the DUT based on its scattering parameters. Further, a respective transfer-matrix is generated for each of the networks to be embedded/de-embedded based on its respective set of scattering-parameters. The transfer-matrix for the DUT is then multiplied with the one or more transfer-matrices associated with the balanced four-port networks to be embedded and/or by an inverse of the transfer-matrices associated with the balanced four-port networks to be de-embedded. A composite transfer-matrix is thereby produced. Finally, a set of composite scattering-parameters is then generated based on the composite transfer-matrix.

Abstract: A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

Abstract: An apparatus for obtaining valid values during a built-in self-testing of logic (“LBIST”) is disclosed. The apparatus includes a first multiplexer, a second multiplexer and a 1-hot init circuit. The 1-hot init circuit includes a scan register, a first inverter, a third multiplexer, a second inverter, and a fourth multiplexer. The scan register includes a plurality of state elements. The first multiplexer is coupled to receive a random data signal and an output of the 1-hot init circuit. Within the 1-hot init circuit, a next to last and a last state element of the scan register is coupled to the inverters and the third and fourth multiplexers, respectively. The first inverter is also coupled to the third multiplexer and the second inverter is coupled to the fourth multiplexer. The output of the fourth multiplexer is coupled to the input of the second multiplexer. Also coupled to the input of the second multiplexer is an input for the random data signal.

Abstract: A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.

Abstract: A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

Abstract: A built-in-self-test (BIST) circuit for RAMBUS DRAM is disclosed. Unlike other conventional memory devices, a RAMBUS DRAM operates at a much higher speed (e.g., 400 MHz) with a complicated protocol imposed on its input stimuli. In order to provide at-speed testing, a new BIST architecture is needed. The new architecture consists of three major components—two interacting finite state machines (FSMs) and a high-speed time-division multiplexer. The two finite state machines, defining the underlying test algorithms jointly, are used to generate a sequence of generic memory commands. Through the time-division multiplexer, each memory command is then further mapped into a multi-cycle packet compliant to the specification of a target RAMBUS DRAM. Among these components, the finite state machines often form the performance bottleneck. A simple master-slave synchronization mechanism is used to convert these two finite state machines into a multi-cycle path component, thereby eliminating the timing criticality.

Abstract: A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules for easily establishing different semiconductor test systems. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is high speed high timing accuracy while other type of performance is low speed low timing accuracy. Each event tester module includes a tester board which is configured as an event based tester.

Abstract: There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I.C. chip area was realized in comparison to the implementation by a conventional state machine.

Abstract: Given the inventive electrical circuit with a device for testing connections in electrical circuits, the change of a test signal (27) due to the effect of a long line is used for determining the quality of an electrical connection (e.g., of a pin). In particular, a determination about the terminating impedance and, thus, about the quality of the connection, is made by defining a maximum value of the test signal (28) reflected at the line end. An existing boundary scan test implementation with appropriate expansions can thereby be used, including a test controller. Standard digital signals can be employed as test signal when their propagation time is lengthened by a delay element.

Abstract: A self testing-and-repairing data buffer and method for operating the same are disclosed. The data buffer comprises a plurality of flip flops, a multiplexer, a test platform, a repair unit, and a buffer rearrange manager. The test platform generates test signals for checking each flip flop. If any damage is found, the repair unit is used to replace the damage flip flops for storing data. The buffer rearrange manager rearranges the address of the damage flip flops to the repair unit so that the data buffer can be operated normally. By the circuit layout and the precise calculation about time delay, the gated clock signal not used currently is used to form the working frequency of the flip flops of the data buffer so as to reduce the power as the IC is inoperative. Furthermore, the area of the data buffer and number of gates are reduced greatly.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: An integrated circuit includes an embedded memory device and an on-chip test circuit. The on-chip test circuit includes a multiplexer and one or more I/O circuits. The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device. As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry. This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit.

Abstract: A semiconductor integrated circuit with a IP test circuit having a IP test circuit, a IP6, a IP7, a COU 4, a SRAM 5. The IP test circuit has a IP test controller 21 including a register 21, a test sequencer 2, a selector 3, and a bus interface 11. Under the control of the IP test controller 1, a test program and test data in serial form are transferred from an external tester through a test data terminal 9 and then converted to the test program and the test data in parallel form. The converted test program and the test data are stored into the SRAM 5. The CPU 4 executes the test operation for the IP6 directly connected to a cpu bus 8. The test sequencer 7 executes the test operation for the IP7 that is not directly connected to the cpu bus 8. The test results are transferred to the external tester through the test data terminal.

Abstract: A system, device, and method for dynamically testing integrated circuits is disclosed. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state.

Abstract: A method of self-testing the programmable routing network in a field programmable gate array (FPGA) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The initial self-testing area is preferably configured to include an horizontal self-testing area primarily for testing horizontal wire segments and a vertical self-testing area primarily for testing vertical wire segments. Programmable logic blocks located within the self-testing areas are configured to function as a test pattern generator and an output response analyzer, and a portion of the programmable routing resources within the self-testing areas is configured as groups of wires under test. An exhaustive set of test patterns generated by the test pattern generator is applied to the groups of wires under test which are repeatedly reconfigured in order to completely test the programmable routing resources within the self-testing areas.

Abstract: An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.

Abstract: A programmable array built-in self test system for testing an embedded array allows self test functions, e.g. test patterns, read/write access, and test sequences, to be modified without hardware changes to the test logic. Prior programmable ABIST systems have three types of control structure: scan only mode control bits; direct use of bits from the microcode instruction; and state machines that are controlled by microcode instructions which may then be used to provide feedback to the branch control functions that control the microcode instruction pointer. A fourth type of control structure is disclosed that can be used to reduce the number and/or size of the microcode instructions that are required to implement many array test algorithms. This fourth type of control structure is used to modify the values that are generated by the original three array control structure types. This mechanism is implemented as a the test mode register. Two other improvements are made to control the looping mechanism.

Abstract: The memory device of a semiconductor chip is tested with a BIST circuit. The configuration and the method store the test results obtained by the BIST circuit. The test results are stored in the sense amplifiers of the memory device. In addition, it also possible for test programs for the BIST circuit to be stored in the sense amplifiers.

Abstract: A Built-In Self-Test (BIST) circuit is employed to automatically test integrated analog to digital converters (ADC). Proposed technique applies delta-sigma (&Dgr;&Sgr;) modulator concept to ADC testing and results in a fully automated accurate test procedure suitable for differential non-linearity (DNL) and integral non-linearity (INL) testing. Additional analog circuitry does not have a significant effect on the test accuracy and the test resolution is determined by the sampling frequency of the delta-sigma modulator.

Abstract: A method of self-testing the programmable logic blocks of field programmable gate arrays (FPGAs) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The self-testing area may be further subdivided into self-testing tiles for concurrent testing if desired. The programmable logic blocks located within the self-testing area or self-testing tiles are established to function as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test for testing. An exhaustive set of test patterns generated by the test pattern generator are applied to the programmable logic blocks under test which are repeatedly reconfigured in order to completely test the programmable logic blocks in all possible modes of operation.

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behavior. Special test circuits are implemented within the test logic configurations to enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur.

Abstract: The present invention is a system and method that facilitates flexible restriction of output transmissions from chosen scan test cells and reduces adverse impacts on functional components from coincidental test vector values during scan test operations. The system and method of the present invention provides the capability of masking test vector values that coincidentally trigger certain undesirable events in functional components. In one embodiment, a system and method of the present invention masks test vector values shifted into scan test cells that are coupled to bus driver enabling signals. The system and method of the of the present invention also facilitates flexible selection of which scan test cell outputs are masked and permits a scan test cell to provide a scan test vector value to an associated functional component and prevent coincidental transmission of inappropriate test vector values.

Abstract: A method and apparatus for testing a contents-addressable-memory type structure using a simultaneous write-thru mode in an array is provided. The circuit to be tested has combinational logic and an array, and the array has bit cells and a logic cells. Each logic cell is uniquely associated with a bit cell such that an output of a bit cell provides an input to a logic cell, and each set of logic cells for an address of the array provides an output data vector from the array. Each cone of logic in the combinational logic receives an output data vector from an associated address in the array as an input data vector, and each cone of logic in the combinational logic is independent from other cones of logic in the combinational logic. A test vector is input to a write port of the array, and a set of logic cell input values are also input into the array.

Abstract: An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.

Abstract: First, in the step of analyzing integrated circuit information, integrated circuit information is retrieved and the structure of the circuit is analyzed, thereby creating routing information for each functional block. Next, in the step of analyzing pin allocation information, pin allocation information, including input and output pin connection information for the functional block, is retrieved and the contents thereof are analyzed, thereby creating machine-readable pin combination information. The input pin connection information represents which input pin of the functional block should be connected to each external test data input pin. The output pin connection information represents which output pin of the functional block should be connected to each external test data output pin.

Abstract: A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: In a semiconductor integrated circuit, a monitor circuit for evaluation is provided on a semiconductor substrate in an input/output buffer circuit region. This monitor circuit includes a delay circuit, a first flip-flop circuit on the input side of the delay circuit, and a second flip-flop circuit on the output side of the delay circuit.

Abstract: Provided is a semiconductor integrated circuit device, an electronic instrument and a method of testing a semiconductor integrated circuit device which simplifies a test circuit and can decrease test loads such as the preparation of a test vector and test time when a plurality of single chips are integrated on one chip. The semiconductor integrated device comprises a first semiconductor integrated circuit, a second semiconductor integrated circuit, and an I/O circuit connected to an external terminal. The I/O circuit receives an internal signal, which is output from the first semiconductor integrated circuit to the second semiconductor integrated circuit, and outputs the internal signal to outside through the external terminal and to the second semiconductor integrated circuit as the input thereof. The I/O circuit comprises a first buffer which controls the output of the internal signal.

Abstract: A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.

Abstract: A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Abstract: A semiconductor device with embedded memory cells is provided, wherein the device comprises a memory block, a logic block for inputting and outputting data with the memory block and performing specific functions, and an embedded test circuit block for testing the memory block with the signals input from outside the device. The device comprises a plurality of signal terminal groups for sending and receiving signals to and from outside the device to perform a normal operation, a direct access test and a built-in self test.

Abstract: A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states.

Abstract: A method, electronic component and test configuration for testing connections of at least one electronic component on a printed circuit board, in particular solder points for connection of pins to the printed circuit board, wherein a test pulse is produced within the electronic component for at least one pin on an electronic component, a signal reflected from the pin is set such that it correlates with the test pulse, and at least one correlation value, obtained from this, is compared with a previously defined set value and is assessed.