Abstract: A debugging device is provided for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to facilitate a debugging procedure on the system controller chip whenever a malfunction occurs to the system controller chip. Consequently, internal signals of the chip are correctly connected to chip leads. Under normal operating conditions of the system controller chip, the debugging device connects the connecting-pad area to the control unit and disconnects the connecting-pad the control unit and connects the connecting-pad area successively in a predetermined sequence to the function blocks, allowing the function blocks to undergo an on-site debugging procedure one by one. The debugging device allows an on-site debugging procedure on the system controller chip in real time, and also allows the system controller chip to undergo a benchmark test to check for the reliability in the overall functionality of the system controller chip.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a bum-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: A memory control circuit is disclosed for use in a data path of a failure capture circuit to selectively control the storage of failure information associated with a pin of a device-under-test. The memory control circuit includes a memory controller operative to generate a store signal in response to a failure control signal and a semiconductor memory having a control input coupled to the controller for receiving the store signal. The memory controller operates in response to the store signal to write failure information associated with a particular failure control signal. Disable logic in the memory control circuit is operative according to predetermined conditions for selectively inhibiting the delivery of the failure control signals to the memory controller.

Abstract: The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test.

Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made.

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test.

Abstract: A semiconductor test system for testing a semiconductor device by applying a test pattern to a device under test. The semiconductor test system is capable of generating test patterns based on predetermined algorithmic sequences and/or inverting data pattern in the test pattern based on predetermined algorithmic sequences. The semiconductor test system is capable of utilizing the same pattern program for different test items, thereby enabling to decrease the required capacity in an instruction memory. Especially, generation of inversion control signal can be made by using the same pattern program without increasing the capacity of the instruction memory.

Abstract: Integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuitry. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port when in snoopy states. At least one of the embedded core circuits includes a test access port controller for similar controlled connection to further embedded core circuits.

Abstract: Analog test instrument architecture for performing functional testing of electronic circuit assemblies is disclosed. The analog test instrument includes a plurality of identical channels, each channel including circuitry for driving test stimuli and measuring responses at one node of a circuit assembly under test. The driver and measurement circuitry in each channel implement functions that traditionally have been implemented in a test system using discrete instruments. The analog test instrument further includes a master clock reference, which is used for synchronizing the operation of the driver and measurement circuits. Each channel further includes triggering circuitry for distributing trigger events within the channel and to the other channels; and, an input buffer, which is shared by the measurement circuits in the channel. The synchronized operation, distributed trigger events, and shared input buffers are used to improve the correlation of measurements made during functional testing.

Abstract: A method of automatically generating a mixed-signal test program. The method according to one embodiment of the present invention is implemented in software in the form of two software processes. The first software process of the present embodiment includes a test-block extraction process which allows a user to extract re-usable test data from pre-existing test programs. The extracted re-usable test data is then stored in a template library in the form of a template. In one embodiment, the user only needs to provide the names of the interested cells and the corresponding pin designations to extract relevant test data from pre-exisiting test programs. The second software process of the present embodiment includes a test-block retargeting process which allows a user to use test data stored in the template library in a new mixed-signal test program. The names of the analog cells used in a new mixed-signal integrated design are provided to the test-block retargeting process.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An integrated circuit includes a monitor port, several circuit modules, and a selection circuit that selects which of the circuit modules drives internal signal through the monitor port. A debugging process can observe the internal signals at the monitor port to identify problems in the integrated circuit. In one embodiment, the selection circuit includes a trace bus that runs serially from the monitor port to each circuit module. Each module has tri-state buffers that connect the module to the trace bus. Alternatively, the selection circuit includes a multiplexer with input ports coupled to the modules. A trace select register controls which module drives the monitor port, and control registers or the current operation of each module select which set of internal signals the module applies to the tri-state buffers. Any of large number of internal signals can be selected and observed by programming the trace select register and the configuration registers for the modules.

Abstract: A system for efficient utilization of multiple test systems may include an apparatus for testing an electronic circuit board, which comprises a number of computer readable media containing computer readable program code comprising code for a test analysis system that interfaces with at least two test systems. The test analysis system reads a description of said board's board topology and analyzes a number of potential defects of said board based on that description. The test analysis system creates at least two test procedures for the at least two test systems by creating a first test procedure to test the electronic circuit board on a first test system of the at least two test systems. The system then creates at least one other test procedure to test the electronic circuit board on at least one other test system of the at least two test systems.

Abstract: A test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit (e.g., a digital television video circuit). The test data is functionally to verify the subject circuit. The functional verification of the subject circuit is performed utilizing an output of the subject circuit generated responsive to the test data in accordance with an operational functionality of the subject circuit. The test data generator is also coupled to provide the test data to a built-in self-test (BIST) circuit so as to enable the built-in self-test circuit to receive the test data.

Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

Abstract: A device for testing input-output (I/O) ports is disclosed, which comprises a plurality of switching devices and a decoder employed between the probe card and the device under test (DUT) card. Every switching device possesses an identical number of input ports and output ports to that of the testing I/O ports of the DUT card. The testing I/O ports of the DUT card are connected to the corresponding output ports of every switching device, respectively. The decoder is used to select a switching device, of which the output ports are connected to the DUT card for testing.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: Noise is introduced into test inputs and voltage supplies provided to logic devices while under going testing by modulating a test voltage output with a noise signal to produce the test input. In particular, a noise signal and a test voltage output are generated. The test voltage output is modulated with the noise signal to provide a test input to the logic device. A more accurate approximation of an actual operating environment is thereby provided.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: An integrated circuit includes an embedded memory device and an on-chip test circuit. The on-chip test circuit includes a multiplexer and one or more I/O circuits. The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device. As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry. This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit.

Abstract: In a module with a BIST function to which signal pulses are fed from outside with a tester, a configuration for generating signal impulses of defined lengths includes registers configured to store measured pulse lengths, and a variable delay element configured to measure pulse lengths of externally supplied signal pulses in a training phase. The element has a series circuit of inverters and delay-free signal paths parallel thereto for read/write from/into the registers. AND gates are disposed between a delay-free write signal path and the element and behind an even number of respective inverters, and the output of the AND gates are connected to the registers through the decoder. AND gates are disposed between the delay-free read signal path and the element and behind an even number of respective inverters. One input of the AND gates is connected to the registers through the decoder, another input is connected to the element, and the outputs are connected to the delay-free read signal path.

Abstract: A boundary scan cell for testing an integrated circuit comprises an output buffer for driving a pad of the integrated circuit, a capture register coupled to the pad through the output buffer, and an input buffer drives a signal present at the pad to a node coupled to core logic of the IC. A first multiplexer is included to have a first input coupled to the node, a second input coupled to data of a previous scan stage, and an output coupled to the capture register. Logic circuitry selectively enables/disables the input and output buffers responsive to first and second control signals such that the I/O buffers can drive the pad and, at the same time, drive the input buffer, the output of which is coupled to the input of the capture register.

Abstract: A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

Abstract: A method of fault tolerant reconfiguration and operation of a field programmable gate array (FPGA) during normal on-line operation includes selecting a programmable logic block as a programmable logic block under test, testing the programmable logic block under test, and detecting the existence of any faults in the programmable logic block under test. During testing, the programmable logic block under test is repeatedly reconfigured in order to test the programmable logic block completely in all possible modes of operation. Based on the results of the test, a test result indication is sent to a controller in communication with a memory for storing usage and fault status data for each programmable logic block. If a partially faulty test result indication is present, the controller determines an intended mode of operation of the partially faulty programmable logic block under test and reconfigures the logic block for further use, thus allowing a more gradual degradation of the field programmable gate array.

Abstract: A logic gate is provided that comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. The sensing circuit is adapted to sense a voltage on the internal node and to output a signal indicating a level of the voltage. The sensing circuit is not used during normal operation of the logic gate and preferably comprises only a single FET that is directly coupled to both the internal node and to the test output. The logic gate also preferably comprises a pre-charge circuit for pre-charging the test output to a predetermined voltage level prior to testing. An IC chip may be formed from a plurality of the logic gates wherein each logic gate comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. Each sensing circuit may be coupled to the same test output or to a unique test output for the sensing circuit's logic gate. The sensing circuits are not used during normal operation of the IC chip.

Abstract: A micro-controller integrated on a single substrate and which includes a read-only information memory for storing firmware, an address controller for performing address control, and an input port for inputting information supplied thereto from a source external to the substrate further incorporates a correcting information storage memory for receiving correcting information input thereto from the source external to the substrate through the input port and storing the correcting information upon an initialization of the micro-controller, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage memory, and a switching circuit for selectively switching the access by the address controller from the defective information part in the read-only information storage memory to the correcting information in the correcting information storage memory.

Abstract: Described is a system with a plurality of subsystems, wherein at least one of the plurality of subsystems comprises one or more monitoring points relevant and representative for certain parameters of the respective subsystem, each one of the one or more monitoring points is connected with a respective diagnosis module for substantially permanently monitoring the respective monitoring point, and an evaluation unit is connected with each respective diagnosis module for receiving information therefrom about each respective monitoring point, and for evaluating the received information in order to draw conclusions about parameters and properties within the system. The system is preferably used in an automated test equipment system.

Abstract: A semiconductor device having a self-test circuit which has an input signal generating circuit for generating a test signal in synchronization with a prescribed clock signal, a selector circuit for switching between a test mode for testing and a general normal mode and supplying the test signal generated by the input signal generating circuit to the tested circuit in the test mode, a divider circuit for obtaining the output signal from the tested circuit in response to the test signal, a latch circuit for well-timed extraction of the output signal of the tested circuit obtained by testing means, and a comparator for obtaining the output signal of the tested circuit from the latch circuit and comparing it with a prescribed expected value to evaluate.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.

Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (Rsense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT_VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME_VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate. When no backdriving is sensed during a given burst of test signals, the tester forgoes the normal cool-down delay, thereby speeding the test process.

Abstract: A method and apparatus for testing an integrated circuit in a system level environment such that the integrated circuit to be tested is wired into a system or module when the testing occurs is disclosed. In one embodiment of a method aspect of the invention, a die in a packaged integrated circuit to be tested is exposed. A module that incorporates the exposed die is placed on a test platform. The test platform and a sensor probe are relatively positioned such that the sensor probe can directly monitor the exposed die during testing. The positioning may be accomplished by moving the test platform, the sensor probe or both. The system is then driven in a manner which exercises the exposed die. The sensor probe then directly monitor the die while the exposed die is being exercised. The die can be exposed in a variety of manners as for example by removing a package cover or by etching portions of the plastic packaging material.

Abstract: A system for testing a communication network component connected to a computer controlled apparatus via a data link in which the system automatically simulates telephonic communication with the communication network component. Device communication specification information is sent to a translator device at the computer controlled apparatus which automatically parses the received device communication specification to enable development of test tools for the simulation of telephonic communication between the computer controlled apparatus and the communication network component employed as a system under test. The translator in response to receipt of the device communication specification automatically generates a computer software based model to simulate a network entity, test scripts, and user documentation guide.

Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

Abstract: Sample chips are tested after determining the chip layout on a semiconductor wafer so that one or plural ones of untested chips are surrounded by plural ones of the sample chips that adjoin the untested samples. A good/defective judgment on the untested chips is performed by using predicted good/defective judgment results that are statistically predicted based on results of the sample test and stored statistical data of a defect generation profile including address information that indicates defective chip locations. As a result, the good/defective judgment can be performed with high accuracy even in a case where defective chips are localized in a particular region on the wafer in a concentrated manner.

Abstract: A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

Abstract: The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing operand feed forward support in a data processing system (10). In one embodiment, a scan chain (100) may be combined with a feed forward source Y (FFY) bit (64) to allow a user to update registers (50) and memory (18) during emulation and debug. In one embodiment, feed forward control circuitry (60) forces the content of the WBBR register (70) to be used as the Y source operand value for the first instruction to be executed following an update of scan chain (100). This allows debug module (14) to update processor registers (50) and/or memory (18) by initializing the WBBR register (70) with the desired value, asserting the FFY bit (64), and executing a processor (12) move instruction to the desired register in registers (50).

Abstract: An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel testing of other complex functions in a MCU. The MCU has a plurality of test modes that can be selected, with different peripheral pins being connected to a test circuit depending on which test mode is selected. This allows testing of peripherals via their corresponding pins, as well as other complex functions without the necessity of having dedicated test pins.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through a service access port in connection with a predetermined service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interface units to initiate execution of a predetermined service operation.

Abstract: Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (R.sub.sense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT.sub.-- VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME.sub.-- -VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate.

Abstract: A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.

Abstract: A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.